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Contents

README

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PJ71K33SQ

PJSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89

PJ71K33SQ from PJSEMI, in a SOT-89. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference. Common return for both input supply and regulated output. Connect to the single-point ground of the application.
2 VIN power_in Unregulated supply input. Absolute max 28V; recommended operating up to 24V. Bypass with a 10uF capacitor to GND close to the pin.
3 VOUT power_out Regulated 3.3V output (3.135V min, 3.465V max, +/-5%). Sources up to 30mA. Bypass with a 10uF capacitor to GND for stability.

Key specifications

Parameter Value
Manufacturer PJSEMI
Package SOT-89
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • PJ71K33SQ

CAD (KiCad official)

  • Symbol: PJ71K33SQ
  • Footprint: Package_TO_SOT_SMD:SOT-89-3
  • 3D model: SOT-89 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PJSEMI datasheet (7 pp, sha256 132afd6a6872ef7e, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF