component
PJ54BM50SE
Public Made by Adomby adom
PJSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PJ54BM50SE
PJSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
PJ54BM50SE from PJSEMI, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN/EN | power_in | Pin 1 is printed as "VIN/EN" in the pin list, so the datasheet does not clearly assign it; it is the input supply pin, rated VIN to GND -0.3 to +55 V with a 3 to 45 V operating input range, and should be decoupled with a 1 µF ceramic capacitor placed close to the device. |
| 2 | GND | power_in | Ground reference pin; the datasheet recommends a wide copper trace for both VIN and GND and placing the output capacitor as close as possible to VOUT and GND. |
| 3 | EN/VIN | input | Pin 3 is printed as "EN/VIN" in the pin list, so the datasheet does not clearly assign it; the Functional Pin Description defines the EN function as active-high chip enable with a high-impedance input, and EN to GND is rated -0.3 to +55 V. |
| 4 | NC | unconnected | No internal connection; the datasheet lists this pin as "NO Connected". |
| 5 | VOUT | power_out | Regulated output; VOUT to GND is rated -0.3 to +6 V, and the datasheet requires a minimum 10 µF ceramic output capacitor (X7R or X5R) placed close to VOUT and GND for stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PJSEMI |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
CAD (KiCad official)
- Symbol:
PJ54BM50SE - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
pj54bm50se-etched.step/pj54bm50se-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pj54bm50se.step/pj54bm50se.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PJSEMI datasheet (9 pp, sha256
9d606d10633cada4, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PJ54BM50SE
**PJSEMI** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
PJ54BM50SE from PJSEMI, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN/EN | power_in | Pin 1 is printed as "VIN/EN" in the pin list, so the datasheet does not clearly assign it; it is the input supply pin, rated VIN to GND -0.3 to +55 V with a 3 to 45 V operating input range, and should be decoupled with a 1 µF ceramic capacitor placed close to the device. |
| 2 | GND | power_in | Ground reference pin; the datasheet recommends a wide copper trace for both VIN and GND and placing the output capacitor as close as possible to VOUT and GND. |
| 3 | EN/VIN | input | Pin 3 is printed as "EN/VIN" in the pin list, so the datasheet does not clearly assign it; the Functional Pin Description defines the EN function as active-high chip enable with a high-impedance input, and EN to GND is rated -0.3 to +55 V. |
| 4 | NC | unconnected | No internal connection; the datasheet lists this pin as "NO Connected". |
| 5 | VOUT | power_out | Regulated output; VOUT to GND is rated -0.3 to +6 V, and the datasheet requires a minimum 10 µF ceramic output capacitor (X7R or X5R) placed close to VOUT and GND for stability. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PJSEMI |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## CAD (KiCad official)
- Symbol: `PJ54BM50SE`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `pj54bm50se-etched.step` / `pj54bm50se-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pj54bm50se.step` / `pj54bm50se.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [PJSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590923862827606016) (9 pp, sha256 `9d606d10633cada4`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pj54bm50se-datasheet.pdf)