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PIC32MX795F512L-80I
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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-100(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+148docs/hero.pngdocs/pic32mx795f512l-80i-datasheet.pdfpackage.json+744page.json+750pic32mx795f512l-80i-etched.glbpic32mx795f512l-80i-hero.glbpic32mx795f512l-80i-hero.overlay.json+2284pic32mx795f512l-80i.glbpic32mx795f512l-80i.kicad_mod+768pic32mx795f512l-80i.kicad_sym+413pic32mx795f512l-80i.lbr+408pic32mx795f512l-80i.step+19646README.mdadded+148@@ -0,0 +1,148 @@+# PIC32MX795F512L-80I++**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · TQFP-100(12x12)++PIC32MX795F512L-80I from Microchip Tech, in a TQFP-100(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AERXERR/RG15 | bidirectional | PORTG I/O pin RG15 (ST input) that also serves as the alternate Ethernet receive error input AERXERR. |+| 2 | VDD | power_in | Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation. |+| 3 | PMD5/RE5 | bidirectional | PORTE I/O pin RE5 (ST) that also carries Parallel Master Port data bit PMD5 (TTL/ST). |+| 4 | PMD6/RE6 | bidirectional | PORTE I/O pin RE6 (ST) that also carries Parallel Master Port data bit PMD6 (TTL/ST). |+| 5 | PMD7/RE7 | bidirectional | PORTE I/O pin RE7 (ST) that also carries Parallel Master Port data bit PMD7 (TTL/ST). |+| 6 | T2CK/RC1 | bidirectional | PORTC I/O pin RC1 (ST) that also serves as the Timer2 external clock input T2CK. |+| 7 | T3CK/AC2TX/RC2 | bidirectional | PORTC I/O pin RC2 (ST) that also serves as the Timer3 external clock input T3CK and alternate CAN2 transmit AC2TX. |+| 8 | T4CK/AC2RX/RC3 | bidirectional | PORTC I/O pin RC3 (ST) that also serves as the Timer4 external clock input T4CK and alternate CAN2 receive AC2RX (ST). |+| 9 | T5CK/SDI1/RC4 | bidirectional | PORTC I/O pin RC4 (ST) that also serves as the Timer5 external clock input T5CK and SPI1 data input SDI1 (ST). |+| 10 | ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 | bidirectional | PORTG I/O pin RG6 (ST) with change notice CN8, shared with SPI2 clock SCK2, UART6 TX, UART3 RTS, PMP address PMA5 and Ethernet collision input ECOL. |+| 11 | ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 | bidirectional | PORTG I/O pin RG7 (ST) with change notice CN9, shared with I2C4 data SDA4, SPI2 data input SDI2, UART3 RX, PMP address PMA4 and Ethernet carrier sense ECRS. |+| 12 | ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 | bidirectional | PORTG I/O pin RG8 (ST) with change notice CN10, shared with I2C4 clock SCL4, SPI2 data output SDO2, UART3 TX, PMP address PMA3 and Ethernet receive data valid/carrier sense data valid functions. |+| 13 | MCLR | input | Active-low Master Clear input that generates a device Reset when pulled low. |+| 14 | ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 | bidirectional | PORTG I/O pin RG9 (ST) with change notice CN11, shared with Ethernet receive/reference clock functions, SPI2 slave select SS2, UART6 RX, UART3 CTS and PMP address PMA2. |+| 15 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |+| 16 | VDD | power_in | Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation. |+| 17 | TMS/RA0 | bidirectional | PORTA I/O pin RA0 (ST) that also serves as the JTAG test mode select input TMS. |+| 18 | AERXD0/INT1/RE8 | bidirectional | PORTE I/O pin RE8 (ST) that also serves as external interrupt 1 INT1 and alternate Ethernet receive data bit AERXD0 (ST). |+| 19 | AERXD1/INT2/RE9 | bidirectional | PORTE I/O pin RE9 (ST) that also serves as external interrupt 2 INT2 and alternate Ethernet receive data bit AERXD1 (ST). |+| 20 | AN5/C1IN+/VBUSON/CN7/RB5 | bidirectional | PORTB I/O pin RB5 (ST) that also serves as ADC analog input AN5, Comparator 1 positive input C1IN+, and USB VBUSON power control output. |+| 21 | AN4/C1IN-/CN6/RB4 | bidirectional | PORTB I/O pin RB4 (ST) that also serves as ADC analog input AN4 and Comparator 1 negative input C1IN-. |+| 22 | AN3/C2IN+/CN5/RB3 | bidirectional | PORTB I/O pin RB3 (ST) that also serves as ADC analog input AN3 and Comparator 2 positive input C2IN+. |+| 23 | AN2/C2IN-/CN4/RB2 | bidirectional | PORTB I/O pin RB2 (ST) that also serves as ADC analog input AN2 and Comparator 2 negative input C2IN-. |+| 24 | PGEC1/AN1/CN3/RB1 | bidirectional | PORTB I/O pin RB1 (ST) that also serves as ADC analog input AN1 and programming/debug clock input PGEC1 for channel 1. |+| 25 | PGED1/AN0/CN2/RB0 | bidirectional | PORTB I/O pin RB0 (ST) that also serves as ADC analog input AN0 and programming/debug data I/O PGED1 for channel 1. |+| 26 | PGEC2/AN6/OCFA/RB6 | bidirectional | PORTB I/O pin RB6 (ST) that also serves as ADC analog input AN6, Output Compare Fault A input OCFA, and programming/debug clock PGEC2. |+| 27 | PGED2/AN7/RB7 | bidirectional | PORTB I/O pin RB7 (ST) that also serves as ADC analog input AN7 and programming/debug data I/O PGED2. |+| 28 | VREF-/CVREF-/AERXD2/PMA7/RA9 | power_in | PORTA I/O pin RA9 (ST) that also serves as the analog voltage reference (low) input VREF- and comparator reference CVREF-. |+| 29 | VREF+/CVREF+/AERXD3/PMA6/RA10 | power_in | PORTA I/O pin RA10 (ST) that also serves as the analog voltage reference (high) input VREF+ and comparator reference CVREF+. |+| 30 | AVDD | power_in | Positive supply for analog modules; this pin must be connected at all times. |+| 31 | AVSS | power_in | Ground reference for analog modules; this pin must be connected at all times. |+| 32 | AN8/C1OUT/RB8 | bidirectional | PORTB I/O pin RB8 (ST) that also serves as ADC analog input AN8 and Comparator 1 output C1OUT. |+| 33 | AN9/C2OUT/RB9 | bidirectional | PORTB I/O pin RB9 (ST) that also serves as ADC analog input AN9 and Comparator 2 output C2OUT. |+| 34 | AN10/CVREFOUT/PMA13/RB10 | bidirectional | PORTB I/O pin RB10 (ST) that also serves as ADC analog input AN10, comparator voltage reference output CVREFOUT, and PMP address PMA13. |+| 35 | AN11/ERXERR/AETXERR/PMA12/RB11 | bidirectional | PORTB I/O pin RB11 (ST) that also serves as ADC analog input AN11, Ethernet receive error input ERXERR and PMP address PMA12. |+| 36 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |+| 37 | VDD | power_in | Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation. |+| 38 | TCK/RA1 | bidirectional | PORTA I/O pin RA1 (ST) that also serves as the JTAG test clock input TCK. |+| 39 | SCK4/U5TX/U2RTS/RF13 | bidirectional | PORTF I/O pin RF13 (ST) that also serves as SPI4 clock SCK4, UART5 TX and UART2 RTS. |+| 40 | SS4/U5RX/U2CTS/RF12 | bidirectional | PORTF I/O pin RF12 (ST) that also serves as SPI4 slave select SS4, UART5 RX and UART2 CTS. |+| 41 | AN12/ERXD0/AECRS/PMA11/RB12 | bidirectional | PORTB I/O pin RB12 (ST) that also serves as ADC analog input AN12, Ethernet receive data ERXD0 and PMP address PMA11. |+| 42 | AN13/ERXD1/AECOL/PMA10/RB13 | bidirectional | PORTB I/O pin RB13 (ST) that also serves as ADC analog input AN13, Ethernet receive data ERXD1 and PMP address PMA10. |+| 43 | AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 | bidirectional | PORTB I/O pin RB14 (ST) that also serves as ADC analog input AN14, Ethernet receive data ERXD2 and PMP address latch high PMALH. |+| 44 | AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 | bidirectional | PORTB I/O pin RB15 (ST) with change notice CN12 that also serves as ADC analog input AN15, Output Compare Fault B input OCFB and PMP address latch low PMALL. |+| 45 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |+| 46 | VDD | power_in | Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation. |+| 47 | AETXD0/SS3/U4RX/U1CTS/CN20/RD14 | bidirectional | PORTD I/O pin RD14 (ST) with change notice CN20 that also serves as SPI3 slave select SS3, UART4 RX and UART1 CTS. |+| 48 | AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 | bidirectional | PORTD I/O pin RD15 (ST) with change notice CN21 that also serves as SPI3 clock SCK3, UART4 TX and UART1 RTS. |+| 49 | SDA5/SDI4/U2RX/PMA9/CN17/RF4 | bidirectional | PORTF I/O pin RF4 (ST) with change notice CN17 that also serves as I2C5 data SDA5, SPI4 data input SDI4, UART2 RX and PMP address PMA9. |+| 50 | SCL5/SDO4/U2TX/PMA8/CN18/RF5 | bidirectional | PORTF I/O pin RF5 (ST) with change notice CN18 that also serves as I2C5 clock SCL5, SPI4 data output SDO4, UART2 TX and PMP address PMA8. |+| 51 | USBID/RF3 | bidirectional | PORTF I/O pin RF3 (ST) that also serves as the USB OTG ID detect input USBID. |+| 52 | SDA3/SDI3/U1RX/RF2 | bidirectional | PORTF I/O pin RF2 (ST) that also serves as I2C3 data SDA3, SPI3 data input SDI3 and UART1 RX. |+| 53 | SCL3/SDO3/U1TX/RF8 | bidirectional | PORTF I/O pin RF8 (ST) that also serves as I2C3 clock SCL3, SPI3 data output SDO3 and UART1 TX. |+| 54 | VBUS | power_in | USB bus power monitor input (analog). |+| 55 | VUSB3V3 | power_in | USB internal transceiver supply; if the USB module is not used, this pin must be connected to VDD. |+| 56 | D-/RG3 | bidirectional | USB D- data line (analog) shared with PORTG I/O pin RG3 (ST input). |+| 57 | D+/RG2 | bidirectional | USB D+ data line (analog) shared with PORTG I/O pin RG2 (ST input). |+| 58 | SCL2/RA2 | bidirectional | PORTA I/O pin RA2 (ST) that also serves as I2C2 synchronous serial clock SCL2. |+| 59 | SDA2/RA3 | bidirectional | PORTA I/O pin RA3 (ST) that also serves as I2C2 synchronous serial data SDA2. |+| 60 | TDI/RA4 | bidirectional | PORTA I/O pin RA4 (ST) that also serves as the JTAG test data input TDI. |+| 61 | TDO/RA5 | bidirectional | PORTA I/O pin RA5 that also serves as the JTAG test data output TDO. |+| 62 | VDD | power_in | Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation. |+| 63 | OSC1/CLKI/RC12 | bidirectional | Oscillator crystal input OSC1 (ST in RC mode, CMOS otherwise) and external clock input CLKI, shared with PORTC I/O pin RC12 (ST). |+| 64 | OSC2/CLKO/RC15 | bidirectional | Oscillator crystal output OSC2 that connects to a crystal or resonator and optionally functions as CLKO, shared with PORTC I/O pin RC15 (ST). |+| 65 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |+| 66 | AETXCLK/SCL1/INT3/RA14 | bidirectional | PORTA I/O pin RA14 (ST) that also serves as external interrupt 3 INT3, I2C1 clock SCL1 and alternate Ethernet transmit clock AETXCLK (ST). |+| 67 | AETXEN/SDA1/INT4/RA15 | bidirectional | PORTA I/O pin RA15 (ST) that also serves as external interrupt 4 INT4, I2C1 data SDA1 and alternate Ethernet transmit enable AETXEN. |+| 68 | RTCC/EMDIO/AEMDIO/IC1/RD8 | bidirectional | PORTD I/O pin RD8 (ST) that also serves as RTCC alarm output RTCC, Input Capture 1 IC1, and Ethernet management data EMDIO. |+| 69 | SS1/IC2/RD9 | bidirectional | PORTD I/O pin RD9 (ST) that also serves as SPI1 slave select SS1 and Input Capture 2 IC2. |+| 70 | SCK1/IC3/PMCS2/PMA15/RD10 | bidirectional | PORTD I/O pin RD10 (ST) that also serves as SPI1 clock SCK1, Input Capture 3 IC3, PMP chip select 2 PMCS2 and PMP address PMA15. |+| 71 | EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 | bidirectional | PORTD I/O pin RD11 (ST) that also serves as Input Capture 4 IC4, PMP chip select 1 PMCS1, PMP address PMA14 and Ethernet management clock EMDC. |+| 72 | SDO1/OC1/INT0/RD0 | bidirectional | PORTD I/O pin RD0 that also serves as SPI1 data output SDO1, Output Compare 1 output OC1 and external interrupt 0 INT0 (ST). |+| 73 | SOSCI/CN1/RC13 | bidirectional | 32.768 kHz secondary oscillator crystal input SOSCI (ST/CMOS) shared with PORTC I/O pin RC13 (ST) and change notice CN1. |+| 74 | SOSCO/T1CK/CN0/RC14 | bidirectional | 32.768 kHz secondary oscillator crystal output SOSCO shared with PORTC I/O pin RC14 (ST), Timer1 external clock T1CK and change notice CN0. |+| 75 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |+| 76 | OC2/RD1 | bidirectional | PORTD I/O pin RD1 (ST) that also serves as Output Compare 2 output OC2. |+| 77 | OC3/RD2 | bidirectional | PORTD I/O pin RD2 (ST) that also serves as Output Compare 3 output OC3. |+| 78 | OC4/RD3 | bidirectional | PORTD I/O pin RD3 (ST) that also serves as Output Compare 4 output OC4. |+| 79 | ETXD2/IC5/PMD12/RD12 | bidirectional | PORTD I/O pin RD12 (ST) that also serves as Input Capture 5 IC5, PMP data bit PMD12 and Ethernet transmit data ETXD2. |+| 80 | ETXD3/PMD13/CN19/RD13 | bidirectional | PORTD I/O pin RD13 (ST) with change notice CN19 that also serves as PMP data bit PMD13 and Ethernet transmit data ETXD3. |+| 81 | OC5/PMWR/CN13/RD4 | bidirectional | PORTD I/O pin RD4 (ST) with change notice CN13 that also serves as Output Compare 5 output OC5 and PMP write strobe PMWR. |+| 82 | PMRD/CN14/RD5 | bidirectional | PORTD I/O pin RD5 (ST) with change notice CN14 that also serves as the Parallel Master Port read strobe PMRD. |+| 83 | ETXEN/PMD14/CN15/RD6 | bidirectional | PORTD I/O pin RD6 (ST) with change notice CN15 that also serves as PMP data bit PMD14 and Ethernet transmit enable ETXEN. |+| 84 | ETXCLK/PMD15/CN16/RD7 | bidirectional | PORTD I/O pin RD7 (ST) with change notice CN16 that also serves as PMP data bit PMD15 and Ethernet transmit clock ETXCLK (ST). |+| 85 | VCAP/VDDCORE | power_in | Capacitor for the internal voltage regulator; VCAP must not be connected to VDD and requires a low-ESR (about 1 ohm) capacitor rated at least 6V connected to ground. |+| 86 | VDD | power_in | Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation. |+| 87 | C1RX/ETXD1/PMD11/RF0 | bidirectional | PORTF I/O pin RF0 (ST) that also serves as CAN1 receive C1RX (ST), PMP data bit PMD11 and Ethernet transmit data ETXD1. |+| 88 | C1TX/ETXD0/PMD10/RF1 | bidirectional | PORTF I/O pin RF1 (ST) that also serves as CAN1 transmit C1TX, PMP data bit PMD10 and Ethernet transmit data ETXD0. |+| 89 | C2TX/ETXERR/PMD9/RG1 | bidirectional | PORTG I/O pin RG1 (ST) that also serves as CAN2 transmit C2TX, PMP data bit PMD9 and Ethernet transmit error ETXERR. |+| 90 | C2RX/PMD8/RG0 | bidirectional | PORTG I/O pin RG0 (ST) that also serves as CAN2 receive C2RX (ST) and PMP data bit PMD8. |+| 91 | TRCLK/RA6 | bidirectional | PORTA I/O pin RA6 (ST) that also serves as the trace clock output TRCLK. |+| 92 | TRD3/RA7 | bidirectional | PORTA I/O pin RA7 (ST) that also serves as trace data bit 3 output TRD3. |+| 93 | PMD0/RE0 | bidirectional | PORTE I/O pin RE0 (ST) that also carries Parallel Master Port data/address bit PMD0 (TTL/ST). |+| 94 | PMD1/RE1 | bidirectional | PORTE I/O pin RE1 (ST) that also carries Parallel Master Port data/address bit PMD1 (TTL/ST). |+| 95 | TRD2/RG14 | bidirectional | PORTG I/O pin RG14 (ST) that also serves as trace data bit 2 output TRD2. |+| 96 | TRD1/RG12 | bidirectional | PORTG I/O pin RG12 (ST) that also serves as trace data bit 1 output TRD1. |+| 97 | TRD0/RG13 | bidirectional | PORTG I/O pin RG13 (ST) that also serves as trace data bit 0 output TRD0. |+| 98 | PMD2/RE2 | bidirectional | PORTE I/O pin RE2 (ST) that also carries Parallel Master Port data/address bit PMD2 (TTL/ST). |+| 99 | PMD3/RE3 | bidirectional | PORTE I/O pin RE3 (ST) that also carries Parallel Master Port data/address bit PMD3 (TTL/ST). |+| 100 | PMD4/RE4 | bidirectional | PORTE I/O pin RE4 (ST) that also carries Parallel Master Port data/address bit PMD4 (TTL/ST). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Microchip Tech |+| Package | TQFP-100(12x12) |+| Category | Embedded Processors & Controllers |+| Pins | 100 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Supply voltage range (DC5, 80 MHz grade) | VDD | 2.3 | | 3.6 | V | Temp. Range -40°C to +85°C | 356 |+| Max. Frequency | | | | 80 | MHz | VDD 2.3-3.6V, -40°C to +85°C | 356 |+| Operating Junction Temperature Range | TJ | -40 | | 125 | °C | Industrial Temperature Devices | 356 |+| Operating Ambient Temperature Range | TA | -40 | | 85 | °C | Industrial Temperature Devices | 356 |+| Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) | JA | | 43 | | °C/W | Junction to ambient; Note 1: achieved by package simulations | 356 |++## CAD (KiCad official)++- Symbol: `PIC32MX795F512L-80I`+- Footprint: `Package_QFP:TQFP-100_12x12mm_P0.4mm`+- 3D model: TQFP-100(12x12) (KiCad packages3D, STEP)+- 3D model files: `pic32mx795f512l-80i-etched.step` / `pic32mx795f512l-80i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic32mx795f512l-80i.step` / `pic32mx795f512l-80i.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588897949170470912) (446 pp, sha256 `7c0e89419ff7a456`, retrieved 2026-10-18, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/pic32mx795f512l-80i-datasheet.pdf)
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package.jsonadded+744@@ -0,0 +1,744 @@+{+ "slug": "pic32mx795f512l-80i",+ "version": "0.1.0",+ "type": "component",+ "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-100(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "pic32mx795f512l-80i",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "pic32mx795f512l-80i.kicad_sym",+ "pic32mx795f512l-80i.kicad_mod",+ "pic32mx795f512l-80i.glb",+ "pic32mx795f512l-80i.step",+ "pic32mx795f512l-80i.lbr",+ "docs/hero.png",+ "docs/pic32mx795f512l-80i-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "pic32mx795f512l-80i-hero.glb",+ "pic32mx795f512l-80i-hero.overlay.json",+ "pic32mx795f512l-80i-etched.glb"+ ],+ "component": {+ "mpn": "PIC32MX795F512L-80I",+ "manufacturer": "Microchip Tech",+ "package": "TQFP-100(12x12)",+ "pin_count": 100,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588897949170470912",+ "parts": {+ "symbol": "pic32mx795f512l-80i.kicad_sym",+ "footprint": "pic32mx795f512l-80i.kicad_mod",+ "model_3d": "pic32mx795f512l-80i-hero.glb",+ "model_3d_plain": "pic32mx795f512l-80i-etched.glb",+ "model_3d_step": "pic32mx795f512l-80i-etched.step",+ "model_3d_step_plain": "pic32mx795f512l-80i.step",+ "lbr": "pic32mx795f512l-80i.lbr"+ },+ "distributor_links": {+ "lcsc": "C2832751"+ },+ "distributor_check": {+ "checked_at": "2026-10-18T22:06:48Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "quota"+ },+ "mouser": {+ "pn": null,+ "status": "quota"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "AERXERR/RG15",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG15 (ST input) that also serves as the alternate Ethernet receive error input AERXERR."+ },+ {+ "number": "2",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "3",+ "name": "PMD5/RE5",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE5 (ST) that also carries Parallel Master Port data bit PMD5 (TTL/ST)."+ },+ {+ "number": "4",+ "name": "PMD6/RE6",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE6 (ST) that also carries Parallel Master Port data bit PMD6 (TTL/ST)."+ },+ {+ "number": "5",+ "name": "PMD7/RE7",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE7 (ST) that also carries Parallel Master Port data bit PMD7 (TTL/ST)."+ },+ {+ "number": "6",+ "name": "T2CK/RC1",+ "type": "bidirectional",+ "description": "PORTC I/O pin RC1 (ST) that also serves as the Timer2 external clock input T2CK."+ },+ {+ "number": "7",+ "name": "T3CK/AC2TX/RC2",+ "type": "bidirectional",+ "description": "PORTC I/O pin RC2 (ST) that also serves as the Timer3 external clock input T3CK and alternate CAN2 transmit AC2TX."+ },+ {+ "number": "8",+ "name": "T4CK/AC2RX/RC3",+ "type": "bidirectional",+ "description": "PORTC I/O pin RC3 (ST) that also serves as the Timer4 external clock input T4CK and alternate CAN2 receive AC2RX (ST)."+ },+ {+ "number": "9",+ "name": "T5CK/SDI1/RC4",+ "type": "bidirectional",+ "description": "PORTC I/O pin RC4 (ST) that also serves as the Timer5 external clock input T5CK and SPI1 data input SDI1 (ST)."+ },+ {+ "number": "10",+ "name": "ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG6 (ST) with change notice CN8, shared with SPI2 clock SCK2, UART6 TX, UART3 RTS, PMP address PMA5 and Ethernet collision input ECOL."+ },+ {+ "number": "11",+ "name": "ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG7 (ST) with change notice CN9, shared with I2C4 data SDA4, SPI2 data input SDI2, UART3 RX, PMP address PMA4 and Ethernet carrier sense ECRS."+ },+ {+ "number": "12",+ "name": "ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG8 (ST) with change notice CN10, shared with I2C4 clock SCL4, SPI2 data output SDO2, UART3 TX, PMP address PMA3 and Ethernet receive data valid/carrier sense data valid functions."+ },+ {+ "number": "13",+ "name": "MCLR",+ "type": "input",+ "description": "Active-low Master Clear input that generates a device Reset when pulled low."+ },+ {+ "number": "14",+ "name": "ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG9 (ST) with change notice CN11, shared with Ethernet receive/reference clock functions, SPI2 slave select SS2, UART6 RX, UART3 CTS and PMP address PMA2."+ },+ {+ "number": "15",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "17",+ "name": "TMS/RA0",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA0 (ST) that also serves as the JTAG test mode select input TMS."+ },+ {+ "number": "18",+ "name": "AERXD0/INT1/RE8",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE8 (ST) that also serves as external interrupt 1 INT1 and alternate Ethernet receive data bit AERXD0 (ST)."+ },+ {+ "number": "19",+ "name": "AERXD1/INT2/RE9",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE9 (ST) that also serves as external interrupt 2 INT2 and alternate Ethernet receive data bit AERXD1 (ST)."+ },+ {+ "number": "20",+ "name": "AN5/C1IN+/VBUSON/CN7/RB5",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB5 (ST) that also serves as ADC analog input AN5, Comparator 1 positive input C1IN+, and USB VBUSON power control output."+ },+ {+ "number": "21",+ "name": "AN4/C1IN-/CN6/RB4",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB4 (ST) that also serves as ADC analog input AN4 and Comparator 1 negative input C1IN-."+ },+ {+ "number": "22",+ "name": "AN3/C2IN+/CN5/RB3",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB3 (ST) that also serves as ADC analog input AN3 and Comparator 2 positive input C2IN+."+ },+ {+ "number": "23",+ "name": "AN2/C2IN-/CN4/RB2",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB2 (ST) that also serves as ADC analog input AN2 and Comparator 2 negative input C2IN-."+ },+ {+ "number": "24",+ "name": "PGEC1/AN1/CN3/RB1",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB1 (ST) that also serves as ADC analog input AN1 and programming/debug clock input PGEC1 for channel 1."+ },+ {+ "number": "25",+ "name": "PGED1/AN0/CN2/RB0",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB0 (ST) that also serves as ADC analog input AN0 and programming/debug data I/O PGED1 for channel 1."+ },+ {+ "number": "26",+ "name": "PGEC2/AN6/OCFA/RB6",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB6 (ST) that also serves as ADC analog input AN6, Output Compare Fault A input OCFA, and programming/debug clock PGEC2."+ },+ {+ "number": "27",+ "name": "PGED2/AN7/RB7",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB7 (ST) that also serves as ADC analog input AN7 and programming/debug data I/O PGED2."+ },+ {+ "number": "28",+ "name": "VREF-/CVREF-/AERXD2/PMA7/RA9",+ "type": "power_in",+ "description": "PORTA I/O pin RA9 (ST) that also serves as the analog voltage reference (low) input VREF- and comparator reference CVREF-."+ },+ {+ "number": "29",+ "name": "VREF+/CVREF+/AERXD3/PMA6/RA10",+ "type": "power_in",+ "description": "PORTA I/O pin RA10 (ST) that also serves as the analog voltage reference (high) input VREF+ and comparator reference CVREF+."+ },+ {+ "number": "30",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive supply for analog modules; this pin must be connected at all times."+ },+ {+ "number": "31",+ "name": "AVSS",+ "type": "power_in",+ "description": "Ground reference for analog modules; this pin must be connected at all times."+ },+ {+ "number": "32",+ "name": "AN8/C1OUT/RB8",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB8 (ST) that also serves as ADC analog input AN8 and Comparator 1 output C1OUT."+ },+ {+ "number": "33",+ "name": "AN9/C2OUT/RB9",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB9 (ST) that also serves as ADC analog input AN9 and Comparator 2 output C2OUT."+ },+ {+ "number": "34",+ "name": "AN10/CVREFOUT/PMA13/RB10",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB10 (ST) that also serves as ADC analog input AN10, comparator voltage reference output CVREFOUT, and PMP address PMA13."+ },+ {+ "number": "35",+ "name": "AN11/ERXERR/AETXERR/PMA12/RB11",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB11 (ST) that also serves as ADC analog input AN11, Ethernet receive error input ERXERR and PMP address PMA12."+ },+ {+ "number": "36",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "37",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "38",+ "name": "TCK/RA1",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA1 (ST) that also serves as the JTAG test clock input TCK."+ },+ {+ "number": "39",+ "name": "SCK4/U5TX/U2RTS/RF13",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF13 (ST) that also serves as SPI4 clock SCK4, UART5 TX and UART2 RTS."+ },+ {+ "number": "40",+ "name": "SS4/U5RX/U2CTS/RF12",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF12 (ST) that also serves as SPI4 slave select SS4, UART5 RX and UART2 CTS."+ },+ {+ "number": "41",+ "name": "AN12/ERXD0/AECRS/PMA11/RB12",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB12 (ST) that also serves as ADC analog input AN12, Ethernet receive data ERXD0 and PMP address PMA11."+ },+ {+ "number": "42",+ "name": "AN13/ERXD1/AECOL/PMA10/RB13",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB13 (ST) that also serves as ADC analog input AN13, Ethernet receive data ERXD1 and PMP address PMA10."+ },+ {+ "number": "43",+ "name": "AN14/ERXD2/AETXD3/PMALH/PMA1/RB14",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB14 (ST) that also serves as ADC analog input AN14, Ethernet receive data ERXD2 and PMP address latch high PMALH."+ },+ {+ "number": "44",+ "name": "AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB15 (ST) with change notice CN12 that also serves as ADC analog input AN15, Output Compare Fault B input OCFB and PMP address latch low PMALL."+ },+ {+ "number": "45",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "46",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "47",+ "name": "AETXD0/SS3/U4RX/U1CTS/CN20/RD14",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD14 (ST) with change notice CN20 that also serves as SPI3 slave select SS3, UART4 RX and UART1 CTS."+ },+ {+ "number": "48",+ "name": "AETXD1/SCK3/U4TX/U1RTS/CN21/RD15",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD15 (ST) with change notice CN21 that also serves as SPI3 clock SCK3, UART4 TX and UART1 RTS."+ },+ {+ "number": "49",+ "name": "SDA5/SDI4/U2RX/PMA9/CN17/RF4",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF4 (ST) with change notice CN17 that also serves as I2C5 data SDA5, SPI4 data input SDI4, UART2 RX and PMP address PMA9."+ },+ {+ "number": "50",+ "name": "SCL5/SDO4/U2TX/PMA8/CN18/RF5",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF5 (ST) with change notice CN18 that also serves as I2C5 clock SCL5, SPI4 data output SDO4, UART2 TX and PMP address PMA8."+ },+ {+ "number": "51",+ "name": "USBID/RF3",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF3 (ST) that also serves as the USB OTG ID detect input USBID."+ },+ {+ "number": "52",+ "name": "SDA3/SDI3/U1RX/RF2",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF2 (ST) that also serves as I2C3 data SDA3, SPI3 data input SDI3 and UART1 RX."+ },+ {+ "number": "53",+ "name": "SCL3/SDO3/U1TX/RF8",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF8 (ST) that also serves as I2C3 clock SCL3, SPI3 data output SDO3 and UART1 TX."+ },+ {+ "number": "54",+ "name": "VBUS",+ "type": "power_in",+ "description": "USB bus power monitor input (analog)."+ },+ {+ "number": "55",+ "name": "VUSB3V3",+ "type": "power_in",+ "description": "USB internal transceiver supply; if the USB module is not used, this pin must be connected to VDD."+ },+ {+ "number": "56",+ "name": "D-/RG3",+ "type": "bidirectional",+ "description": "USB D- data line (analog) shared with PORTG I/O pin RG3 (ST input)."+ },+ {+ "number": "57",+ "name": "D+/RG2",+ "type": "bidirectional",+ "description": "USB D+ data line (analog) shared with PORTG I/O pin RG2 (ST input)."+ },+ {+ "number": "58",+ "name": "SCL2/RA2",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA2 (ST) that also serves as I2C2 synchronous serial clock SCL2."+ },+ {+ "number": "59",+ "name": "SDA2/RA3",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA3 (ST) that also serves as I2C2 synchronous serial data SDA2."+ },+ {+ "number": "60",+ "name": "TDI/RA4",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA4 (ST) that also serves as the JTAG test data input TDI."+ },+ {+ "number": "61",+ "name": "TDO/RA5",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA5 that also serves as the JTAG test data output TDO."+ },+ {+ "number": "62",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "63",+ "name": "OSC1/CLKI/RC12",+ "type": "bidirectional",+ "description": "Oscillator crystal input OSC1 (ST in RC mode, CMOS otherwise) and external clock input CLKI, shared with PORTC I/O pin RC12 (ST)."+ },+ {+ "number": "64",+ "name": "OSC2/CLKO/RC15",+ "type": "bidirectional",+ "description": "Oscillator crystal output OSC2 that connects to a crystal or resonator and optionally functions as CLKO, shared with PORTC I/O pin RC15 (ST)."+ },+ {+ "number": "65",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "66",+ "name": "AETXCLK/SCL1/INT3/RA14",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA14 (ST) that also serves as external interrupt 3 INT3, I2C1 clock SCL1 and alternate Ethernet transmit clock AETXCLK (ST)."+ },+ {+ "number": "67",+ "name": "AETXEN/SDA1/INT4/RA15",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA15 (ST) that also serves as external interrupt 4 INT4, I2C1 data SDA1 and alternate Ethernet transmit enable AETXEN."+ },+ {+ "number": "68",+ "name": "RTCC/EMDIO/AEMDIO/IC1/RD8",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD8 (ST) that also serves as RTCC alarm output RTCC, Input Capture 1 IC1, and Ethernet management data EMDIO."+ },+ {+ "number": "69",+ "name": "SS1/IC2/RD9",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD9 (ST) that also serves as SPI1 slave select SS1 and Input Capture 2 IC2."+ },+ {+ "number": "70",+ "name": "SCK1/IC3/PMCS2/PMA15/RD10",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD10 (ST) that also serves as SPI1 clock SCK1, Input Capture 3 IC3, PMP chip select 2 PMCS2 and PMP address PMA15."+ },+ {+ "number": "71",+ "name": "EMDC/AEMDC/IC4/PMCS1/PMA14/RD11",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD11 (ST) that also serves as Input Capture 4 IC4, PMP chip select 1 PMCS1, PMP address PMA14 and Ethernet management clock EMDC."+ },+ {+ "number": "72",+ "name": "SDO1/OC1/INT0/RD0",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD0 that also serves as SPI1 data output SDO1, Output Compare 1 output OC1 and external interrupt 0 INT0 (ST)."+ },+ {+ "number": "73",+ "name": "SOSCI/CN1/RC13",+ "type": "bidirectional",+ "description": "32.768 kHz secondary oscillator crystal input SOSCI (ST/CMOS) shared with PORTC I/O pin RC13 (ST) and change notice CN1."+ },+ {+ "number": "74",+ "name": "SOSCO/T1CK/CN0/RC14",+ "type": "bidirectional",+ "description": "32.768 kHz secondary oscillator crystal output SOSCO shared with PORTC I/O pin RC14 (ST), Timer1 external clock T1CK and change notice CN0."+ },+ {+ "number": "75",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "76",+ "name": "OC2/RD1",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD1 (ST) that also serves as Output Compare 2 output OC2."+ },+ {+ "number": "77",+ "name": "OC3/RD2",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD2 (ST) that also serves as Output Compare 3 output OC3."+ },+ {+ "number": "78",+ "name": "OC4/RD3",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD3 (ST) that also serves as Output Compare 4 output OC4."+ },+ {+ "number": "79",+ "name": "ETXD2/IC5/PMD12/RD12",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD12 (ST) that also serves as Input Capture 5 IC5, PMP data bit PMD12 and Ethernet transmit data ETXD2."+ },+ {+ "number": "80",+ "name": "ETXD3/PMD13/CN19/RD13",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD13 (ST) with change notice CN19 that also serves as PMP data bit PMD13 and Ethernet transmit data ETXD3."+ },+ {+ "number": "81",+ "name": "OC5/PMWR/CN13/RD4",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD4 (ST) with change notice CN13 that also serves as Output Compare 5 output OC5 and PMP write strobe PMWR."+ },+ {+ "number": "82",+ "name": "PMRD/CN14/RD5",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD5 (ST) with change notice CN14 that also serves as the Parallel Master Port read strobe PMRD."+ },+ {+ "number": "83",+ "name": "ETXEN/PMD14/CN15/RD6",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD6 (ST) with change notice CN15 that also serves as PMP data bit PMD14 and Ethernet transmit enable ETXEN."+ },+ {+ "number": "84",+ "name": "ETXCLK/PMD15/CN16/RD7",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD7 (ST) with change notice CN16 that also serves as PMP data bit PMD15 and Ethernet transmit clock ETXCLK (ST)."+ },+ {+ "number": "85",+ "name": "VCAP/VDDCORE",+ "type": "power_in",+ "description": "Capacitor for the internal voltage regulator; VCAP must not be connected to VDD and requires a low-ESR (about 1 ohm) capacitor rated at least 6V connected to ground."+ },+ {+ "number": "86",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "87",+ "name": "C1RX/ETXD1/PMD11/RF0",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF0 (ST) that also serves as CAN1 receive C1RX (ST), PMP data bit PMD11 and Ethernet transmit data ETXD1."+ },+ {+ "number": "88",+ "name": "C1TX/ETXD0/PMD10/RF1",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF1 (ST) that also serves as CAN1 transmit C1TX, PMP data bit PMD10 and Ethernet transmit data ETXD0."+ },+ {+ "number": "89",+ "name": "C2TX/ETXERR/PMD9/RG1",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG1 (ST) that also serves as CAN2 transmit C2TX, PMP data bit PMD9 and Ethernet transmit error ETXERR."+ },+ {+ "number": "90",+ "name": "C2RX/PMD8/RG0",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG0 (ST) that also serves as CAN2 receive C2RX (ST) and PMP data bit PMD8."+ },+ {+ "number": "91",+ "name": "TRCLK/RA6",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA6 (ST) that also serves as the trace clock output TRCLK."+ },+ {+ "number": "92",+ "name": "TRD3/RA7",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA7 (ST) that also serves as trace data bit 3 output TRD3."+ },+ {+ "number": "93",+ "name": "PMD0/RE0",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE0 (ST) that also carries Parallel Master Port data/address bit PMD0 (TTL/ST)."+ },+ {+ "number": "94",+ "name": "PMD1/RE1",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE1 (ST) that also carries Parallel Master Port data/address bit PMD1 (TTL/ST)."+ },+ {+ "number": "95",+ "name": "TRD2/RG14",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG14 (ST) that also serves as trace data bit 2 output TRD2."+ },+ {+ "number": "96",+ "name": "TRD1/RG12",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG12 (ST) that also serves as trace data bit 1 output TRD1."+ },+ {+ "number": "97",+ "name": "TRD0/RG13",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG13 (ST) that also serves as trace data bit 0 output TRD0."+ },+ {+ "number": "98",+ "name": "PMD2/RE2",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE2 (ST) that also carries Parallel Master Port data/address bit PMD2 (TTL/ST)."+ },+ {+ "number": "99",+ "name": "PMD3/RE3",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE3 (ST) that also carries Parallel Master Port data/address bit PMD3 (TTL/ST)."+ },+ {+ "number": "100",+ "name": "PMD4/RE4",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE4 (ST) that also carries Parallel Master Port data/address bit PMD4 (TTL/ST)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package selection: PIC32MX795F512L is listed in the 100-pin USB, Ethernet and CAN pin table (Table 9; Footnote markers were removed from pin names (e.g. AC2TX(1), AC2RX(1), C2TX(1), C2RX(1)). Footnote 1; Pin 85 is printed as VCAP/VDDCORE in Table 9. Table 1-1 (page 33) lists it as VCAP, and the revision"+ ],+ "pages_sent": 74,+ "cost_usd": 0.4373,+ "at": "2026-10-18T22:06:16"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588897949170470912",+ "pages": 446,+ "sha256": "7c0e89419ff7a456",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 100,+ "described": 100,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "pic32mx795f512l-80i.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14.0,+ 14.0,+ 1.1+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "eec53eae666dfb8fe1a37fcc11f81298b0e0fa9cf31f3fa1ae15fa87f47baf70",+ "checked": "2026-10-18",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "pic32mx795f512l-80i-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14.0,+ 14.0,+ 1.1+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "dca3056738e9b0e30458fdf79518d422ae05519521fa053d6f0bc3564e30a11e",+ "checked": "2026-10-18",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ }+}
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "pic32mx795f512l-80i",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "pic32mx795f512l-80i.kicad_sym",+ "pic32mx795f512l-80i.kicad_mod",+ "pic32mx795f512l-80i.glb",+ "pic32mx795f512l-80i.step",+ "pic32mx795f512l-80i.lbr",+ "docs/hero.png",+ "docs/pic32mx795f512l-80i-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "pic32mx795f512l-80i-hero.glb",+ "pic32mx795f512l-80i-hero.overlay.json",+ "pic32mx795f512l-80i-etched.glb"+ ],+ "component": {+ "mpn": "PIC32MX795F512L-80I",+ "manufacturer": "Microchip Tech",+ "package": "TQFP-100(12x12)",+ "pin_count": 100,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588897949170470912",+ "parts": {+ "symbol": "pic32mx795f512l-80i.kicad_sym",+ "footprint": "pic32mx795f512l-80i.kicad_mod",+ "model_3d": "pic32mx795f512l-80i-hero.glb",+ "model_3d_plain": "pic32mx795f512l-80i-etched.glb",+ "model_3d_step": "pic32mx795f512l-80i-etched.step",+ "model_3d_step_plain": "pic32mx795f512l-80i.step",+ "lbr": "pic32mx795f512l-80i.lbr"+ },+ "distributor_links": {+ "lcsc": "C2832751"+ },+ "distributor_check": {+ "checked_at": "2026-10-18T22:06:48Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "quota"+ },+ "mouser": {+ "pn": null,+ "status": "quota"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "AERXERR/RG15",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG15 (ST input) that also serves as the alternate Ethernet receive error input AERXERR."+ },+ {+ "number": "2",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "3",+ "name": "PMD5/RE5",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE5 (ST) that also carries Parallel Master Port data bit PMD5 (TTL/ST)."+ },+ {+ "number": "4",+ "name": "PMD6/RE6",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE6 (ST) that also carries Parallel Master Port data bit PMD6 (TTL/ST)."+ },+ {+ "number": "5",+ "name": "PMD7/RE7",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE7 (ST) that also carries Parallel Master Port data bit PMD7 (TTL/ST)."+ },+ {+ "number": "6",+ "name": "T2CK/RC1",+ "type": "bidirectional",+ "description": "PORTC I/O pin RC1 (ST) that also serves as the Timer2 external clock input T2CK."+ },+ {+ "number": "7",+ "name": "T3CK/AC2TX/RC2",+ "type": "bidirectional",+ "description": "PORTC I/O pin RC2 (ST) that also serves as the Timer3 external clock input T3CK and alternate CAN2 transmit AC2TX."+ },+ {+ "number": "8",+ "name": "T4CK/AC2RX/RC3",+ "type": "bidirectional",+ "description": "PORTC I/O pin RC3 (ST) that also serves as the Timer4 external clock input T4CK and alternate CAN2 receive AC2RX (ST)."+ },+ {+ "number": "9",+ "name": "T5CK/SDI1/RC4",+ "type": "bidirectional",+ "description": "PORTC I/O pin RC4 (ST) that also serves as the Timer5 external clock input T5CK and SPI1 data input SDI1 (ST)."+ },+ {+ "number": "10",+ "name": "ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG6 (ST) with change notice CN8, shared with SPI2 clock SCK2, UART6 TX, UART3 RTS, PMP address PMA5 and Ethernet collision input ECOL."+ },+ {+ "number": "11",+ "name": "ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG7 (ST) with change notice CN9, shared with I2C4 data SDA4, SPI2 data input SDI2, UART3 RX, PMP address PMA4 and Ethernet carrier sense ECRS."+ },+ {+ "number": "12",+ "name": "ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG8 (ST) with change notice CN10, shared with I2C4 clock SCL4, SPI2 data output SDO2, UART3 TX, PMP address PMA3 and Ethernet receive data valid/carrier sense data valid functions."+ },+ {+ "number": "13",+ "name": "MCLR",+ "type": "input",+ "description": "Active-low Master Clear input that generates a device Reset when pulled low."+ },+ {+ "number": "14",+ "name": "ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG9 (ST) with change notice CN11, shared with Ethernet receive/reference clock functions, SPI2 slave select SS2, UART6 RX, UART3 CTS and PMP address PMA2."+ },+ {+ "number": "15",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "17",+ "name": "TMS/RA0",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA0 (ST) that also serves as the JTAG test mode select input TMS."+ },+ {+ "number": "18",+ "name": "AERXD0/INT1/RE8",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE8 (ST) that also serves as external interrupt 1 INT1 and alternate Ethernet receive data bit AERXD0 (ST)."+ },+ {+ "number": "19",+ "name": "AERXD1/INT2/RE9",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE9 (ST) that also serves as external interrupt 2 INT2 and alternate Ethernet receive data bit AERXD1 (ST)."+ },+ {+ "number": "20",+ "name": "AN5/C1IN+/VBUSON/CN7/RB5",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB5 (ST) that also serves as ADC analog input AN5, Comparator 1 positive input C1IN+, and USB VBUSON power control output."+ },+ {+ "number": "21",+ "name": "AN4/C1IN-/CN6/RB4",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB4 (ST) that also serves as ADC analog input AN4 and Comparator 1 negative input C1IN-."+ },+ {+ "number": "22",+ "name": "AN3/C2IN+/CN5/RB3",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB3 (ST) that also serves as ADC analog input AN3 and Comparator 2 positive input C2IN+."+ },+ {+ "number": "23",+ "name": "AN2/C2IN-/CN4/RB2",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB2 (ST) that also serves as ADC analog input AN2 and Comparator 2 negative input C2IN-."+ },+ {+ "number": "24",+ "name": "PGEC1/AN1/CN3/RB1",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB1 (ST) that also serves as ADC analog input AN1 and programming/debug clock input PGEC1 for channel 1."+ },+ {+ "number": "25",+ "name": "PGED1/AN0/CN2/RB0",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB0 (ST) that also serves as ADC analog input AN0 and programming/debug data I/O PGED1 for channel 1."+ },+ {+ "number": "26",+ "name": "PGEC2/AN6/OCFA/RB6",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB6 (ST) that also serves as ADC analog input AN6, Output Compare Fault A input OCFA, and programming/debug clock PGEC2."+ },+ {+ "number": "27",+ "name": "PGED2/AN7/RB7",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB7 (ST) that also serves as ADC analog input AN7 and programming/debug data I/O PGED2."+ },+ {+ "number": "28",+ "name": "VREF-/CVREF-/AERXD2/PMA7/RA9",+ "type": "power_in",+ "description": "PORTA I/O pin RA9 (ST) that also serves as the analog voltage reference (low) input VREF- and comparator reference CVREF-."+ },+ {+ "number": "29",+ "name": "VREF+/CVREF+/AERXD3/PMA6/RA10",+ "type": "power_in",+ "description": "PORTA I/O pin RA10 (ST) that also serves as the analog voltage reference (high) input VREF+ and comparator reference CVREF+."+ },+ {+ "number": "30",+ "name": "AVDD",+ "type": "power_in",+ "description": "Positive supply for analog modules; this pin must be connected at all times."+ },+ {+ "number": "31",+ "name": "AVSS",+ "type": "power_in",+ "description": "Ground reference for analog modules; this pin must be connected at all times."+ },+ {+ "number": "32",+ "name": "AN8/C1OUT/RB8",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB8 (ST) that also serves as ADC analog input AN8 and Comparator 1 output C1OUT."+ },+ {+ "number": "33",+ "name": "AN9/C2OUT/RB9",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB9 (ST) that also serves as ADC analog input AN9 and Comparator 2 output C2OUT."+ },+ {+ "number": "34",+ "name": "AN10/CVREFOUT/PMA13/RB10",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB10 (ST) that also serves as ADC analog input AN10, comparator voltage reference output CVREFOUT, and PMP address PMA13."+ },+ {+ "number": "35",+ "name": "AN11/ERXERR/AETXERR/PMA12/RB11",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB11 (ST) that also serves as ADC analog input AN11, Ethernet receive error input ERXERR and PMP address PMA12."+ },+ {+ "number": "36",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "37",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "38",+ "name": "TCK/RA1",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA1 (ST) that also serves as the JTAG test clock input TCK."+ },+ {+ "number": "39",+ "name": "SCK4/U5TX/U2RTS/RF13",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF13 (ST) that also serves as SPI4 clock SCK4, UART5 TX and UART2 RTS."+ },+ {+ "number": "40",+ "name": "SS4/U5RX/U2CTS/RF12",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF12 (ST) that also serves as SPI4 slave select SS4, UART5 RX and UART2 CTS."+ },+ {+ "number": "41",+ "name": "AN12/ERXD0/AECRS/PMA11/RB12",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB12 (ST) that also serves as ADC analog input AN12, Ethernet receive data ERXD0 and PMP address PMA11."+ },+ {+ "number": "42",+ "name": "AN13/ERXD1/AECOL/PMA10/RB13",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB13 (ST) that also serves as ADC analog input AN13, Ethernet receive data ERXD1 and PMP address PMA10."+ },+ {+ "number": "43",+ "name": "AN14/ERXD2/AETXD3/PMALH/PMA1/RB14",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB14 (ST) that also serves as ADC analog input AN14, Ethernet receive data ERXD2 and PMP address latch high PMALH."+ },+ {+ "number": "44",+ "name": "AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15",+ "type": "bidirectional",+ "description": "PORTB I/O pin RB15 (ST) with change notice CN12 that also serves as ADC analog input AN15, Output Compare Fault B input OCFB and PMP address latch low PMALL."+ },+ {+ "number": "45",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "46",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "47",+ "name": "AETXD0/SS3/U4RX/U1CTS/CN20/RD14",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD14 (ST) with change notice CN20 that also serves as SPI3 slave select SS3, UART4 RX and UART1 CTS."+ },+ {+ "number": "48",+ "name": "AETXD1/SCK3/U4TX/U1RTS/CN21/RD15",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD15 (ST) with change notice CN21 that also serves as SPI3 clock SCK3, UART4 TX and UART1 RTS."+ },+ {+ "number": "49",+ "name": "SDA5/SDI4/U2RX/PMA9/CN17/RF4",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF4 (ST) with change notice CN17 that also serves as I2C5 data SDA5, SPI4 data input SDI4, UART2 RX and PMP address PMA9."+ },+ {+ "number": "50",+ "name": "SCL5/SDO4/U2TX/PMA8/CN18/RF5",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF5 (ST) with change notice CN18 that also serves as I2C5 clock SCL5, SPI4 data output SDO4, UART2 TX and PMP address PMA8."+ },+ {+ "number": "51",+ "name": "USBID/RF3",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF3 (ST) that also serves as the USB OTG ID detect input USBID."+ },+ {+ "number": "52",+ "name": "SDA3/SDI3/U1RX/RF2",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF2 (ST) that also serves as I2C3 data SDA3, SPI3 data input SDI3 and UART1 RX."+ },+ {+ "number": "53",+ "name": "SCL3/SDO3/U1TX/RF8",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF8 (ST) that also serves as I2C3 clock SCL3, SPI3 data output SDO3 and UART1 TX."+ },+ {+ "number": "54",+ "name": "VBUS",+ "type": "power_in",+ "description": "USB bus power monitor input (analog)."+ },+ {+ "number": "55",+ "name": "VUSB3V3",+ "type": "power_in",+ "description": "USB internal transceiver supply; if the USB module is not used, this pin must be connected to VDD."+ },+ {+ "number": "56",+ "name": "D-/RG3",+ "type": "bidirectional",+ "description": "USB D- data line (analog) shared with PORTG I/O pin RG3 (ST input)."+ },+ {+ "number": "57",+ "name": "D+/RG2",+ "type": "bidirectional",+ "description": "USB D+ data line (analog) shared with PORTG I/O pin RG2 (ST input)."+ },+ {+ "number": "58",+ "name": "SCL2/RA2",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA2 (ST) that also serves as I2C2 synchronous serial clock SCL2."+ },+ {+ "number": "59",+ "name": "SDA2/RA3",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA3 (ST) that also serves as I2C2 synchronous serial data SDA2."+ },+ {+ "number": "60",+ "name": "TDI/RA4",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA4 (ST) that also serves as the JTAG test data input TDI."+ },+ {+ "number": "61",+ "name": "TDO/RA5",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA5 that also serves as the JTAG test data output TDO."+ },+ {+ "number": "62",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "63",+ "name": "OSC1/CLKI/RC12",+ "type": "bidirectional",+ "description": "Oscillator crystal input OSC1 (ST in RC mode, CMOS otherwise) and external clock input CLKI, shared with PORTC I/O pin RC12 (ST)."+ },+ {+ "number": "64",+ "name": "OSC2/CLKO/RC15",+ "type": "bidirectional",+ "description": "Oscillator crystal output OSC2 that connects to a crystal or resonator and optionally functions as CLKO, shared with PORTC I/O pin RC15 (ST)."+ },+ {+ "number": "65",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "66",+ "name": "AETXCLK/SCL1/INT3/RA14",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA14 (ST) that also serves as external interrupt 3 INT3, I2C1 clock SCL1 and alternate Ethernet transmit clock AETXCLK (ST)."+ },+ {+ "number": "67",+ "name": "AETXEN/SDA1/INT4/RA15",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA15 (ST) that also serves as external interrupt 4 INT4, I2C1 data SDA1 and alternate Ethernet transmit enable AETXEN."+ },+ {+ "number": "68",+ "name": "RTCC/EMDIO/AEMDIO/IC1/RD8",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD8 (ST) that also serves as RTCC alarm output RTCC, Input Capture 1 IC1, and Ethernet management data EMDIO."+ },+ {+ "number": "69",+ "name": "SS1/IC2/RD9",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD9 (ST) that also serves as SPI1 slave select SS1 and Input Capture 2 IC2."+ },+ {+ "number": "70",+ "name": "SCK1/IC3/PMCS2/PMA15/RD10",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD10 (ST) that also serves as SPI1 clock SCK1, Input Capture 3 IC3, PMP chip select 2 PMCS2 and PMP address PMA15."+ },+ {+ "number": "71",+ "name": "EMDC/AEMDC/IC4/PMCS1/PMA14/RD11",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD11 (ST) that also serves as Input Capture 4 IC4, PMP chip select 1 PMCS1, PMP address PMA14 and Ethernet management clock EMDC."+ },+ {+ "number": "72",+ "name": "SDO1/OC1/INT0/RD0",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD0 that also serves as SPI1 data output SDO1, Output Compare 1 output OC1 and external interrupt 0 INT0 (ST)."+ },+ {+ "number": "73",+ "name": "SOSCI/CN1/RC13",+ "type": "bidirectional",+ "description": "32.768 kHz secondary oscillator crystal input SOSCI (ST/CMOS) shared with PORTC I/O pin RC13 (ST) and change notice CN1."+ },+ {+ "number": "74",+ "name": "SOSCO/T1CK/CN0/RC14",+ "type": "bidirectional",+ "description": "32.768 kHz secondary oscillator crystal output SOSCO shared with PORTC I/O pin RC14 (ST), Timer1 external clock T1CK and change notice CN0."+ },+ {+ "number": "75",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins; must be connected at all times."+ },+ {+ "number": "76",+ "name": "OC2/RD1",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD1 (ST) that also serves as Output Compare 2 output OC2."+ },+ {+ "number": "77",+ "name": "OC3/RD2",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD2 (ST) that also serves as Output Compare 3 output OC3."+ },+ {+ "number": "78",+ "name": "OC4/RD3",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD3 (ST) that also serves as Output Compare 4 output OC4."+ },+ {+ "number": "79",+ "name": "ETXD2/IC5/PMD12/RD12",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD12 (ST) that also serves as Input Capture 5 IC5, PMP data bit PMD12 and Ethernet transmit data ETXD2."+ },+ {+ "number": "80",+ "name": "ETXD3/PMD13/CN19/RD13",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD13 (ST) with change notice CN19 that also serves as PMP data bit PMD13 and Ethernet transmit data ETXD3."+ },+ {+ "number": "81",+ "name": "OC5/PMWR/CN13/RD4",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD4 (ST) with change notice CN13 that also serves as Output Compare 5 output OC5 and PMP write strobe PMWR."+ },+ {+ "number": "82",+ "name": "PMRD/CN14/RD5",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD5 (ST) with change notice CN14 that also serves as the Parallel Master Port read strobe PMRD."+ },+ {+ "number": "83",+ "name": "ETXEN/PMD14/CN15/RD6",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD6 (ST) with change notice CN15 that also serves as PMP data bit PMD14 and Ethernet transmit enable ETXEN."+ },+ {+ "number": "84",+ "name": "ETXCLK/PMD15/CN16/RD7",+ "type": "bidirectional",+ "description": "PORTD I/O pin RD7 (ST) with change notice CN16 that also serves as PMP data bit PMD15 and Ethernet transmit clock ETXCLK (ST)."+ },+ {+ "number": "85",+ "name": "VCAP/VDDCORE",+ "type": "power_in",+ "description": "Capacitor for the internal voltage regulator; VCAP must not be connected to VDD and requires a low-ESR (about 1 ohm) capacitor rated at least 6V connected to ground."+ },+ {+ "number": "86",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral logic and I/O pins, specified for 2.3V to 3.6V operation."+ },+ {+ "number": "87",+ "name": "C1RX/ETXD1/PMD11/RF0",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF0 (ST) that also serves as CAN1 receive C1RX (ST), PMP data bit PMD11 and Ethernet transmit data ETXD1."+ },+ {+ "number": "88",+ "name": "C1TX/ETXD0/PMD10/RF1",+ "type": "bidirectional",+ "description": "PORTF I/O pin RF1 (ST) that also serves as CAN1 transmit C1TX, PMP data bit PMD10 and Ethernet transmit data ETXD0."+ },+ {+ "number": "89",+ "name": "C2TX/ETXERR/PMD9/RG1",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG1 (ST) that also serves as CAN2 transmit C2TX, PMP data bit PMD9 and Ethernet transmit error ETXERR."+ },+ {+ "number": "90",+ "name": "C2RX/PMD8/RG0",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG0 (ST) that also serves as CAN2 receive C2RX (ST) and PMP data bit PMD8."+ },+ {+ "number": "91",+ "name": "TRCLK/RA6",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA6 (ST) that also serves as the trace clock output TRCLK."+ },+ {+ "number": "92",+ "name": "TRD3/RA7",+ "type": "bidirectional",+ "description": "PORTA I/O pin RA7 (ST) that also serves as trace data bit 3 output TRD3."+ },+ {+ "number": "93",+ "name": "PMD0/RE0",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE0 (ST) that also carries Parallel Master Port data/address bit PMD0 (TTL/ST)."+ },+ {+ "number": "94",+ "name": "PMD1/RE1",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE1 (ST) that also carries Parallel Master Port data/address bit PMD1 (TTL/ST)."+ },+ {+ "number": "95",+ "name": "TRD2/RG14",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG14 (ST) that also serves as trace data bit 2 output TRD2."+ },+ {+ "number": "96",+ "name": "TRD1/RG12",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG12 (ST) that also serves as trace data bit 1 output TRD1."+ },+ {+ "number": "97",+ "name": "TRD0/RG13",+ "type": "bidirectional",+ "description": "PORTG I/O pin RG13 (ST) that also serves as trace data bit 0 output TRD0."+ },+ {+ "number": "98",+ "name": "PMD2/RE2",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE2 (ST) that also carries Parallel Master Port data/address bit PMD2 (TTL/ST)."+ },+ {+ "number": "99",+ "name": "PMD3/RE3",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE3 (ST) that also carries Parallel Master Port data/address bit PMD3 (TTL/ST)."+ },+ {+ "number": "100",+ "name": "PMD4/RE4",+ "type": "bidirectional",+ "description": "PORTE I/O pin RE4 (ST) that also carries Parallel Master Port data/address bit PMD4 (TTL/ST)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package selection: PIC32MX795F512L is listed in the 100-pin USB, Ethernet and CAN pin table (Table 9; Footnote markers were removed from pin names (e.g. AC2TX(1), AC2RX(1), C2TX(1), C2RX(1)). Footnote 1; Pin 85 is printed as VCAP/VDDCORE in Table 9. Table 1-1 (page 33) lists it as VCAP, and the revision"+ ],+ "pages_sent": 74,+ "cost_usd": 0.4373,+ "at": "2026-10-18T22:06:16"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588897949170470912",+ "pages": 446,+ "sha256": "7c0e89419ff7a456",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 100,+ "described": 100,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "pic32mx795f512l-80i.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14,+ 14,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "eec53eae666dfb8fe1a37fcc11f81298b0e0fa9cf31f3fa1ae15fa87f47baf70",+ "checked": "2026-10-18",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "pic32mx795f512l-80i-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14,+ 14,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dca3056738e9b0e30458fdf79518d422ae05519521fa053d6f0bc3564e30a11e",+ "checked": "2026-10-18",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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pic32mx795f512l-80i.glbadded⋯ 1 unchanged line ⋯
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length="middle" direction="io" rot="R180"/>+ <pin name="ETXD3/PMD13/CN19/RD13" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+ <pin name="ETXD2/IC5/PMD12/RD12" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+ <pin name="OC4/RD3" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="OC3/RD2" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="OC2/RD1" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+ <pin name="VSS@4" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="SOSCO/T1CK/CN0/RC14" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>+ <pin name="SOSCI/CN1/RC13" x="17.78" y="-7.62" length="middle" direction="io" rot="R180"/>+ <pin name="SDO1/OC1/INT0/RD0" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>+ <pin name="EMDC/AEMDC/IC4/PMCS1/PMA14/RD11" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>+ <pin name="SCK1/IC3/PMCS2/PMA15/RD10" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>+ <pin name="SS1/IC2/RD9" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>+ <pin name="RTCC/EMDIO/AEMDIO/IC1/RD8" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/>+ <pin name="AETXEN/SDA1/INT4/RA15" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/>+ <pin name="AETXCLK/SCL1/INT3/RA14" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>+ <pin name="VSS@5" x="17.78" y="-27.94" length="middle" direction="pwr" rot="R180"/>+ <pin name="OSC2/CLKO/RC15" x="17.78" y="-30.48" length="middle" direction="io" rot="R180"/>+ <pin name="OSC1/CLKI/RC12" x="17.78" y="-33.02" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@6" x="17.78" y="-35.56" length="middle" direction="pwr" rot="R180"/>+ <pin name="TDO/RA5" x="17.78" y="-38.1" length="middle" direction="io" rot="R180"/>+ <pin name="TDI/RA4" x="17.78" y="-40.64" length="middle" direction="io" rot="R180"/>+ <pin name="SDA2/RA3" x="17.78" y="-43.18" length="middle" direction="io" rot="R180"/>+ <pin name="SCL2/RA2" x="17.78" y="-45.72" length="middle" direction="io" rot="R180"/>+ <pin name="D+/RG2" x="17.78" y="-48.26" length="middle" direction="io" rot="R180"/>+ <pin name="D-/RG3" x="17.78" y="-50.8" length="middle" direction="io" rot="R180"/>+ <pin name="VUSB3V3" x="17.78" y="-53.34" length="middle" direction="pwr" rot="R180"/>+ <pin name="VBUS" x="17.78" y="-55.88" length="middle" direction="pwr" rot="R180"/>+ <pin name="SCL3/SDO3/U1TX/RF8" x="17.78" y="-58.42" length="middle" direction="io" rot="R180"/>+ <pin name="SDA3/SDI3/U1RX/RF2" x="17.78" y="-60.96" length="middle" direction="io" rot="R180"/>+ <pin name="USBID/RF3" x="17.78" y="-63.5" length="middle" direction="io" rot="R180"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="PIC32MX795F512L-80I" prefix="U">+ <description></description>+ <gates>+ <gate name="G$1" symbol="PIC32MX795F512L-80I" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="TQFP-100_12x12mm_P0.4mm">+ <connects>+ <connect gate="G$1" pin="AERXERR/RG15" pad="1"/>+ <connect gate="G$1" pin="VDD" pad="2"/>+ <connect gate="G$1" pin="PMD5/RE5" pad="3"/>+ <connect gate="G$1" pin="PMD6/RE6" pad="4"/>+ <connect gate="G$1" pin="PMD7/RE7" pad="5"/>+ <connect gate="G$1" pin="T2CK/RC1" pad="6"/>+ <connect gate="G$1" pin="T3CK/AC2TX/RC2" pad="7"/>+ <connect gate="G$1" pin="T4CK/AC2RX/RC3" pad="8"/>+ <connect gate="G$1" pin="T5CK/SDI1/RC4" pad="9"/>+ <connect gate="G$1" pin="ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6" pad="10"/>+ <connect gate="G$1" pin="ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7" pad="11"/>+ <connect gate="G$1" pin="ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8" pad="12"/>+ <connect gate="G$1" pin="MCLR" pad="13"/>+ <connect gate="G$1" pin="ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9" pad="14"/>+ <connect gate="G$1" pin="VSS" pad="15"/>+ <connect gate="G$1" pin="VDD@2" pad="16"/>+ <connect gate="G$1" pin="TMS/RA0" pad="17"/>+ <connect gate="G$1" pin="AERXD0/INT1/RE8" pad="18"/>+ <connect gate="G$1" pin="AERXD1/INT2/RE9" pad="19"/>+ <connect gate="G$1" pin="AN5/C1IN+/VBUSON/CN7/RB5" pad="20"/>+ <connect gate="G$1" pin="AN4/C1IN-/CN6/RB4" pad="21"/>+ <connect gate="G$1" pin="AN3/C2IN+/CN5/RB3" pad="22"/>+ <connect gate="G$1" pin="AN2/C2IN-/CN4/RB2" pad="23"/>+ <connect gate="G$1" pin="PGEC1/AN1/CN3/RB1" pad="24"/>+ <connect gate="G$1" pin="PGED1/AN0/CN2/RB0" pad="25"/>+ <connect gate="G$1" pin="PGEC2/AN6/OCFA/RB6" pad="26"/>+ <connect gate="G$1" pin="PGED2/AN7/RB7" pad="27"/>+ <connect gate="G$1" pin="VREF-/CVREF-/AERXD2/PMA7/RA9" pad="28"/>+ <connect gate="G$1" pin="VREF+/CVREF+/AERXD3/PMA6/RA10" pad="29"/>+ <connect gate="G$1" pin="AVDD" pad="30"/>+ <connect gate="G$1" pin="AVSS" pad="31"/>+ <connect gate="G$1" pin="AN8/C1OUT/RB8" pad="32"/>+ <connect gate="G$1" pin="AN9/C2OUT/RB9" pad="33"/>+ <connect gate="G$1" pin="AN10/CVREFOUT/PMA13/RB10" pad="34"/>+ <connect gate="G$1" pin="AN11/ERXERR/AETXERR/PMA12/RB11" pad="35"/>+ <connect gate="G$1" pin="VSS@2" pad="36"/>+ <connect gate="G$1" pin="VDD@3" pad="37"/>+ <connect gate="G$1" pin="TCK/RA1" pad="38"/>+ <connect gate="G$1" pin="SCK4/U5TX/U2RTS/RF13" pad="39"/>+ <connect gate="G$1" pin="SS4/U5RX/U2CTS/RF12" pad="40"/>+ <connect gate="G$1" pin="AN12/ERXD0/AECRS/PMA11/RB12" pad="41"/>+ <connect gate="G$1" pin="AN13/ERXD1/AECOL/PMA10/RB13" pad="42"/>+ <connect gate="G$1" pin="AN14/ERXD2/AETXD3/PMALH/PMA1/RB14" pad="43"/>+ <connect gate="G$1" pin="AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15" pad="44"/>+ <connect gate="G$1" pin="VSS@3" pad="45"/>+ <connect gate="G$1" pin="VDD@4" pad="46"/>+ <connect gate="G$1" pin="AETXD0/SS3/U4RX/U1CTS/CN20/RD14" pad="47"/>+ <connect gate="G$1" pin="AETXD1/SCK3/U4TX/U1RTS/CN21/RD15" pad="48"/>+ <connect gate="G$1" pin="SDA5/SDI4/U2RX/PMA9/CN17/RF4" pad="49"/>+ <connect gate="G$1" pin="SCL5/SDO4/U2TX/PMA8/CN18/RF5" pad="50"/>+ <connect gate="G$1" pin="PMD4/RE4" pad="100"/>+ <connect gate="G$1" pin="PMD3/RE3" pad="99"/>+ <connect gate="G$1" pin="PMD2/RE2" pad="98"/>+ <connect gate="G$1" pin="TRD0/RG13" pad="97"/>+ <connect gate="G$1" pin="TRD1/RG12" pad="96"/>+ <connect gate="G$1" pin="TRD2/RG14" pad="95"/>+ <connect gate="G$1" pin="PMD1/RE1" pad="94"/>+ <connect gate="G$1" pin="PMD0/RE0" pad="93"/>+ <connect gate="G$1" pin="TRD3/RA7" pad="92"/>+ <connect gate="G$1" pin="TRCLK/RA6" pad="91"/>+ <connect gate="G$1" pin="C2RX/PMD8/RG0" pad="90"/>+ <connect gate="G$1" pin="C2TX/ETXERR/PMD9/RG1" pad="89"/>+ <connect gate="G$1" pin="C1TX/ETXD0/PMD10/RF1" pad="88"/>+ <connect gate="G$1" pin="C1RX/ETXD1/PMD11/RF0" pad="87"/>+ <connect gate="G$1" pin="VDD@5" pad="86"/>+ <connect gate="G$1" pin="VCAP/VDDCORE" pad="85"/>+ <connect gate="G$1" pin="ETXCLK/PMD15/CN16/RD7" pad="84"/>+ <connect gate="G$1" pin="ETXEN/PMD14/CN15/RD6" pad="83"/>+ <connect gate="G$1" pin="PMRD/CN14/RD5" pad="82"/>+ <connect gate="G$1" pin="OC5/PMWR/CN13/RD4" pad="81"/>+ <connect gate="G$1" pin="ETXD3/PMD13/CN19/RD13" pad="80"/>+ <connect gate="G$1" pin="ETXD2/IC5/PMD12/RD12" pad="79"/>+ <connect gate="G$1" pin="OC4/RD3" pad="78"/>+ <connect gate="G$1" pin="OC3/RD2" pad="77"/>+ <connect gate="G$1" pin="OC2/RD1" pad="76"/>+ <connect gate="G$1" pin="VSS@4" pad="75"/>+ <connect gate="G$1" pin="SOSCO/T1CK/CN0/RC14" pad="74"/>+ <connect gate="G$1" pin="SOSCI/CN1/RC13" pad="73"/>+ <connect gate="G$1" pin="SDO1/OC1/INT0/RD0" pad="72"/>+ <connect gate="G$1" pin="EMDC/AEMDC/IC4/PMCS1/PMA14/RD11" pad="71"/>+ <connect gate="G$1" pin="SCK1/IC3/PMCS2/PMA15/RD10" pad="70"/>+ <connect gate="G$1" pin="SS1/IC2/RD9" pad="69"/>+ <connect gate="G$1" pin="RTCC/EMDIO/AEMDIO/IC1/RD8" pad="68"/>+ <connect gate="G$1" pin="AETXEN/SDA1/INT4/RA15" pad="67"/>+ <connect gate="G$1" pin="AETXCLK/SCL1/INT3/RA14" pad="66"/>+ <connect gate="G$1" pin="VSS@5" pad="65"/>+ <connect gate="G$1" pin="OSC2/CLKO/RC15" pad="64"/>+ <connect gate="G$1" pin="OSC1/CLKI/RC12" pad="63"/>+ <connect gate="G$1" pin="VDD@6" pad="62"/>+ <connect gate="G$1" pin="TDO/RA5" pad="61"/>+ <connect gate="G$1" pin="TDI/RA4" pad="60"/>+ <connect gate="G$1" pin="SDA2/RA3" pad="59"/>+ <connect gate="G$1" pin="SCL2/RA2" pad="58"/>+ <connect gate="G$1" pin="D+/RG2" pad="57"/>+ <connect gate="G$1" pin="D-/RG3" pad="56"/>+ <connect gate="G$1" pin="VUSB3V3" pad="55"/>+ <connect gate="G$1" pin="VBUS" pad="54"/>+ <connect gate="G$1" pin="SCL3/SDO3/U1TX/RF8" pad="53"/>+ <connect gate="G$1" pin="SDA3/SDI3/U1RX/RF2" pad="52"/>+ <connect gate="G$1" pin="USBID/RF3" pad="51"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
pic32mx795f512l-80i.stepadded+19646@@ -0,0 +1,30971 @@+ISO-10303-21;+HEADER;+/* TQFP-100_12x12mm_P0.4mm.step 3D STEP model for use in ECAD systems+ * Copyright (C) 2025, KiCAD+ *+ * This work is licensed under the+ * [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode),+ * with the following exception:+ *+ * To the extent that the creation of electronic designs that use 'Licensed Material' can be+ * considered to be 'Adapted Material', then the copyright holder waives article 3 of the license+ * with respect to these designs and any generated files which use data provided as part of the+ * 'Licensed Material'.+ *+ * You are free to use the library data in your own projects without the obligation to share your+ * project files under this or any other license agreement. However, if you wish to distribute+ * these libraries, or parts thereof (including in modified form) as a collection then the exception+ * above does not apply. Please refer to+ * https://gitlab.com/kicad/libraries/kicad-packages3D/-/blob/master/LICENSE.md for further clarification+ * of the exception.+ *+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * USE 3D CAD DATA AT YOUR OWN RISK+ * DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.+ */++FILE_DESCRIPTION(+/* description */ ('model of TQFP-100_12x12mm_P0.4mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'TQFP-100_12x12mm_P0.4mm.step',+/* time_stamp */ '1970-01-01T00:00:00',+/* author */ ('KiCAD','kicad'),+/* organization */ ('OCCT'),+/* preprocessor_version */ '',+/* originating_system */ 'KiCAD',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1=APPLICATION_PROTOCOL_DEFINITION('international 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BOUNDED_SURFACE() B_SPLINE_SURFACE(2,2,((#33,#34,#35,#36,#37),(#326,#327,#328,#329,#330),(#303,#304,#305,#306,#307)),.UNSPECIFIED.,.F.,.F.,.F.) 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B_SPLINE_SURFACE_WITH_KNOTS((3,3),(3,1,1,3),(0.,0.206784146731),(-0.254623960569,-3.99824328808E-02,0.166801713851,0.381443241539),.UNSPECIFIED.) GEOMETRIC_REPRESENTATION_ITEM() RATIONAL_B_SPLINE_SURFACE(((1.,1.,1.,1.,1.),(0.781002645201,0.781002645201,0.781002645201,0.781002645201,0.781002645201),(1.,1.,1.,1.,1.))) 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