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PIC32MX530F128H-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC32MX530F128H-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)

PIC32MX530F128H-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AN22/RPE5/PMD5/RE5 bidirectional Analog input AN22 and PORTE bit RE5 with ST input buffer, also remappable as RPE5 and PMP data bit PMD5.
2 AN23/PMD6/RE6 bidirectional Analog input AN23 and PORTE bit RE6 with ST input buffer, also PMP data bit PMD6.
3 AN27/PMD7/RE7 bidirectional Analog input AN27 and PORTE bit RE7 with ST input buffer, also PMP data bit PMD7.
4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 bidirectional Analog input AN16 and Comparator 1 input C1IND, also PORTG bit RG6 (ST buffer), remappable RPG6, SPI2 clock SCK2 and PMP address PMA5.
5 AN17/C1INC/RPG7/PMA4/RG7 bidirectional Analog input AN17 and Comparator 1 input C1INC, also PORTG bit RG7 (ST buffer), remappable RPG7 and PMP address PMA4.
6 AN18/C2IND/RPG8/PMA3/RG8 bidirectional Analog input AN18 and Comparator 2 input C2IND, also PORTG bit RG8 (ST buffer), remappable RPG8 and PMP address PMA3.
7 MCLR input Master Clear (Reset) input; an active-low Reset to the device, with ST buffer.
8 AN19/C2INC/RPG9/PMA2/RG9 bidirectional Analog input AN19 and Comparator 2 input C2INC, also PORTG bit RG9 (ST buffer), remappable RPG9 and PMP address PMA2.
9 VSS power_in Ground reference for logic and I/O pins.
10 VDD power_in Positive supply for peripheral logic and I/O pins.
11 AN5/C1INA/RPB5/VBUSON/RB5 bidirectional Analog input AN5 and Comparator 1 input C1INA, also PORTB bit RB5 (ST buffer) and USB host/OTG bus power control output VBUSON; VBUSON is not available when remapped to RPB5.
12 AN4/C1INB/RB4 bidirectional Analog input AN4 and Comparator 1 input C1INB, also PORTB bit RB4 with ST input buffer.
13 PGED3/AN3/C2INA/RPB3/RB3 bidirectional ICSP/debug data I/O for channel 3, analog input AN3, Comparator 2 input C2INA, and PORTB bit RB3 (ST buffer).
14 PGEC3/AN2/CTCMP/C2INB/RPB2/CTED13/RB2 bidirectional ICSP/debug clock input for channel 3 (ST buffer), analog input AN2, Comparator 2 input C2INB, CTMU external edge input CTED13, and PORTB bit RB2.
15 PGEC1/VREF-/AN1/RPB1/CTED12/RB1 bidirectional ICSP/debug clock input for channel 1 (ST buffer), analog reference VREF- input, analog input AN1, CTMU edge input CTED12, and PORTB bit RB1.
16 PGED1/VREF+/AN0/RPB0/PMA6/RB0 bidirectional ICSP/debug data I/O for channel 1, analog reference VREF+ input, analog input AN0, and PORTB bit RB0 (ST buffer).
17 PGEC2/AN6/RPB6/RB6 bidirectional ICSP/debug clock input for channel 2 (ST buffer), analog input AN6, and PORTB bit RB6.
18 PGED2/AN7/RPB7/CTED3/RB7 bidirectional ICSP/debug data I/O for channel 2, analog input AN7, CTMU edge input CTED3, and PORTB bit RB7 (ST buffer).
19 AVDD power_in Positive supply for analog modules; must be connected at all times.
20 AVSS power_in Ground reference for analog modules; must be connected even if the ADC is not used.
21 AN8/RPB8/CTED10/RB8 bidirectional Analog input AN8, CTMU edge input CTED10, and PORTB bit RB8 (ST buffer), remappable as RPB8.
22 AN9/RPB9/CTED4/PMA7/RB9 bidirectional Analog input AN9, CTMU edge input CTED4, and PORTB bit RB9 (ST buffer), remappable as RPB9, with PMP address PMA7.
23 TMS/CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10 bidirectional JTAG Test Mode Select input (ST buffer), comparator voltage reference output CVREFOUT, analog input AN10, and PORTB bit RB10.
24 TDO/AN11/PMA12/RB11 bidirectional JTAG Test Data Output, analog input AN11, PMP address PMA12, and PORTB bit RB11 (ST buffer).
25 VSS power_in Ground reference for logic and I/O pins.
26 VDD power_in Positive supply for peripheral logic and I/O pins.
27 TCK/AN12/PMA11/RB12 bidirectional JTAG Test Clock input (ST buffer), analog input AN12, PMP address PMA11, and PORTB bit RB12.
28 TDI/AN13/PMA10/RB13 bidirectional JTAG Test Data Input, analog input AN13, PMP address PMA10, and PORTB bit RB13.
29 AN14/RPB14/SCK3/CTED5/PMA1/RB14 bidirectional Analog input AN14, SPI3 clock SCK3, CTMU edge input CTED5, PMP address PMA1, and PORTB bit RB14 (ST buffer), remappable as RPB14.
30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 bidirectional Analog input AN15, Output Compare Fault B input OCFB, CTMU edge input CTED6, PMP address PMA0, and PORTB bit RB15 (ST buffer).
31 RPF4/SDA2/PMA9/RF4 bidirectional Remappable pin RPF4, I2C2 data SDA2 (open-drain by default), PMP address PMA9, and PORTF bit RF4 (ST buffer).
32 RPF5/SCL2/PMA8/RF5 bidirectional Remappable pin RPF5, I2C2 clock SCL2 (open-drain by default), PMP address PMA8, and PORTF bit RF5 (ST buffer).
33 USBID/RPF3/RF3 bidirectional USB OTG ID detect input (ST buffer), also remappable RPF3 and PORTF bit RF3; the RPF3 remap is not available when USBID is used.
34 VBUS power_in USB bus power monitor input (analog).
35 VUSB3V3 power_in USB internal transceiver supply; if the USB module is not used this pin must be connected to VDD.
36 D- bidirectional USB D- data line (analog I/O).
37 D+ bidirectional USB D+ data line (analog I/O).
38 VDD power_in Positive supply for peripheral logic and I/O pins.
39 OSC1/CLKI/RC12 bidirectional Primary oscillator crystal input and external clock input CLKI (ST buffer in RC mode, CMOS otherwise), also PORTC bit RC12.
40 OSC2/CLKO/RC15 bidirectional Primary oscillator crystal output, optionally CLKO in RC and EC modes, and PORTC bit RC15 (ST buffer).
41 VSS power_in Ground reference for logic and I/O pins.
42 RPD8/RTCC/RD8 bidirectional Remappable pin RPD8, RTCC alarm output, and PORTD bit RD8 (ST buffer).
43 RPD9/SDA1/RD9 bidirectional Remappable pin RPD9, I2C1 data SDA1 (open-drain by default), and PORTD bit RD9 (ST buffer).
44 RPD10/SCL1/PMA15/RD10 bidirectional Remappable pin RPD10, I2C1 clock SCL1 (open-drain by default), PMP address PMA15, and PORTD bit RD10 (ST buffer).
45 RPD11/PMA14/RD11 bidirectional Remappable pin RPD11, PMP address PMA14, and PORTD bit RD11 (ST buffer).
46 RPD0/INT0/RD0 bidirectional Remappable pin RPD0, external interrupt INT0 (ST buffer), and PORTD bit RD0.
47 SOSCI/RPC13/RC13 bidirectional 32.768 kHz secondary oscillator crystal input (ST/CMOS), remappable RPC13 and PORTC bit RC13.
48 SOSCO/RPC14/T1CK/RC14 bidirectional 32.768 kHz secondary oscillator crystal output, Timer1 external clock T1CK, remappable RPC14, and PORTC bit RC14 (ST buffer).
49 AN24/RPD1/RD1 bidirectional Analog input AN24, remappable pin RPD1, and PORTD bit RD1 (ST buffer).
50 AN25/RPD2/SCK1/RD2 bidirectional Analog input AN25, remappable pin RPD2, SPI1 clock SCK1, and PORTD bit RD2 (ST buffer).
51 AN26/C3IND/RPD3/RD3 bidirectional Analog input AN26, Comparator 3 input C3IND, remappable pin RPD3, and PORTD bit RD3 (ST buffer).
52 RPD4/PMWR/RD4 bidirectional Remappable pin RPD4, PMP write strobe PMWR, and PORTD bit RD4 (ST buffer).
53 RPD5/PMRD/RD5 bidirectional Remappable pin RPD5, PMP read strobe PMRD, and PORTD bit RD5 (ST buffer).
54 C3INC/RD6 bidirectional Comparator 3 input C3INC (analog) and PORTD bit RD6 (ST buffer).
55 C3INB/RD7 bidirectional Comparator 3 input C3INB (analog) and PORTD bit RD7 (ST buffer).
56 VCAP power_in Capacitor connection for the internal voltage regulator; must not be connected to VDD and requires a low-ESR (3 ohm) capacitor to ground, with at least a 6V rating.
57 VDD power_in Positive supply for peripheral logic and I/O pins.
58 C3INA/RPF0/RF0 bidirectional Comparator 3 input C3INA (analog), remappable pin RPF0, and PORTF bit RF0 (ST buffer).
59 RPF1/RF1 bidirectional Remappable pin RPF1 and PORTF bit RF1 (ST buffer).
60 PMD0/RE0 bidirectional PMP data bit PMD0 (TTL/ST) and PORTE bit RE0 (ST buffer).
61 PMD1/RE1 bidirectional PMP data bit PMD1 (TTL/ST) and PORTE bit RE1 (ST buffer).
62 AN20/PMD2/RE2 bidirectional Analog input AN20, PMP data bit PMD2, and PORTE bit RE2 (ST buffer).
63 RPE3/CTPLS/PMD3/RE3 bidirectional Remappable pin RPE3, CTMU pulse output CTPLS, PMP data bit PMD3, and PORTE bit RE3 (ST buffer).
64 AN21/PMD4/RE4 bidirectional Analog input AN21, PMP data bit PMD4, and PORTE bit RE4 (ST buffer).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (Standard Operating Conditions) VDD 2.3 3.6 V Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) 328
Maximum operating frequency 50 MHz -40°C to +85°C (industrial), DC to 50 MHz 1
Operating Ambient Temperature Range (Industrial) TA -40 85 °C Industrial Temperature Devices 314
Operating Junction Temperature Range (Industrial) TJ -40 125 °C Industrial Temperature Devices 314
INTx Pin High or Low Time DI35 TINP 10 ns 328
CNx High or Low Time (input) DI40 TRBP 2 TSYSCLK 328
Port Output Rise Time DO31 TIOR 5 15 ns VDD < 2.5V 328
Port Output Rise Time DO31 TIOR 5 10 ns VDD > 2.5V 328
Port Output Fall Time DO32 TIOF 5 15 ns VDD < 2.5V 328
Port Output Fall Time DO32 TIOF 5 10 ns VDD > 2.5V 328
Package Thermal Resistance, 64-pin TQFP 10 mm x 10 mm (junction to ambient) JA 55 °C/W Note 1: Junction-to-ambient, achieved by package simulations 314

CAD (KiCad official)

  • Symbol: PIC32MX530F128H-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: pic32mx530f128h-i-etched.step / pic32mx530f128h-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic32mx530f128h-i.step / pic32mx530f128h-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (390 pp, sha256 56ad63db79d818a4, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF