PIC32MM0256GPM064T-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)

PIC32MM0256GPM064T-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RP21/SDI3/RA7	bidirectional	PORTA digital I/O RA7 with remappable pin RP21 and SPI3 data input SDI3.
2	CVREF/AN9/C3INB/RP16/VBUSON/RB14	bidirectional	PORTB I/O RB14 with comparator voltage reference output CVREF, ADC input AN9, Comparator 3 input B, RP16 and USB VBUSON power-control output.
3	AN10/C3INA/REFCLKO/RP17/RB15	bidirectional	High drive strength PORTB I/O RB15 with ADC input AN10, Comparator 3 input A, reference clock output REFCLKO and RP17.
4	AVSS	power_in	Analog modules ground; must be connected even if the ADC is not used.
5	AVDD	power_in	Analog modules power supply; must be connected even if the ADC is not used.
6	AN16/U1CTS/RA13	bidirectional	PORTA I/O RA13 with ADC input AN16 and UART1 Clear-to-Send input.
7	AN17/OCM1A/RA12	bidirectional	PORTA I/O RA12 with ADC input AN17 and MCCP1 output A.
8	AN18/RA11	bidirectional	PORTA I/O RA11 with ADC input AN18.
9	MCLR	input	Master Clear (device Reset) Schmitt Trigger input, active low; also used for device programming and debugging.
10	AN19/U1RX/RA6	bidirectional	PORTA I/O RA6 with ADC input AN19 and UART1 receive data input.
11	PGEC2/VREF+/CVREF+/AN0/RP1/RA0	bidirectional	PORTA I/O RA0 with ICSP port 2 clock input, ADC positive reference VREF+, CVREF+ input, AN0 and RP1.
12	PGED2/VREF-/AN1/RP2/OCM1F/RA1	bidirectional	PORTA I/O RA1 with ICSP port 2 data, ADC negative reference VREF-, AN1, RP2 and MCCP1 output F.
13	PGED1/AN2/C1IND/C2INB/C3INC/RP6/OCM2C/RB0	bidirectional	PORTB I/O RB0 with ICSP port 1 data, AN2, comparator inputs C1IND/C2INB/C3INC, RP6 and MCCP2 output C.
14	PGEC1/AN3/C1INC/C2INA/RP7/OCM2D/RB1	bidirectional	PORTB I/O RB1 with ICSP port 1 clock input, AN3, comparator inputs C1INC/C2INA, RP7 and MCCP2 output D.
15	AN4/C1INB/RP8/SDA2/OCM2E/RB2	bidirectional	PORTB I/O RB2 with AN4, Comparator 1 input B, RP8, I2C2 data and MCCP2 output E.
16	TDI/AN11/C1INA/RP9/SCL2/OCM2F/RB3	bidirectional	PORTB I/O RB3 with JTAG data input TDI, AN11, Comparator 1 input A, RP9, I2C2 clock and MCCP2 output F.
17	VDD	power_in	Digital modules power supply, 2.0V to 3.6V operating range.
18	VSS	power_in	Digital modules ground.
19	AN12/C2IND/T2CK/T2G/RC0	bidirectional	PORTC I/O RC0 with AN12, Comparator 2 input D, Timer2 external clock input and Timer2 gate input.
20	AN13/T3CK/T3G/RC1	bidirectional	PORTC I/O RC1 with AN13, Timer3 external clock input and Timer3 gate input.
21	RP19/OCM2A/RC2	bidirectional	PORTC I/O RC2 with remappable pin RP19 and MCCP2 output A.
22	SS3/FSYNC3/RC11	bidirectional	PORTC I/O RC11 with SPI3 slave select input and SPI3 frame signal.
23	VDD	power_in	Digital modules power supply, 2.0V to 3.6V operating range.
24	VSS	power_in	Digital modules ground.
25	OSC1/CLKI/AN5/RP3/OCM1C/RA2	bidirectional	PORTA I/O RA2 with primary oscillator crystal pin OSC1, external clock input CLKI, AN5, RP3 and MCCP1 output C.
26	OSC2/CLKO/AN6/C3IND/RP4/RA3	bidirectional	High drive strength PORTA I/O RA3 with primary oscillator crystal pin OSC2, clock output CLKO, AN6, Comparator 3 input D and RP4.
27	SDO3/RA8	bidirectional	High drive strength PORTA I/O RA8 with SPI3 data output.
28	SOSCI/AN7/RP10/RB4	bidirectional	PORTB I/O RB4 with secondary oscillator crystal pin SOSCI, AN7 and RP10.
29	SOSCO/SCLKI/RP5/PWRLCLK/RA4	bidirectional	PORTA I/O RA4 with secondary oscillator pin SOSCO, digital clock input SCLKI, RP5 and RTCC 50/60 Hz clock input.
30	RP24/RA9	bidirectional	PORTA I/O RA9 with remappable pin RP24.
31	SDI1/INT1/RD4	bidirectional	PORTD I/O RD4 with SPI1 data input and external interrupt 1.
32	SS1/FSYNC1/INT0/RD2	bidirectional	PORTD I/O RD2 with SPI1 slave select input, SPI1 frame signal and external interrupt 0.
33	OCM3B/RD3	bidirectional	PORTD I/O RD3 with MCCP3 output B.
34	REFCLKI/T1CK/T1G/U1RTS/U1BCLK/SDO1/RD0	bidirectional	High drive strength PORTD I/O RD0 with reference clock input, Timer1 clock/gate inputs, UART1 RTS and IrDA baud clock outputs, and SPI1 data output.
35	OCM2B/RC3	bidirectional	PORTC I/O RC3 with MCCP2 output B.
36	OCM1E/INT3/RC4	bidirectional	PORTC I/O RC4 with MCCP1 output E and external interrupt 3.
37	AN15/OCM1D/RC5	bidirectional	PORTC I/O RC5 with AN15 and MCCP1 output D.
38	VSS	power_in	Digital modules ground.
39	VDD	power_in	Digital modules power supply, 2.0V to 3.6V operating range.
40	U1TX/RC12	bidirectional	PORTC I/O RC12 with UART1 transmit data output.
41	OCM3D/RC14	bidirectional	PORTC I/O RC14 with MCCP3 output D.
42	OCM3E/RC15	bidirectional	PORTC I/O RC15 with MCCP3 output E.
43	RB5	bidirectional	PORTB I/O RB5 with ICSP port 3 data, RP11, alternate I2C1 data and USB OTG ID input.
44	VBUS/RB6	power_in	PORTB I/O RB6 sharing the USB VBUS connection (5V nominal).
45	OCM3F/RC10	bidirectional	PORTC I/O RC10 with MCCP3 output F.
46	RP12/SDA3/RB7	bidirectional	PORTB I/O RB7 with remappable pin RP12 and I2C3 data.
47	SCK1/RC13	bidirectional	High drive strength PORTC I/O RC13 with SPI1 clock.
48	TCK/RP13/SCL1/RB8	bidirectional	High drive strength PORTB I/O RB8 with JTAG clock input TCK, RP13 and I2C1 clock.
49	TMS/RP14/SDA1/INT2/RB9	bidirectional	High drive strength PORTB I/O RB9 with JTAG mode select TMS, RP14, I2C1 data and external interrupt 2; may toggle during ICSP programming.
50	RP23/RC6	bidirectional	PORTC I/O RC6 with remappable pin RP23.
51	RP20/RC7	bidirectional	PORTC I/O RC7 with remappable pin RP20.
52	AN14/LVDIN/C2INC/RC8	bidirectional	PORTC I/O RC8 with AN14, High/Low-Voltage Detect input and Comparator 2 input C.
53	OCM1B/RD1	bidirectional	PORTD I/O RD1 with MCCP1 output B.
54	OCM3A/RA5	bidirectional	PORTA I/O RA5 with MCCP3 output A.
55	RC9	bidirectional	High drive strength PORTC I/O RC9 with ICSP port 3 clock, JTAG data output TDO, RP18, alternate I2C1 clock and USB output enable.
56	VCAP	passive	Core voltage regulator filter capacitor connection; requires a 10 µF low-ESR (<5 Ω) capacitor to ground and must not be connected to VDD.
57	VDD	power_in	Digital modules power supply, 2.0V to 3.6V operating range.
58	RTCC/RA15	bidirectional	PORTA I/O RA15 with Real-Time Clock/Calendar alarm/seconds output.
59	OCM3C/RA14	bidirectional	PORTA I/O RA14 with MCCP3 output C.
60	D-/RB10	bidirectional	USB transceiver differential minus line, shared with PORTB I/O RB10.
61	D+/RB11	bidirectional	USB transceiver differential plus line, shared with PORTB I/O RB11.
62	VUSB3V3	power_in	USB transceiver power input, 3.3V nominal (3.0V to 3.6V required for USB operation); must be powered for USB.
63	AN8/RP15/SCL3/RB13	bidirectional	High drive strength PORTB I/O RB13 with AN8, RP15 and I2C3 clock.
64	RP22/SCK3/RA10	bidirectional	High drive strength PORTA I/O RA10 with RP22 and SPI3 clock.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	TQFP-64(10x10)
Category	Single Chip Microcomputer/Microcontroller
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage	VDD	2		3.6	V		285
Operating Ambient Temperature Range	TA	-40		125	°C		284
Operating Junction Temperature Range	TJ	-40		125	°C		284
Ambient temperature under bias		-40		125	°C		283
Storage temperature		-65		150	°C		283
Voltage on VDD with respect to VSS	VDD	-0.3		4	V		283
Voltage on 5.5V tolerant pin with respect to VSS		-0.3		4	V	When VDD = 0V	283
Voltage on 5.5V tolerant pin with respect to VSS		-0.3		6	V	When VDD ≥ 2.0V	283
Voltage on AVSS with respect to VSS		-0.3		0.3	V		283
Maximum output current sunk by I/O pin				11	mA		283
Maximum output current sourced by I/O pin with increased drive strength				24	mA	RA3, RA8, RA10, RB8, RB9, RB13, RB15, RC9, RC13 and RD0	283
Package thermal resistance junction to ambient, 64-Pin TQFP	θJA		44.5		°C/W	64-Pin TQFP	284
Supply Voltage	VDD	2		3.6	V	DC10	285
VDD Start Voltage to Ensure Internal Power-on Reset Signal	VPOR			100	mV	DC16 (min VSS)	285
Recommended VDD Rise Rate to Ensure Internal Power-on Reset Signal	SVDD	0.05			V/ms	0-3.3V in 66 ms, 0-2.0V in 40 ms	285
Brown-out Reset Voltage on VDD Transition, High-to-Low	VBOR	2		2.083	V		285
Operating current	IDD		0.72	0.96	mA	FSYS = 1 MHz, -40°C to +85°C, 2.0V	285
Operating current	IDD			1.4	mA	FSYS = 1 MHz, -40°C to +125°C, 3.3V	285
Operating current	IDD		2.5	3.7	mA	FSYS = 8 MHz, -40°C to +85°C, 3.3V	285
Operating current	IDD		7.9	10.2	mA	FSYS = 25 MHz, -40°C to +85°C, 3.3V	285
Operating current	IDD		7.9	12.5	mA	FSYS = 25 MHz, -40°C to +125°C, 3.3V	285
Operating current	IDD		0.4	1	mA	LPRC, FSYS = 32 kHz, -40°C to +125°C, 3.3V	285
Idle current	IIDLE		0.98	2.3	mA	FSYS = 8 MHz, -40°C to +125°C, 3.3V	286
Idle current	IIDLE		2.9	4.5	mA	FSYS = 25 MHz, -40°C to +125°C, 3.3V	286
Power-down current, Sleep with active main Voltage Regulator	IPD		200	400	µA	+125°C, 3.3V, VREGS = 1, RETEN = 0	287
Power-down current, Sleep with main Voltage Regulator in Standby mode	IPD		55	110	µA	+125°C, 3.3V, VREGS = 0, RETEN = 0	287
Input Low Voltage, I/O Pins with ST Buffer	VIL			0.2	VDD	DI10, min VSS	289
Input Low Voltage, MCLR	VIL			0.2	VDD	DI15, min VSS	289
Input High Voltage, I/O Pins with ST Buffer without 5V Tolerance	VIH	0.8			VDD	DI20, max VDD	289
Input High Voltage, I/O Pins with ST Buffer with 5V Tolerance	VIH			5.5	V	DI20, min 0.8 VDD	289
Input High Voltage, MCLR	VIH	0.8			VDD	DI25, max VDD	289
CNPUx Pull-up Current	ICNPU	150	350	450	µA	VDD = 3.3V, VPIN = VSS	289
CNPDx Pull-Down Current	ICNPD	230	300	500	µA	VDD = 3.3V, VPIN = VDD	289
Input Leakage Current, I/O Pins 5V Tolerant	IIL			1	µA	VSS ≤ VPIN ≤ VDD, pin at high-impedance	289
Input Leakage Current, I/O Pins Not 5V Tolerant	IIL			1	µA	VSS ≤ VPIN ≤ VDD, pin at high-impedance	289
Input Leakage Current, MCLR	IIL			1	µA	VSS ≤ VPIN ≤ VDD	289
Input Low Injection Current	IICL			-5	mA	applies to all pins (min 0)	290
Input High Injection Current	IICH	0		5	mA	all pins except 5V tolerant pins and SOSCI	290
Total Input Injection Current	IICT	-20		20	mA	Absolute instantaneous sum of all ± input injection currents	290
Output Low Voltage, I/O Ports	VOL			0.4	V	IOL = 6.6 mA, VDD = 3.6V	291
Output Low Voltage, I/O Ports	VOL			0.21	V	IOL = 5.0 mA, VDD = 2V	291
Output Low Voltage, OSC2/CLKO	VOL			0.16	V	IOL = 6.6 mA, VDD = 3.6V	291
Output High Voltage, I/O Ports	VOH	3.25			V	IOH = -6.0 mA, VDD = 3.6V	291
Output High Voltage, I/O Ports	VOH	1.4			V	IOH = -3.0 mA, VDD = 2V	291
Output High Voltage, OSC2/CLKO	VOH	3.3			V	IOH = -6.0 mA, VDD = 3.6V	291
Flash Cell Endurance	EP	10000	20000		E/W		291
Flash Characteristic Retention	TRETD	20			Year	If no other specifications are violated	291
Self-Timed Page Erase Time	TIE	4.18	4.26	4.33	ms	2048 bytes	291
Self-Timed Chip Erase Time	TCE	16.6	16.9	17.3	ms		291
External Filter Capacitor Value	CEFC	4.7	10		µF	Series Resistance < 3 recommended; < 5 required	292
Low-Voltage Regulator Output Voltage	VLVR	0.9		1.2	V	RETEN = 1, RETVR (FPOR[2]) = 0	292
Comparator Input Offset Voltage	VIOFF	-20		20	mV		293
Voltage Reference Absolute Accuracy	VRAA	-1		1	LSb		293
Voltage Reference Settling Time	TSET			10	µs		293

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	ppa		01110 = Time base is synchronized to SCCP8 01101 = Time base is synchronized to the INT4 Pin (Remappable)	150

CAD (KiCad official)

Symbol: PIC32MM0256GPM064T-I
Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: pic32mm0256gpm064t-i-etched.step / pic32mm0256gpm064t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic32mm0256gpm064t-i.step / pic32mm0256gpm064t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (356 pp, sha256 e0e3b208b87a54d9, retrieved 2026-10-26, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# PIC32MM0256GPM064T-I

**Microchip Tech** · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)

PIC32MM0256GPM064T-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RP21/SDI3/RA7 | bidirectional | PORTA digital I/O RA7 with remappable pin RP21 and SPI3 data input SDI3. |
| 2 | CVREF/AN9/C3INB/RP16/VBUSON/RB14 | bidirectional | PORTB I/O RB14 with comparator voltage reference output CVREF, ADC input AN9, Comparator 3 input B, RP16 and USB VBUSON power-control output. |
| 3 | AN10/C3INA/REFCLKO/RP17/RB15 | bidirectional | High drive strength PORTB I/O RB15 with ADC input AN10, Comparator 3 input A, reference clock output REFCLKO and RP17. |
| 4 | AVSS | power_in | Analog modules ground; must be connected even if the ADC is not used. |
| 5 | AVDD | power_in | Analog modules power supply; must be connected even if the ADC is not used. |
| 6 | AN16/U1CTS/RA13 | bidirectional | PORTA I/O RA13 with ADC input AN16 and UART1 Clear-to-Send input. |
| 7 | AN17/OCM1A/RA12 | bidirectional | PORTA I/O RA12 with ADC input AN17 and MCCP1 output A. |
| 8 | AN18/RA11 | bidirectional | PORTA I/O RA11 with ADC input AN18. |
| 9 | MCLR | input | Master Clear (device Reset) Schmitt Trigger input, active low; also used for device programming and debugging. |
| 10 | AN19/U1RX/RA6 | bidirectional | PORTA I/O RA6 with ADC input AN19 and UART1 receive data input. |
| 11 | PGEC2/VREF+/CVREF+/AN0/RP1/RA0 | bidirectional | PORTA I/O RA0 with ICSP port 2 clock input, ADC positive reference VREF+, CVREF+ input, AN0 and RP1. |
| 12 | PGED2/VREF-/AN1/RP2/OCM1F/RA1 | bidirectional | PORTA I/O RA1 with ICSP port 2 data, ADC negative reference VREF-, AN1, RP2 and MCCP1 output F. |
| 13 | PGED1/AN2/C1IND/C2INB/C3INC/RP6/OCM2C/RB0 | bidirectional | PORTB I/O RB0 with ICSP port 1 data, AN2, comparator inputs C1IND/C2INB/C3INC, RP6 and MCCP2 output C. |
| 14 | PGEC1/AN3/C1INC/C2INA/RP7/OCM2D/RB1 | bidirectional | PORTB I/O RB1 with ICSP port 1 clock input, AN3, comparator inputs C1INC/C2INA, RP7 and MCCP2 output D. |
| 15 | AN4/C1INB/RP8/SDA2/OCM2E/RB2 | bidirectional | PORTB I/O RB2 with AN4, Comparator 1 input B, RP8, I2C2 data and MCCP2 output E. |
| 16 | TDI/AN11/C1INA/RP9/SCL2/OCM2F/RB3 | bidirectional | PORTB I/O RB3 with JTAG data input TDI, AN11, Comparator 1 input A, RP9, I2C2 clock and MCCP2 output F. |
| 17 | VDD | power_in | Digital modules power supply, 2.0V to 3.6V operating range. |
| 18 | VSS | power_in | Digital modules ground. |
| 19 | AN12/C2IND/T2CK/T2G/RC0 | bidirectional | PORTC I/O RC0 with AN12, Comparator 2 input D, Timer2 external clock input and Timer2 gate input. |
| 20 | AN13/T3CK/T3G/RC1 | bidirectional | PORTC I/O RC1 with AN13, Timer3 external clock input and Timer3 gate input. |
| 21 | RP19/OCM2A/RC2 | bidirectional | PORTC I/O RC2 with remappable pin RP19 and MCCP2 output A. |
| 22 | SS3/FSYNC3/RC11 | bidirectional | PORTC I/O RC11 with SPI3 slave select input and SPI3 frame signal. |
| 23 | VDD | power_in | Digital modules power supply, 2.0V to 3.6V operating range. |
| 24 | VSS | power_in | Digital modules ground. |
| 25 | OSC1/CLKI/AN5/RP3/OCM1C/RA2 | bidirectional | PORTA I/O RA2 with primary oscillator crystal pin OSC1, external clock input CLKI, AN5, RP3 and MCCP1 output C. |
| 26 | OSC2/CLKO/AN6/C3IND/RP4/RA3 | bidirectional | High drive strength PORTA I/O RA3 with primary oscillator crystal pin OSC2, clock output CLKO, AN6, Comparator 3 input D and RP4. |
| 27 | SDO3/RA8 | bidirectional | High drive strength PORTA I/O RA8 with SPI3 data output. |
| 28 | SOSCI/AN7/RP10/RB4 | bidirectional | PORTB I/O RB4 with secondary oscillator crystal pin SOSCI, AN7 and RP10. |
| 29 | SOSCO/SCLKI/RP5/PWRLCLK/RA4 | bidirectional | PORTA I/O RA4 with secondary oscillator pin SOSCO, digital clock input SCLKI, RP5 and RTCC 50/60 Hz clock input. |
| 30 | RP24/RA9 | bidirectional | PORTA I/O RA9 with remappable pin RP24. |
| 31 | SDI1/INT1/RD4 | bidirectional | PORTD I/O RD4 with SPI1 data input and external interrupt 1. |
| 32 | SS1/FSYNC1/INT0/RD2 | bidirectional | PORTD I/O RD2 with SPI1 slave select input, SPI1 frame signal and external interrupt 0. |
| 33 | OCM3B/RD3 | bidirectional | PORTD I/O RD3 with MCCP3 output B. |
| 34 | REFCLKI/T1CK/T1G/U1RTS/U1BCLK/SDO1/RD0 | bidirectional | High drive strength PORTD I/O RD0 with reference clock input, Timer1 clock/gate inputs, UART1 RTS and IrDA baud clock outputs, and SPI1 data output. |
| 35 | OCM2B/RC3 | bidirectional | PORTC I/O RC3 with MCCP2 output B. |
| 36 | OCM1E/INT3/RC4 | bidirectional | PORTC I/O RC4 with MCCP1 output E and external interrupt 3. |
| 37 | AN15/OCM1D/RC5 | bidirectional | PORTC I/O RC5 with AN15 and MCCP1 output D. |
| 38 | VSS | power_in | Digital modules ground. |
| 39 | VDD | power_in | Digital modules power supply, 2.0V to 3.6V operating range. |
| 40 | U1TX/RC12 | bidirectional | PORTC I/O RC12 with UART1 transmit data output. |
| 41 | OCM3D/RC14 | bidirectional | PORTC I/O RC14 with MCCP3 output D. |
| 42 | OCM3E/RC15 | bidirectional | PORTC I/O RC15 with MCCP3 output E. |
| 43 | RB5 | bidirectional | PORTB I/O RB5 with ICSP port 3 data, RP11, alternate I2C1 data and USB OTG ID input. |
| 44 | VBUS/RB6 | power_in | PORTB I/O RB6 sharing the USB VBUS connection (5V nominal). |
| 45 | OCM3F/RC10 | bidirectional | PORTC I/O RC10 with MCCP3 output F. |
| 46 | RP12/SDA3/RB7 | bidirectional | PORTB I/O RB7 with remappable pin RP12 and I2C3 data. |
| 47 | SCK1/RC13 | bidirectional | High drive strength PORTC I/O RC13 with SPI1 clock. |
| 48 | TCK/RP13/SCL1/RB8 | bidirectional | High drive strength PORTB I/O RB8 with JTAG clock input TCK, RP13 and I2C1 clock. |
| 49 | TMS/RP14/SDA1/INT2/RB9 | bidirectional | High drive strength PORTB I/O RB9 with JTAG mode select TMS, RP14, I2C1 data and external interrupt 2; may toggle during ICSP programming. |
| 50 | RP23/RC6 | bidirectional | PORTC I/O RC6 with remappable pin RP23. |
| 51 | RP20/RC7 | bidirectional | PORTC I/O RC7 with remappable pin RP20. |
| 52 | AN14/LVDIN/C2INC/RC8 | bidirectional | PORTC I/O RC8 with AN14, High/Low-Voltage Detect input and Comparator 2 input C. |
| 53 | OCM1B/RD1 | bidirectional | PORTD I/O RD1 with MCCP1 output B. |
| 54 | OCM3A/RA5 | bidirectional | PORTA I/O RA5 with MCCP3 output A. |
| 55 | RC9 | bidirectional | High drive strength PORTC I/O RC9 with ICSP port 3 clock, JTAG data output TDO, RP18, alternate I2C1 clock and USB output enable. |
| 56 | VCAP | passive | Core voltage regulator filter capacitor connection; requires a 10 µF low-ESR (<5 Ω) capacitor to ground and must not be connected to VDD. |
| 57 | VDD | power_in | Digital modules power supply, 2.0V to 3.6V operating range. |
| 58 | RTCC/RA15 | bidirectional | PORTA I/O RA15 with Real-Time Clock/Calendar alarm/seconds output. |
| 59 | OCM3C/RA14 | bidirectional | PORTA I/O RA14 with MCCP3 output C. |
| 60 | D-/RB10 | bidirectional | USB transceiver differential minus line, shared with PORTB I/O RB10. |
| 61 | D+/RB11 | bidirectional | USB transceiver differential plus line, shared with PORTB I/O RB11. |
| 62 | VUSB3V3 | power_in | USB transceiver power input, 3.3V nominal (3.0V to 3.6V required for USB operation); must be powered for USB. |
| 63 | AN8/RP15/SCL3/RB13 | bidirectional | High drive strength PORTB I/O RB13 with AN8, RP15 and I2C3 clock. |
| 64 | RP22/SCK3/RA10 | bidirectional | High drive strength PORTA I/O RA10 with RP22 and SPI3 clock. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2 |  | 3.6 | V |  | 285 |
| Operating Ambient Temperature Range | TA | -40 |  | 125 | °C |  | 284 |
| Operating Junction Temperature Range | TJ | -40 |  | 125 | °C |  | 284 |
| Ambient temperature under bias |  | -40 |  | 125 | °C |  | 283 |
| Storage temperature |  | -65 |  | 150 | °C |  | 283 |
| Voltage on VDD with respect to VSS | VDD | -0.3 |  | 4 | V |  | 283 |
| Voltage on 5.5V tolerant pin with respect to VSS |  | -0.3 |  | 4 | V | When VDD = 0V | 283 |
| Voltage on 5.5V tolerant pin with respect to VSS |  | -0.3 |  | 6 | V | When VDD ≥ 2.0V | 283 |
| Voltage on AVSS with respect to VSS |  | -0.3 |  | 0.3 | V |  | 283 |
| Maximum output current sunk by I/O pin |  |  |  | 11 | mA |  | 283 |
| Maximum output current sourced by I/O pin with increased drive strength |  |  |  | 24 | mA | RA3, RA8, RA10, RB8, RB9, RB13, RB15, RC9, RC13 and RD0 | 283 |
| Package thermal resistance junction to ambient, 64-Pin TQFP | θJA |  | 44.5 |  | °C/W | 64-Pin TQFP | 284 |
| Supply Voltage | VDD | 2 |  | 3.6 | V | DC10 | 285 |
| VDD Start Voltage to Ensure Internal Power-on Reset Signal | VPOR |  |  | 100 | mV | DC16 (min VSS) | 285 |
| Recommended VDD Rise Rate to Ensure Internal Power-on Reset Signal | SVDD | 0.05 |  |  | V/ms | 0-3.3V in 66 ms, 0-2.0V in 40 ms | 285 |
| Brown-out Reset Voltage on VDD Transition, High-to-Low | VBOR | 2 |  | 2.083 | V |  | 285 |
| Operating current | IDD |  | 0.72 | 0.96 | mA | FSYS = 1 MHz, -40°C to +85°C, 2.0V | 285 |
| Operating current | IDD |  |  | 1.4 | mA | FSYS = 1 MHz, -40°C to +125°C, 3.3V | 285 |
| Operating current | IDD |  | 2.5 | 3.7 | mA | FSYS = 8 MHz, -40°C to +85°C, 3.3V | 285 |
| Operating current | IDD |  | 7.9 | 10.2 | mA | FSYS = 25 MHz, -40°C to +85°C, 3.3V | 285 |
| Operating current | IDD |  | 7.9 | 12.5 | mA | FSYS = 25 MHz, -40°C to +125°C, 3.3V | 285 |
| Operating current | IDD |  | 0.4 | 1 | mA | LPRC, FSYS = 32 kHz, -40°C to +125°C, 3.3V | 285 |
| Idle current | IIDLE |  | 0.98 | 2.3 | mA | FSYS = 8 MHz, -40°C to +125°C, 3.3V | 286 |
| Idle current | IIDLE |  | 2.9 | 4.5 | mA | FSYS = 25 MHz, -40°C to +125°C, 3.3V | 286 |
| Power-down current, Sleep with active main Voltage Regulator | IPD |  | 200 | 400 | µA | +125°C, 3.3V, VREGS = 1, RETEN = 0 | 287 |
| Power-down current, Sleep with main Voltage Regulator in Standby mode | IPD |  | 55 | 110 | µA | +125°C, 3.3V, VREGS = 0, RETEN = 0 | 287 |
| Input Low Voltage, I/O Pins with ST Buffer | VIL |  |  | 0.2 | VDD | DI10, min VSS | 289 |
| Input Low Voltage, MCLR | VIL |  |  | 0.2 | VDD | DI15, min VSS | 289 |
| Input High Voltage, I/O Pins with ST Buffer without 5V Tolerance | VIH | 0.8 |  |  | VDD | DI20, max VDD | 289 |
| Input High Voltage, I/O Pins with ST Buffer with 5V Tolerance | VIH |  |  | 5.5 | V | DI20, min 0.8 VDD | 289 |
| Input High Voltage, MCLR | VIH | 0.8 |  |  | VDD | DI25, max VDD | 289 |
| CNPUx Pull-up Current | ICNPU | 150 | 350 | 450 | µA | VDD = 3.3V, VPIN = VSS | 289 |
| CNPDx Pull-Down Current | ICNPD | 230 | 300 | 500 | µA | VDD = 3.3V, VPIN = VDD | 289 |
| Input Leakage Current, I/O Pins 5V Tolerant | IIL |  |  | 1 | µA | VSS ≤ VPIN ≤ VDD, pin at high-impedance | 289 |
| Input Leakage Current, I/O Pins Not 5V Tolerant | IIL |  |  | 1 | µA | VSS ≤ VPIN ≤ VDD, pin at high-impedance | 289 |
| Input Leakage Current, MCLR | IIL |  |  | 1 | µA | VSS ≤ VPIN ≤ VDD | 289 |
| Input Low Injection Current | IICL |  |  | -5 | mA | applies to all pins (min 0) | 290 |
| Input High Injection Current | IICH | 0 |  | 5 | mA | all pins except 5V tolerant pins and SOSCI | 290 |
| Total Input Injection Current | IICT | -20 |  | 20 | mA | Absolute instantaneous sum of all ± input injection currents | 290 |
| Output Low Voltage, I/O Ports | VOL |  |  | 0.4 | V | IOL = 6.6 mA, VDD = 3.6V | 291 |
| Output Low Voltage, I/O Ports | VOL |  |  | 0.21 | V | IOL = 5.0 mA, VDD = 2V | 291 |
| Output Low Voltage, OSC2/CLKO | VOL |  |  | 0.16 | V | IOL = 6.6 mA, VDD = 3.6V | 291 |
| Output High Voltage, I/O Ports | VOH | 3.25 |  |  | V | IOH = -6.0 mA, VDD = 3.6V | 291 |
| Output High Voltage, I/O Ports | VOH | 1.4 |  |  | V | IOH = -3.0 mA, VDD = 2V | 291 |
| Output High Voltage, OSC2/CLKO | VOH | 3.3 |  |  | V | IOH = -6.0 mA, VDD = 3.6V | 291 |
| Flash Cell Endurance | EP | 10000 | 20000 |  | E/W |  | 291 |
| Flash Characteristic Retention | TRETD | 20 |  |  | Year | If no other specifications are violated | 291 |
| Self-Timed Page Erase Time | TIE | 4.18 | 4.26 | 4.33 | ms | 2048 bytes | 291 |
| Self-Timed Chip Erase Time | TCE | 16.6 | 16.9 | 17.3 | ms |  | 291 |
| External Filter Capacitor Value | CEFC | 4.7 | 10 |  | µF | Series Resistance < 3 recommended; < 5 required | 292 |
| Low-Voltage Regulator Output Voltage | VLVR | 0.9 |  | 1.2 | V | RETEN = 1, RETVR (FPOR[2]) = 0 | 292 |
| Comparator Input Offset Voltage | VIOFF | -20 |  | 20 | mV |  | 293 |
| Voltage Reference Absolute Accuracy | VRAA | -1 |  | 1 | LSb |  | 293 |
| Voltage Reference Settling Time | TSET |  |  | 10 | µs |  | 293 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | ppa |  | 01110 = Time base is synchronized to SCCP8 01101 = Time base is synchronized to the INT4 Pin (Remappable) | 150 |

## CAD (KiCad official)

- Symbol: `PIC32MM0256GPM064T-I`
- Footprint: `Package_QFP:TQFP-64_10x10mm_P0.5mm`
- 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `pic32mm0256gpm064t-i-etched.step` / `pic32mm0256gpm064t-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic32mm0256gpm064t-i.step` / `pic32mm0256gpm064t-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/pic32mm0256gpm064t-i-datasheet.pdf) (356 pp, sha256 `e0e3b208b87a54d9`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pic32mm0256gpm064t-i-datasheet.pdf)