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PIC32CM5164JH01100-I

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MICROCHIP TECHNOLOGY Global Sourcing Parts, TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC32CM5164JH01100-I

MICROCHIP TECHNOLOGY · Global Sourcing Parts · TQFP-100(14x14)

PIC32CM5164JH01100-I from MICROCHIP TECHNOLOGY, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA00, XIN32 passive PA00 I/O pin on AVDD, also the 32.768 kHz crystal input XIN32 and EXTINT[0], with SERCOM1 PAD[0], TCC2 WO[0], TC7 WO[0] and CMP[2] alternate functions; resets to I/O, HI-Z.
2 PA01, XOUT32 passive PA01 I/O pin on AVDD, also the 32.768 kHz crystal output XOUT32 and EXTINT[1], with SERCOM1 PAD[1], TCC2 WO[1], TC7 WO[1] and CMP[3] alternate functions; resets to I/O, HI-Z.
3 PC00 bidirectional PC00 general-purpose I/O on AVDD with EXTINT[8] external interrupt; resets to I/O, HI-Z.
4 PC01 bidirectional PC01 general-purpose I/O on AVDD with EXTINT[9] external interrupt; resets to I/O, HI-Z.
5 PC02 bidirectional PC02 general-purpose I/O on AVDD with EXTINT[10] external interrupt; resets to I/O, HI-Z.
6 PC03 bidirectional PC03 general-purpose I/O on AVDD with EXTINT[11] and TCC2 WO[0]; resets to I/O, HI-Z.
7 PA02 bidirectional PA02 I/O on AVDD with EXTINT[2], AIN[0], AIN[4], DAC output VOUT and PTC Y[0]/DS[0]; analog functions are selected through peripheral function B, which disables digital control of the pin; resets to I/O, HI-Z.
8 PA03 bidirectional PA03 I/O on AVDD with EXTINT[3], external ADC reference VREFA, AIN[1], AIN[5] and PTC Y[1]/DS[1]; analog functions are selected through peripheral function B; resets to I/O, HI-Z.
9 PB04 bidirectional PB04 I/O on AVDD with EXTINT[4], AIN[6] and PTC Y[10]/DS[10]; analog functions are selected through peripheral function B; resets to I/O, HI-Z.
10 PB05 bidirectional PB05 I/O on AVDD with EXTINT[5], AIN[7], AIN[6] and PTC Y[11]/DS[11]; analog functions are selected through peripheral function B; resets to I/O, HI-Z.
11 AVSS power_in Analog ground reference for the ADC, AC, DAC, PTC and oscillator blocks, per the power supply table.
12 AVDD power_in Analog supply pin; the same voltage must be applied to VDDIN and AVDD, referred to as VDD, and it powers the ADC, AC, DAC, PTC and oscillators.
13 PB06 bidirectional PB06 I/O on AVDD with EXTINT[6], AIN[8], AIN[7], IN[6] and PTC Y[12]/DS[12]; resets to I/O, HI-Z.
14 PB07 bidirectional PB07 I/O on AVDD with EXTINT[7], AIN[9], IN[7] and PTC Y[13]/DS[13]; resets to I/O, HI-Z.
15 PB08 bidirectional PB08 I/O on AVDD with EXTINT[8], AIN[2], AIN[4], SERCOM4 PAD[0], TC0 WO[0], IN[8] and PTC Y[14]/DS[14]; resets to I/O, HI-Z.
16 PB09 bidirectional PB09 I/O on AVDD with EXTINT[9], AIN[3], AIN[5], SERCOM4 PAD[1], TC0 WO[1], OUT[2] and PTC Y[15]/DS[15]; resets to I/O, HI-Z.
17 PA04 bidirectional PA04 I/O on AVDD with EXTINT[4], AIN[4], AIN[0], SERCOM0 PAD[0], TCC0 WO[0], TC5 WO[0], IN[0] and PTC Y[2]/DS[2]; resets to I/O, HI-Z.
18 PA05 bidirectional PA05 I/O on AVDD with EXTINT[5], AIN[5], AIN[1], SERCOM0 PAD[1], TCC0 WO[1], TC5 WO[1], IN[1] and PTC Y[3]/DS[3]; resets to I/O, HI-Z.
19 PA06 bidirectional PA06 I/O on AVDD with EXTINT[6], AIN[6], AIN[2], SERCOM0 PAD[2], TCC1 WO[0], TC6 WO[0], IN[2] and PTC Y[4]/DS[4]; resets to I/O, HI-Z.
20 PA07 bidirectional PA07 I/O on AVDD with EXTINT[7], AIN[7], AIN[3], SERCOM0 PAD[3], TCC1 WO[1], TC6 WO[1], OUT[0] and PTC Y[5]/DS[5]; resets to I/O, HI-Z.
21 PC05 bidirectional PC05 I/O on AVDD with EXTINT[13], SERCOM6 PAD[3] and TCC2 WO[1]; resets to I/O, HI-Z.
22 PC06 bidirectional PC06 I/O on AVDD with EXTINT[14] and SERCOM6 PAD[0]; resets to I/O, HI-Z.
23 PC07 bidirectional PC07 I/O on AVDD with EXTINT[15] and SERCOM6 PAD[1]; resets to I/O, HI-Z.
24 VDDIO power_in I/O supply pin that powers the I/O lines and XOSC; VDDIO must be less than or equal to VDDIN = AVDD = VDD.
25 GND power_in Ground reference for the digital I/O and core supplies.
26 PA08 bidirectional PA08 I/O on VDDIO with NMI non-maskable interrupt, AIN[8], AIN[10], SERCOM0 PAD[0], SERCOM2 PAD[0], TCC0 WO[0], TCC1 WO[2], IN[3], QDI[0] and PTC X[0]/Y[16]/DS[16]; high-sink not specified for this pin; resets to I/O, HI-Z.
27 PA09 bidirectional PA09 I/O on VDDIO with EXTINT[9], AIN[9], AIN[11], SERCOM0 PAD[1], SERCOM2 PAD[1], TCC0 WO[1], TCC1 WO[3], IN[4], QDI[1] and PTC X[1]/Y[17]/DS[17]; resets to I/O, HI-Z.
28 PA10 bidirectional PA10 high-sink I/O on VDDIO with EXTINT[10], AIN[10], SERCOM0 PAD[2], SERCOM2 PAD[2], TCC1 WO[0], TCC0 WO[2], GCLK IO[4], IN[5], QDI[2] and PTC X[2]/Y[18]/DS[18]; resets to I/O, HI-Z.
29 PA11 bidirectional PA11 high-sink I/O on VDDIO with EXTINT[11], AIN[11], SERCOM0 PAD[3], SERCOM2 PAD[3], TCC1 WO[1], TCC0 WO[3], GCLK IO[5], OUT[1] and PTC X[3]/Y[19]/DS[19]; resets to I/O, HI-Z.
30 VDDIO power_in I/O supply pin that powers the I/O lines and XOSC; VDDIO must be less than or equal to VDDIN = AVDD = VDD.
31 GND power_in Ground reference for the digital I/O and core supplies.
32 PB10 bidirectional PB10 high-sink I/O on VDDIO with EXTINT[10], SERCOM4 PAD[2], TC1 WO[0], TCC0 WO[4], CAN1 TX, GCLK IO[4] and IN[5]; CAN is available only on PIC32CM JH01 devices; resets to I/O, HI-Z.
33 PB11 bidirectional PB11 high-sink I/O on VDDIO with EXTINT[11], SERCOM4 PAD[3], TC1 WO[1], TCC0 WO[5], CAN1 RX, GCLK IO[5] and OUT[1]; CAN is available only on PIC32CM JH01 devices; resets to I/O, HI-Z.
34 PB12 bidirectional PB12 I/O on VDDIO with EXTINT[12], SERCOM4 PAD[0], TC0 WO[0], TCC0 WO[6], GCLK IO[6] and PTC X[12]/Y[28]/DS[28]; resets to I/O, HI-Z.
35 PB13 bidirectional PB13 I/O on VDDIO with EXTINT[13], SERCOM4 PAD[1], TC0 WO[1], TCC0 WO[7], GCLK IO[7] and PTC X[13]/Y[29]/DS[29]; resets to I/O, HI-Z.
36 PB14 bidirectional PB14 I/O on VDDIO with EXTINT[14], SERCOM4 PAD[2], TC1 WO[0], TC7 WO[0], CAN1 TX, GCLK IO[0], IN[9] and PTC X[14]/Y[30]/DS[30]; resets to I/O, HI-Z.
37 PB15 bidirectional PB15 I/O on VDDIO with EXTINT[15], SERCOM4 PAD[3], TC1 WO[1], TC7 WO[1], CAN1 RX, GCLK IO[1], IN[10] and PTC X[15]/Y[31]/DS[31]; resets to I/O, HI-Z.
38 PC08 bidirectional PC08 I/O on VDDIO with EXTINT[0] and SERCOM6 PAD[0]; resets to I/O, HI-Z.
39 PC09 bidirectional PC09 I/O on VDDIO with EXTINT[1] and SERCOM6 PAD[1]; resets to I/O, HI-Z.
40 PC10 bidirectional PC10 I/O on VDDIO with EXTINT[2] and SERCOM6 PAD[2]; resets to I/O, HI-Z.
41 PC11 bidirectional PC11 I/O on VDDIO with EXTINT[3] and SERCOM6 PAD[3]; resets to I/O, HI-Z.
42 PC12 bidirectional PC12 I/O on VDDIO with EXTINT[4] and SERCOM7 PAD[0]; resets to I/O, HI-Z.
43 PC13 bidirectional PC13 I/O on VDDIO with EXTINT[5] and SERCOM7 PAD[1]; resets to I/O, HI-Z.
44 PC14 bidirectional PC14 I/O on VDDIO with EXTINT[6] and SERCOM7 PAD[2]; resets to I/O, HI-Z.
45 PC15 bidirectional PC15 I/O on VDDIO with EXTINT[7] and SERCOM7 PAD[3]; resets to I/O, HI-Z.
46 PA12 bidirectional PA12 I/O on VDDIO with EXTINT[12], SERCOM2 PAD[0], SERCOM4 PAD[0], TCC2 WO[0], TCC0 WO[6] and CMP[0]; resets to I/O, HI-Z.
47 PA13 bidirectional PA13 I/O on VDDIO with EXTINT[13], SERCOM2 PAD[1], SERCOM4 PAD[1], TCC2 WO[1], TCC0 WO[7] and CMP[1]; resets to I/O, HI-Z.
48 PA14, XIN passive PA14 I/O on VDDIO, also the crystal or external clock input XIN with EXTINT[14], SERCOM2 PAD[2], SERCOM4 PAD[2], TC4 WO[0], TCC0 WO[4] and GCLK IO[0]; resets to I/O, HI-Z.
49 PA15, XOUT passive PA15 I/O on VDDIO, also the crystal output XOUT with EXTINT[15], SERCOM2 PAD[3], SERCOM4 PAD[3], TC4 WO[1], TCC0 WO[5] and GCLK IO[1]; resets to I/O, HI-Z.
50 GND power_in Ground reference for the digital I/O and core supplies.
51 VDDIO power_in I/O supply pin that powers the I/O lines and XOSC; VDDIO must be less than or equal to VDDIN = AVDD = VDD.
52 PA16 bidirectional PA16 I/O on VDDIO with EXTINT[0], SERCOM1 PAD[0], SERCOM3 PAD[0], TCC2 WO[0], TCC0 WO[6], QDI[0], GCLK IO[2], IN[0] and PTC X[4]/Y[20]/DS[20]; resets to I/O, HI-Z.
53 PA17 bidirectional PA17 I/O on VDDIO with EXTINT[1], SERCOM1 PAD[1], SERCOM3 PAD[1], TCC2 WO[1], TCC0 WO[7], QDI[1], GCLK IO[3], IN[1] and PTC X[5]/Y[21]/DS[21]; resets to I/O, HI-Z.
54 PA18 bidirectional PA18 I/O on VDDIO with EXTINT[2], SERCOM1 PAD[2], SERCOM3 PAD[2], TC4 WO[0], TCC0 WO[2], QDI[2], CMP[0], IN[2] and PTC X[6]/Y[22]/DS[22]; resets to I/O, HI-Z.
55 PA19 bidirectional PA19 I/O on VDDIO with EXTINT[3], SERCOM1 PAD[3], SERCOM3 PAD[3], TC4 WO[1], TCC0 WO[3], CMP[1], OUT[0] and PTC X[7]/Y[23]/DS[23]; resets to I/O, HI-Z.
56 PC16 bidirectional PC16 I/O on VDDIO with EXTINT[8], SERCOM6 PAD[0] and SERCOM7 PAD[0]; resets to I/O, HI-Z.
57 PC17 bidirectional PC17 I/O on VDDIO with EXTINT[9], SERCOM6 PAD[1] and SERCOM7 PAD[1]; resets to I/O, HI-Z.
58 PC18 bidirectional PC18 I/O on VDDIO with EXTINT[10], SERCOM6 PAD[2] and SERCOM7 PAD[2]; resets to I/O, HI-Z.
59 PC19 bidirectional PC19 I/O on VDDIO with EXTINT[11], SERCOM6 PAD[3] and SERCOM7 PAD[3]; resets to I/O, HI-Z.
60 PC20 bidirectional PC20 I/O on VDDIO with EXTINT[12] and CCL IN[9]; resets to I/O, HI-Z.
61 PC21 bidirectional PC21 I/O on VDDIO with EXTINT[13] and CCL IN[10]; resets to I/O, HI-Z.
62 GND power_in Ground reference for the digital I/O and core supplies.
63 VDDIO power_in I/O supply pin that powers the I/O lines and XOSC; VDDIO must be less than or equal to VDDIN = AVDD = VDD.
64 PB16 bidirectional PB16 I/O on VDDIO with EXTINT[0], SERCOM5 PAD[0], TC2 WO[0], TCC0 WO[4], GCLK IO[2] and IN[11]; resets to I/O, HI-Z.
65 PB17 bidirectional PB17 I/O on VDDIO with EXTINT[1], SERCOM5 PAD[1], TC2 WO[1], TCC0 WO[5], GCLK IO[3] and OUT[3]; resets to I/O, HI-Z.
66 PB18 bidirectional PB18 I/O on VDDIO with EXTINT[2], SERCOM5 PAD[2], SERCOM3 PAD[2] and GCLK IO[4]; resets to I/O, HI-Z.
67 PB19 bidirectional PB19 I/O on VDDIO with EXTINT[3], SERCOM5 PAD[3], SERCOM3 PAD[3] and GCLK IO[5]; resets to I/O, HI-Z.
68 PB20 bidirectional PB20 I/O on VDDIO with EXTINT[4], SERCOM3 PAD[0], SERCOM2 PAD[0] and GCLK IO[6]; resets to I/O, HI-Z.
69 PB21 bidirectional PB21 I/O on VDDIO with EXTINT[5], SERCOM3 PAD[1], SERCOM2 PAD[1] and GCLK IO[7]; resets to I/O, HI-Z.
70 PA20 bidirectional PA20 I/O on VDDIO with EXTINT[4], SERCOM5 PAD[2], SERCOM3 PAD[2], TC3 WO[0], TCC0 WO[6], GCLK IO[4] and PTC X[8]/Y[24]/DS[24]; resets to I/O, HI-Z.
71 PA21 bidirectional PA21 I/O on VDDIO with EXTINT[5], SERCOM5 PAD[3], SERCOM3 PAD[3], TC3 WO[1], TCC0 WO[7], GCLK IO[5] and PTC X[9]/Y[25]/DS[25]; resets to I/O, HI-Z.
72 PA22 bidirectional PA22 I/O on VDDIO with EXTINT[6], SERCOM3 PAD[0], SERCOM5 PAD[0], TC0 WO[0], TCC0 WO[4], GCLK IO[6], IN[6] and PTC X[10]/Y[26]/DS[26]; resets to I/O, HI-Z.
73 PA23 bidirectional PA23 I/O on VDDIO with EXTINT[7], SERCOM3 PAD[1], SERCOM5 PAD[1], TC0 WO[1], TCC0 WO[5], GCLK IO[7], IN[7] and PTC X[11]/Y[27]/DS[27]; resets to I/O, HI-Z.
74 PA24 bidirectional PA24 I/O on VDDIO with EXTINT[12], SERCOM3 PAD[2], SERCOM5 PAD[2], TC1 WO[0], TCC1 WO[2], CAN0 TX, CMP[2] and IN[8]; resets to I/O, HI-Z.
75 PA25 bidirectional PA25 I/O on VDDIO with EXTINT[13], SERCOM3 PAD[3], SERCOM5 PAD[3], TC1 WO[1], TCC1 WO[3], CAN0 RX, CMP[3] and OUT[2]; resets to I/O, HI-Z.
76 GND power_in Ground reference for the digital I/O and core supplies.
77 VDDIO power_in I/O supply pin that powers the I/O lines and XOSC; VDDIO must be less than or equal to VDDIN = AVDD = VDD.
78 PB22 bidirectional PB22 I/O on VDDIO with EXTINT[6], SERCOM5 PAD[2], TC3 WO[0], CAN0 TX, GCLK IO[0] and IN[0]; resets to I/O, HI-Z.
79 PB23 bidirectional PB23 I/O on VDDIO with EXTINT[7], SERCOM5 PAD[3], TC3 WO[1], CAN0 RX, GCLK IO[1] and OUT[0]; resets to I/O, HI-Z.
80 PB24 bidirectional PB24 I/O on VDDIO with EXTINT[8], SERCOM0 PAD[0], SERCOM4 PAD[0] and CMP[0]; resets to I/O, HI-Z.
81 PB25 bidirectional PB25 I/O on VDDIO with EXTINT[9], SERCOM0 PAD[1], SERCOM4 PAD[1] and CMP[1]; resets to I/O, HI-Z.
82 PC24 bidirectional PC24 I/O on VDDIO with EXTINT[0], SERCOM0 PAD[2] and SERCOM4 PAD[2]; resets to I/O, HI-Z.
83 PC25 bidirectional PC25 I/O on VDDIO with EXTINT[1], SERCOM0 PAD[3] and SERCOM4 PAD[3]; resets to I/O, HI-Z.
84 PC26 bidirectional PC26 I/O on VDDIO with EXTINT[2]; resets to I/O, HI-Z.
85 PC27 bidirectional PC27 I/O on VDDIO with EXTINT[3], SERCOM1 PAD[0] and CCL IN[4]; resets to I/O, HI-Z.
86 PC28 bidirectional PC28 I/O on VDDIO with EXTINT[4], SERCOM1 PAD[1] and CCL IN[5]; resets to I/O, HI-Z.
87 PA27 bidirectional PA27 I/O on VDDIN with EXTINT[15] and GCLK IO[0]; resets to I/O, HI-Z.
88 RESET input External reset pin, active level LOW, powered from VDDIN; resets with an internal pull-up enabled (PU).
89 PA28 bidirectional PA28 I/O on VDDIN with EXTINT[8] and GCLK IO[0]; resets to I/O, HI-Z.
90 GND power_in Ground reference for the digital I/O and core supplies.
91 VDDCORE power_out Internal regulated voltage output that powers the core, memories, peripherals and FDPLL96M; it is not an input for an external supply.
92 VDDIN power_in Main supply pin that powers I/O lines, OSC48M and the internal regulator; VDDIN and AVDD must carry the same voltage, referred to as VDD.
93 PA30, SWCLK input PA30 on VDDIN, used as the Serial Wire Debug clock SWCLK, which is internally pulled up at startup, with EXTINT[10], SERCOM1 PAD[2], TCC1 WO[0], GCLK IO[0] and IN[3] alternate functions.
94 PA31, SWDIO bidirectional PA31 on VDDIN, used as the Serial Wire Debug bidirectional data SWDIO, with EXTINT[11], SERCOM1 PAD[3], TCC1 WO[1] and OUT[1] alternate functions.
95 PB30 bidirectional PB30 I/O on VDDIN with EXTINT[14], SERCOM5 PAD[0], TCC0 WO[0], TCC1 WO[2] and CMP[2]; resets to I/O, HI-Z.
96 PB31 bidirectional PB31 I/O on VDDIN with EXTINT[15], SERCOM5 PAD[1], TCC0 WO[1], TCC1 WO[3] and CMP[3]; resets to I/O, HI-Z.
97 PB00 bidirectional PB00 I/O on AVDD with EXTINT[0], AIN[0], SERCOM5 PAD[2], TC3 WO[0], TC6 WO[0], IN[1] and PTC Y[6]/DS[6]; resets to I/O, HI-Z.
98 PB01 bidirectional PB01 I/O on AVDD with EXTINT[1], AIN[1], SERCOM5 PAD[3], TC3 WO[1], TC6 WO[1], IN[2] and PTC Y[7]/DS[7]; resets to I/O, HI-Z.
99 PB02 bidirectional PB02 I/O on AVDD with EXTINT[2], AIN[2], SERCOM5 PAD[0], TC2 WO[0], TC5 WO[0], OUT[0] and PTC Y[8]/DS[8]; resets to I/O, HI-Z.
100 PB03 bidirectional PB03 I/O on AVDD with EXTINT[3], AIN[3], SERCOM5 PAD[1], TC2 WO[1], TC5 WO[1] and PTC Y[9]/DS[9]; resets to I/O, HI-Z.

Key specifications

Parameter Value
Manufacturer MICROCHIP TECHNOLOGY
Package TQFP-100(14x14)
Category Global Sourcing Parts
Pins 100

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin configurations, including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. 990

CAD (KiCad official)

  • Symbol: PIC32CM5164JH01100-I
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: pic32cm5164jh01100-i-etched.step / pic32cm5164jh01100-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic32cm5164jh01100-i.step / pic32cm5164jh01100-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MICROCHIP TECHNOLOGY datasheet (1226 pp, sha256 b5b81c05ee290f2c, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF