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PIC24FJ64GB106-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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PIC24FJ64GB106-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)

PIC24FJ64GB106-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RE5 bidirectional PORTE digital I/O (ST) multiplexed with PMD5 parallel master port data and CN63 change notification.
2 RE6 bidirectional PORTE digital I/O (ST) multiplexed with PMD6, SCL3 (I2C3 clock) and CN64.
3 RE7 bidirectional PORTE digital I/O (ST) multiplexed with PMD7, SDA3 (I2C3 data) and CN65.
4 RG6 bidirectional PORTG digital I/O (ST) multiplexed with PMA5, C1IND comparator input, RP21 and CN8.
5 RG7 bidirectional PORTG digital I/O (ST) multiplexed with PMA4, C1INC comparator input, RP26 and CN9.
6 RG8 bidirectional PORTG digital I/O (ST) multiplexed with PMA3, C2IND comparator input, RP19 and CN10.
7 MCLR input Master Clear (device Reset) input, ST buffer; brought low to cause a Reset.
8 RG9 bidirectional PORTG digital I/O (ST) multiplexed with PMA2, C2INC comparator input, RP27 and CN11.
9 VSS power_in Ground reference for logic and I/O pins.
10 VDD power_in Positive supply for peripheral digital logic and I/O pins.
11 RB5 bidirectional PORTB I/O (ST) with AN5 analog input, C1INA, PGEC3 ICSP clock, RP18, VBUSON (USB OTG charge pump control) and CN7.
12 RB4 bidirectional PORTB I/O (ST) with AN4 analog input, C1INB, PGED3 ICSP data, RP28, USBOEN (USB output enable) and CN6.
13 RB3 bidirectional PORTB I/O (ST) with AN3 analog input, C2INA, VPIO (external USB transceiver D+ I/O) and CN5.
14 RB2 bidirectional PORTB I/O (ST) with AN2 analog input, C2INB, VMIO (external USB transceiver D- I/O), RP13 and CN4.
15 RB1 bidirectional PORTB I/O (ST) with AN1 analog input, VREF- A/D and comparator low reference, PGEC1 ICSP clock, RP1 and CN3.
16 RB0 bidirectional PORTB I/O (ST) with AN0 analog input, VREF+ A/D and comparator high reference, PGED1 ICSP data, PMA6, RP0 and CN2.
17 RB6 bidirectional PORTB I/O (ST) with AN6 analog input, PGEC2 ICSP clock, RP6 and CN24.
18 RB7 bidirectional PORTB I/O (ST) with AN7 analog input, PGED2 ICSP data, RP7, RCV (USB receive input from external transceiver) and CN25.
19 AVDD power_in Positive supply for analog modules; must always be connected.
20 AVSS power_in Ground reference for analog modules; must always be connected.
21 RB8 bidirectional PORTB I/O (ST) with AN8 analog input, RP8 and CN26.
22 RB9 bidirectional PORTB I/O (ST) with AN9 analog input, PMA7, RP9 and CN27.
23 RB10 bidirectional PORTB I/O (ST) with AN10 analog input, CVREF comparator reference output, PMA13, TMS JTAG mode select and CN28.
24 RB11 bidirectional PORTB I/O (ST) with AN11 analog input, PMA12, TDO JTAG data output and CN29.
25 VSS power_in Ground reference for logic and I/O pins.
26 VDD power_in Positive supply for peripheral digital logic and I/O pins.
27 RB12 bidirectional PORTB I/O (ST) with AN12 analog input, CTED2 CTMU edge input, PMA11, TCK JTAG clock and CN30.
28 RB13 bidirectional PORTB I/O (ST) with AN13 analog input, CTED1 CTMU edge input, PMA10, TDI JTAG data input and CN31.
29 RB14 bidirectional PORTB I/O (ST) with AN14 analog input, CTPLS CTMU pulse output, PMA1, RP14 and CN32.
30 RB15 bidirectional PORTB I/O (ST) with AN15 analog input, REFO reference clock output, PMA0, RP29 and CN12.
31 RF4 bidirectional PORTF digital I/O (ST) multiplexed with PMA9, RP10, SDA2 (I2C2 data) and CN17.
32 RF5 bidirectional PORTF digital I/O (ST) multiplexed with PMA8, RP17, SCL2 (I2C2 clock) and CN18.
33 RF3 bidirectional PORTF digital I/O (ST) multiplexed with USBID (USB OTG ID, OTG mode only), RP16 and CN71.
34 VBUS power_in USB voltage, Host mode (5V).
35 VUSB power_in USB voltage (3.3V).
36 D- bidirectional USB differential minus line (internal transceiver); shared with RG3 input.
37 D+ bidirectional USB differential plus line (internal transceiver); shared with RG2 input.
38 VDD power_in Positive supply for peripheral digital logic and I/O pins.
39 OSCI input Main oscillator input / CLKI clock input (analog level), shared with RC12 and CN23.
40 OSCO output Main oscillator output / CLKO system clock output, shared with RC15 and CN22.
41 VSS power_in Ground reference for logic and I/O pins.
42 RD8 bidirectional PORTD digital I/O (ST) multiplexed with RP2, RTCC alarm/seconds output, DMLN (D- pull-down control) and CN53.
43 RD9 bidirectional PORTD digital I/O (ST) multiplexed with RP4, SDA1 (I2C1 data), DPLN (D+ pull-down control) and CN54.
44 RD10 bidirectional PORTD digital I/O (ST) multiplexed with RP3, SCL1 (I2C1 clock), PMCS2 and CN55.
45 RD11 bidirectional PORTD digital I/O (ST) multiplexed with RP12, PMCS1 chip select/address bit 15 (ST/TTL) and CN56.
46 RD0 bidirectional PORTD digital I/O (ST) multiplexed with RP11, INT0 external interrupt, DMH (D- pull-up control) and CN49.
47 RC13 bidirectional PORTC digital I/O (ST) multiplexed with SOSCI secondary oscillator input, C3IND comparator input and CN1.
48 RC14 bidirectional PORTC digital I/O (ST) multiplexed with SOSCO secondary oscillator output, T1CK Timer1 clock, C3INC, RPI37 and CN0.
49 RD1 bidirectional PORTD digital I/O (ST) multiplexed with RP24, VCPCON (USB OTG VBUS PWM/charge output) and CN50.
50 RD2 bidirectional PORTD digital I/O (ST) multiplexed with RP23, DPH (D+ pull-up control) and CN51.
51 RD3 bidirectional PORTD digital I/O (ST) multiplexed with RP22, PMBE parallel master port byte enable strobe and CN52.
52 RD4 bidirectional PORTD digital I/O (ST) multiplexed with RP25, PMWR parallel master port write strobe and CN13.
53 RD5 bidirectional PORTD digital I/O (ST) multiplexed with RP20, PMRD parallel master port read strobe and CN14.
54 RD6 bidirectional PORTD digital I/O (ST) multiplexed with C3INB comparator input and CN15.
55 RD7 bidirectional PORTD digital I/O (ST) multiplexed with C3INA comparator input and CN16.
56 VCAP/VDDCORE passive External filter capacitor connection when regulator is enabled (10 µF, low-ESR <5 Ω, not tied to VDD); core supply input when regulator is disabled.
57 ENVREG input Voltage regulator enable (ST); tie to VDD to enable the regulator or to ground to disable it.
58 RF0 bidirectional PORTF digital I/O (ST) multiplexed with VBUSST (USB OTG charge pump feedback), VCMPST1 (VBUS boost comparator input 1) and CN68.
59 RF1 bidirectional PORTF digital I/O (ST) multiplexed with VCMPST2 (VBUS boost comparator input 2) and CN69.
60 RE0 bidirectional PORTE digital I/O (ST) multiplexed with PMD0 parallel master port data (ST/TTL) and CN58.
61 RE1 bidirectional PORTE digital I/O (ST) multiplexed with PMD1 parallel master port data (ST/TTL) and CN59.
62 RE2 bidirectional PORTE digital I/O (ST) multiplexed with PMD2 parallel master port data (ST/TTL) and CN60.
63 RE3 bidirectional PORTE digital I/O (ST) multiplexed with PMD3 parallel master port data (ST/TTL) and CN61.
64 RE4 bidirectional PORTE digital I/O (ST) multiplexed with PMD4 parallel master port data (ST/TTL) and CN62.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (regulator enabled) VDD 2.2 3.6 V Regulator enabled 313
Supply Voltage (regulator disabled) VDD 3.6 V Regulator disabled, VDD >= VDDCORE 313
Core Supply Voltage VDDCORE 2 2.75 V Regulator disabled 313
RAM Data Retention Voltage VDR 1.5 V 313
VDD Rise Rate for POR SVDD 0.05 V/ms 0-3.3V in 0.1s; 0-2.5V in 60 ms 313
Operating Ambient Temperature TA -40 85 °C Industrial 312
Operating Junction Temperature TJ -40 125 °C 312
Operating Current IDD 1.1 1.7 mA +25°C, 3.3V, 1 MIPS 314
Operating Current IDD 18.2 24 mA +25°C, 3.3V, 16 MIPS 314
Operating Current IDD 4.3 6 mA +25°C, 3.3V, 4 MIPS 314
Power-Down Current IPD 0.15 1 µA +25°C, 2.0V, base power-down 316
Power-Down Current IPD 4 10 µA +25°C, 3.3V, base power-down 316
Output Low Voltage, I/O Ports VOL 0.4 V IOL = 8.5 mA, VDD = 3.6V 319
Output High Voltage, I/O Ports VOH 3 V IOH = -3.0 mA, VDD = 3.6V 319
Output High Voltage, I/O Ports VOH 2.4 V IOH = -6.0 mA, VDD = 3.6V 319
Output High Voltage, I/O Ports VOH 1.65 V IOH = -1.0 mA, VDD = 2.0V 319
Output High Voltage, I/O Ports VOH 1.4 V IOH = -3.0 mA, VDD = 2.0V 319
Flash Cell Endurance EP 10000 E/W -40C to +85C 319
Flash Data Retention TRETD 20 Year Provided no other specifications are violated 319
VDDCORE for Self-Timed Writes VDDCORE 2.25 3.6 V 319
VDD for Self-Timed Writes VDD 2.35 3.6 V 319
Self-Timed Page Erase Time TIE 40 ms 319
BOR Voltage on VDD, High-to-Low VBOR 2.05 V Voltage regulator enabled 313
Self-Timed Write Cycle Time TIW 3 ms 319
Supply Current during Programming IDDP 7 mA 319
Ambient temperature under bias -40 100 °C 311
Storage temperature -65 150 °C 311
Voltage on VDD with respect to VSS VDD -0.3 4 V 311
Voltage on any combined analog and digital pin and MCLR -0.3 V max is VDD + 0.3V, with respect to VSS 311
Voltage on any digital only pin -0.3 6 V with respect to VSS 311
Voltage on VDDCORE VDDCORE -0.3 3 V with respect to VSS 311
Package Thermal Resistance, 10x10x1 mm TQFP θJA 76.6 °C/W Note 1: package simulation 312

CAD (KiCad official)

  • Symbol: PIC24FJ64GB106-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: pic24fj64gb106-i-etched.step / pic24fj64gb106-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic24fj64gb106-i.step / pic24fj64gb106-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (352 pp, sha256 7d2ee89c95aba693, retrieved 2026-10-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF