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PIC24FJ256GA106T-I

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Microchip Tech MICROCHIP, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC24FJ256GA106T-I

Microchip Tech · MICROCHIP · TQFP-64(10x10)

PIC24FJ256GA106T-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PMD5/RE5/CN63 bidirectional PORTE digital I/O RE5 with PMP data bit 5 and interrupt-on-change CN63; ST/TTL input buffer.
2 PMD6/RE6/SCL3/CN64 bidirectional PORTE I/O RE6 with PMP data bit 6, I2C3 clock SCL3 and CN64.
3 PMD7/RE7/SDA3/CN65 bidirectional PORTE I/O RE7 with PMP data bit 7, I2C3 data SDA3 and CN65.
4 RG6/RP21/PMA5/C1IND/CN8 bidirectional PORTG I/O RG6, remappable RP21, PMP address 5, Comparator 1 input D and CN8.
5 RG7/RP26/PMA4/C1INC/CN9 bidirectional PORTG I/O RG7, remappable RP26, PMP address 4, Comparator 1 input C and CN9.
6 RG8/RP19/PMA3/C2IND/CN10 bidirectional PORTG I/O RG8, remappable RP19, PMP address 3, Comparator 2 input D and CN10.
7 MCLR input Master Clear (device Reset) input; brought low to cause a Reset, Schmitt Trigger buffer.
8 RG9/RP27/PMA2/C2INC/CN11 bidirectional PORTG I/O RG9, remappable RP27, PMP address 2, Comparator 2 input C and CN11.
9 VSS power_in Ground reference for logic and I/O pins.
10 VDD power_in Positive supply for peripheral digital logic and I/O pins.
11 PGEC3/AN5/C1INA/RP18/CN7/RB5 bidirectional PORTB I/O RB5 with A/D input AN5, Comparator 1 input A, RP18, ICSP clock PGEC3 and CN7.
12 PGED3/AN4/C1INB/RP28/CN6/RB4 bidirectional PORTB I/O RB4 with A/D input AN4, Comparator 1 input B, RP28, ICSP data PGED3 and CN6.
13 AN3/C2INA/CN5/RB3 bidirectional PORTB I/O RB3 with A/D input AN3, Comparator 2 input A and CN5.
14 AN2/C2INB/RP13/CN4/RB2 bidirectional PORTB I/O RB2 with A/D input AN2, Comparator 2 input B, RP13 and CN4.
15 PGEC1/AN1/VREF-/RP1/CN3/RB1 bidirectional PORTB I/O RB1 with AN1, A/D and comparator low reference input VREF-, RP1, ICSP clock PGEC1 and CN3.
16 RB0/AN0/VREF+/RP0/PGED1/PMA6/CN2 bidirectional PORTB I/O RB0 with AN0, high reference input VREF+, RP0, ICSP data PGED1, PMP address 6 and CN2.
17 PGEC2/AN6/RP6/CN24/RB6 bidirectional PORTB I/O RB6 with A/D input AN6, RP6, ICSP clock PGEC2 and CN24.
18 PGED2/AN7/RP7/CN25/RB7 bidirectional PORTB I/O RB7 with A/D input AN7, RP7, ICSP data PGED2 and CN25.
19 AVDD power_in Positive supply for analog modules; must always be connected.
20 AVSS power_in Ground reference for analog modules; must always be connected.
21 AN8/RP8/CN26/RB8 bidirectional PORTB I/O RB8 with A/D input AN8, RP8 and CN26.
22 RB9/AN9/RP9/PMA7/CN27 bidirectional PORTB I/O RB9 with A/D input AN9, RP9, PMP address 7 and CN27.
23 RB10/AN10/CVREF/PMA13/TMS/CN28 bidirectional PORTB I/O RB10 with AN10, comparator voltage reference output CVREF, PMP address 13, JTAG TMS and CN28.
24 RB11/AN11/PMA12/TDO/CN29 bidirectional PORTB I/O RB11 with AN11, PMP address 12, JTAG TDO output and CN29.
25 VSS power_in Ground reference for logic and I/O pins.
26 VDD power_in Positive supply for peripheral digital logic and I/O pins.
27 RB12/AN12/CTED2/PMA11/TCK/CN30 bidirectional PORTB I/O RB12 with AN12, CTMU edge input 2, PMP address 11, JTAG TCK and CN30.
28 RB13/AN13/CTED1/PMA10/TDI/CN31 bidirectional PORTB I/O RB13 with AN13, CTMU edge input 1, PMP address 10, JTAG TDI and CN31.
29 RB14/AN14/CTPLS/RP14/PMA1/CN32 bidirectional PORTB I/O RB14 with AN14, CTMU pulse output, RP14, PMP address 1 and CN32.
30 RB15/AN15/REFO/RP29/PMA0/CN12 bidirectional PORTB I/O RB15 with AN15, reference clock output REFO, RP29, PMP address 0 and CN12.
31 RF4/RP10/PMA9/SDA2/CN17 bidirectional PORTF I/O RF4 with RP10, PMP address 9, I2C2 data SDA2 and CN17.
32 RF5/RP17/PMA8/SCL2/CN18 bidirectional PORTF I/O RF5 with RP17, PMP address 8, I2C2 clock SCL2 and CN18.
33 RP16/CN71/RF3 bidirectional PORTF I/O RF3 with remappable RP16 and CN71.
34 RP30/CN70/RF2 bidirectional PORTF I/O RF2 with remappable RP30 and CN70.
35 RF6/INT0/RPI45/CN72 bidirectional PORTF I/O RF6 with external interrupt INT0, remappable input RPI45 and CN72.
36 SDA1/CN84/RG3 bidirectional PORTG I/O RG3 with I2C1 data SDA1 and CN84.
37 SCL1/CN83/RG2 bidirectional PORTG I/O RG2 with I2C1 clock SCL1 and CN83.
38 VDD power_in Positive supply for peripheral digital logic and I/O pins.
39 OSCI/CLKI/CN23/RC12 input Main oscillator input / external clock input, also PORTC I/O RC12 and CN23.
40 OSCO/CLKO/CN22/RC15 bidirectional Main oscillator output / system clock output, also PORTC I/O RC15 and CN22.
41 VSS power_in Ground reference for logic and I/O pins.
42 RTCC/RP2/CN53/RD8 bidirectional PORTD I/O RD8 with RP2, RTCC alarm/seconds pulse output and CN53.
43 RP4/CN54/RD9 bidirectional PORTD I/O RD9 with remappable RP4 and CN54.
44 RD10/RP3/PMCS2/CN55 bidirectional PORTD I/O RD10 with RP3, PMP chip select 2 / address bit 14 and CN55.
45 RD11/RP12/PMCS1/CN56 bidirectional PORTD I/O RD11 with RP12, PMP chip select 1 / address bit 15 and CN56.
46 RP11/CN49/RD0 bidirectional PORTD I/O RD0 with remappable RP11 and CN49.
47 SOSCI/C3IND/CN1/RC13 bidirectional PORTC I/O RC13 with secondary oscillator/Timer1 clock input SOSCI, Comparator 3 input D and CN1.
48 RC14/SOSCO/T1CK/C3INC/RPI37/CN0 bidirectional PORTC I/O RC14 with secondary oscillator output SOSCO, Timer1 clock T1CK, Comparator 3 input C, RPI37 and CN0.
49 RP24/CN50/RD1 bidirectional PORTD I/O RD1 with remappable RP24 and CN50.
50 RP23/CN51/RD2 bidirectional PORTD I/O RD2 with remappable RP23 and CN51.
51 RD3/RP22/PMBE/CN52 bidirectional PORTD I/O RD3 with RP22, PMP byte enable strobe and CN52.
52 RD4/RP25/PMWR/CN13 bidirectional PORTD I/O RD4 with RP25, PMP write strobe and CN13.
53 RD5/RP20/PMRD/CN14 bidirectional PORTD I/O RD5 with RP20, PMP read strobe and CN14.
54 C3INB/CN15/RD6 bidirectional PORTD I/O RD6 with Comparator 3 input B and CN15.
55 C3INA/CN16/RD7 bidirectional PORTD I/O RD7 with Comparator 3 input A and CN16.
56 VCAP/VDDCORE passive External filter capacitor (10 µF, low-ESR) connection with regulator enabled; core supply input when regulator disabled; must not be tied to VDD.
57 ENVREG input Voltage regulator enable; tie to VDD to enable the regulator or to ground to disable it.
58 CN68/RF0 bidirectional PORTF I/O RF0 with interrupt-on-change CN68.
59 CN69/RF1 bidirectional PORTF I/O RF1 with interrupt-on-change CN69.
60 PMD0/RE0/CN58 bidirectional PORTE I/O RE0 with PMP data bit 0 and CN58.
61 PMD1/RE1/CN59 bidirectional PORTE I/O RE1 with PMP data bit 1 and CN59.
62 PMD2/RE2/CN60 bidirectional PORTE I/O RE2 with PMP data bit 2 and CN60.
63 PMD3/RE3/CN61 bidirectional PORTE I/O RE3 with PMP data bit 3 and CN61.
64 PMD4/RE4/CN62 bidirectional PORTE I/O RE4 with PMP data bit 4 and CN62.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: PIC24FJ256GA106T-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: pic24fj256ga106t-i-etched.step / pic24fj256ga106t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic24fj256ga106t-i.step / pic24fj256ga106t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (332 pp, sha256 a3c9f7848654cb8b, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF