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PIC24FJ256GA106-I

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Microchip Tech MICROCHIP, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC24FJ256GA106-I

Microchip Tech · MICROCHIP · TQFP-64(10x10)

PIC24FJ256GA106-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RE5/PMD5/CN63 bidirectional PORTE digital I/O with ST/TTL input buffers, also Parallel Master Port data bit 5.
2 RE6/PMD6/SCL3/CN64 bidirectional PORTE digital I/O with ST/TTL input buffers, also I2C3 synchronous serial clock input/output.
3 RE7/PMD7/SDA3/CN65 bidirectional PORTE digital I/O with ST/TTL input buffers, also I2C3 data input/output.
4 C1IND/RG6/RP21/CN8 passive Comparator 1 Input D analog input.
5 C1INC/RG7/RP26/CN9 passive Comparator 1 Input C analog input.
6 C2IND/RG8/RP19/CN10 passive Comparator 2 Input D analog input.
7 MCLR input Master Clear (device Reset) input; this line is brought low to cause a Reset.
8 C2INC/RG9/RP27/CN11 passive Comparator 2 Input C analog input.
9 VSS power_in Ground reference for logic and I/O pins.
10 VDD power_in Positive supply for peripheral digital logic and I/O pins.
11 C1INA/RB5/RP18/PGEC3/CN7 passive Comparator 1 Input A analog input.
12 C1INB/RB4/RP28/PGED3/CN6 passive Comparator 1 Input B analog input.
13 C2INA/RB3/CN5 passive Comparator 2 Input A analog input.
14 C2INB/RB2/RP13/CN4 passive Comparator 2 Input B analog input.
15 AN1/VREF-/RB1/RP1/PGEC1/CN3 passive A/D analog input AN1; this pin is also the VREF- (low) reference voltage input for the A/D and comparators.
16 AN0/VREF+/RB0/RP0/PGED1/CN2 passive A/D analog input AN0; this pin is also the VREF+ (high) reference voltage input for the A/D and comparators.
17 AN6/RB6/RP6/PGEC2/CN24 passive A/D analog input AN6.
18 AN7/RB7/RP7/PGED2/CN25 passive A/D analog input AN7.
19 AVDD power_in Positive supply for analog modules; must always be connected regardless of analog module use.
20 AVSS power_in Ground reference for analog modules; must always be connected regardless of analog module use.
21 AN8/RB8/RP8/CN26 passive A/D analog input AN8.
22 AN9/RB9/RP9/PMA7/CN27 passive A/D analog input AN9.
23 AN10/CVREF/RB10/TMS/CN28 passive A/D analog input AN10; the pin is shared with the comparator voltage reference output CVREF and JTAG TMS input.
24 AN11/RB11/TDO/PMA12/CN29 passive A/D analog input AN11; the pin is shared with the JTAG TDO output.
25 VSS power_in Ground reference for logic and I/O pins.
26 VDD power_in Positive supply for peripheral digital logic and I/O pins.
27 AN12/RB12/TCK/CTED2/PMA11/CN30 passive A/D analog input AN12; the pin is shared with the JTAG TCK input.
28 AN13/RB13/TDI/CTED1/PMA10/CN31 passive A/D analog input AN13; the pin is shared with the JTAG TDI input.
29 AN14/RB14/RP14/CTPLS/PMA1/CN32 passive A/D analog input AN14.
30 AN15/RB15/REFO/RP29/PMA0/CN12 passive A/D analog input AN15; the pin is shared with the REFO reference clock output.
31 RF4/SDA2/RP10/PMA9/CN17 bidirectional PORTF digital I/O with Schmitt Trigger input buffer, also I2C2 data input/output.
32 RF5/SCL2/RP17/PMA8/CN18 bidirectional PORTF digital I/O with Schmitt Trigger input buffer, also I2C2 clock input/output.
33 RF3/RP16/CN71 bidirectional PORTF digital I/O with Schmitt Trigger input buffer.
34 RF2/RP30/CN70 bidirectional PORTF digital I/O with Schmitt Trigger input buffer.
35 RF6/INT0/RPI45/CN72 bidirectional PORTF digital I/O with Schmitt Trigger input buffer, also external interrupt INT0 input.
36 RG3/SDA1/CN84 bidirectional PORTG digital I/O with Schmitt Trigger input buffer, also I2C1 data input/output.
37 RG2/SCL1/CN83 bidirectional PORTG digital I/O with Schmitt Trigger input buffer, also I2C1 clock input/output.
38 VDD power_in Positive supply for peripheral digital logic and I/O pins.
39 OSCI/CLKI/RC12/CN23 input Main oscillator input connection; also the main clock input connection CLKI.
40 OSCO/CLKO/RC15/CN22 output Main oscillator output connection; also provides the system clock output CLKO.
41 VSS power_in Ground reference for logic and I/O pins.
42 RD8/RP2/RTCC/CN53 bidirectional PORTD digital I/O with Schmitt Trigger input buffer; the pin is also the RTCC alarm/seconds pulse output.
43 RD9/RP4/CN54 bidirectional PORTD digital I/O with Schmitt Trigger input buffer.
44 RD10/RP3/PMCS2/CN55 bidirectional PORTD digital I/O with Schmitt Trigger input buffer; the pin is also the Parallel Master Port Chip Select 2 strobe.
45 RD11/RP12/PMCS1/CN56 bidirectional PORTD digital I/O with Schmitt Trigger input buffer; the pin is also the Parallel Master Port Chip Select 1 strobe.
46 RD0/RP11/CN49 bidirectional PORTD digital I/O with Schmitt Trigger input buffer.
47 RC13/SOSCI/CN1/C3IND bidirectional PORTC digital I/O with Schmitt Trigger input buffer; the pin is shared with the secondary oscillator input SOSCI.
48 RC14/SOSCO/T1CK/RPI37/CN0/C3INC bidirectional PORTC digital I/O with Schmitt Trigger input buffer; the pin is shared with the secondary oscillator output SOSCO and Timer1 clock T1CK.
49 RD1/RP24/CN50 bidirectional PORTD digital I/O with Schmitt Trigger input buffer.
50 RD2/RP23/CN51 bidirectional PORTD digital I/O with Schmitt Trigger input buffer.
51 RD3/RP22/PMBE/CN52 bidirectional PORTD digital I/O with Schmitt Trigger input buffer; the pin is also the Parallel Master Port byte enable strobe.
52 RD4/RP25/PMWR/CN13 bidirectional PORTD digital I/O with Schmitt Trigger input buffer; the pin is also the Parallel Master Port write strobe.
53 RD5/RP20/PMRD/CN14 bidirectional PORTD digital I/O with Schmitt Trigger input buffer; the pin is also the Parallel Master Port read strobe.
54 RD6/C3INB/CN15 bidirectional PORTD digital I/O with Schmitt Trigger input buffer; the pin is shared with Comparator 3 Input B.
55 RD7/C3INA/CN16 bidirectional PORTD digital I/O with Schmitt Trigger input buffer; the pin is shared with Comparator 3 Input A.
56 VCAP/VDDCORE passive External filter capacitor connection when the regulator is enabled; VDDCORE is the core supply when the regulator is disabled.
57 ENVREG input Voltage regulator enable input with Schmitt Trigger buffer.
58 RF0/CN68 bidirectional PORTF digital I/O with Schmitt Trigger input buffer.
59 RF1/CN69 bidirectional PORTF digital I/O with Schmitt Trigger input buffer.
60 RE0/PMD0/CN58 bidirectional PORTE digital I/O with ST/TTL input buffers, also Parallel Master Port data bit 0.
61 RE1/PMD1/CN59 bidirectional PORTE digital I/O with ST/TTL input buffers, also Parallel Master Port data bit 1.
62 RE2/PMD2/CN60 bidirectional PORTE digital I/O with ST/TTL input buffers, also Parallel Master Port data bit 2.
63 RE3/PMD3/CN61 bidirectional PORTE digital I/O with ST/TTL input buffers, also Parallel Master Port data bit 3.
64 RE4/PMD4/CN62 bidirectional PORTE digital I/O with ST/TTL input buffers, also Parallel Master Port data bit 4.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage on any digital only pin with respect to VSS -0.3 6 V 269
Voltage on VDD with respect to VSS -0.3 4 V 269
Voltage on VDDCORE with respect to VSS -0.3 3 V 269
Voltage on any combined analog and digital pin, and MCLR with respect to VSS -0.3 V max printed as VDD + 0.3V 269
Ambient temperature under bias -40 135 °C 269
Storage temperature -65 150 °C 269
Operating Junction Temperature Range TJ -40 140 °C 270
Operating Ambient Temperature Range TA -40 125 °C 270
Package Thermal Resistance, 10x10x1 mm TQFP JA 76.6 °C/W Note 1: junction to ambient 270
Supply Voltage VDD (regulator enabled) VDD 3.6 V Regulator enabled 271
Supply Voltage VDD (regulator disabled) VDD 3.6 V Regulator disabled 271
Supply Voltage VDDCORE VDDCORE 2 2.75 V Regulator disabled 271
RAM Data Retention Voltage VDR 1.5 V 271
VDD Rise Rate to Ensure Internal Power-on Reset Signal SVDD 0.05 V/ms 0-3.3V in 0.1s 271
Brown-Out Reset Voltage VBOR 1.9 2.1 2.25 V 271
BOR Hysteresis VBHYS 5 mV 271
Operating Current (IDD) DC20 IDD 0.83 1.2 mA -40°C, 2.0V, 1 MIPS, PMD bits set 273
Operating Current (IDD) DC20d IDD 1.1 1.7 mA -40°C, 3.3V, 1 MIPS, PMD bits set 273
Operating Current (IDD) DC23 IDD 3.3 4.5 mA -40°C, 2.0V, 4 MIPS, PMD bits set 273
Operating Current (IDD) DC24 IDD 18.2 24 mA -40°C, 2.5V, 16 MIPS, PMD bits set 273
Operating Current (IDD) LPRC DC31g IDD 120 281 µA +125°C, 3.3V, LPRC (31 kHz), PMD bits set 273
Idle Current (IIDLE) DC40 IIDLE 220 310 µA -40°C, 2.0V, 1 MIPS, core off, PMD bits set 274
Idle Current (IIDLE) DC47 IIDLE 4.4 5.6 mA 2.5V, 16 MIPS, core off, PMD bits set 274
Idle Current (IIDLE) FRC DC50g IIDLE 1.4 1.8 mA +125°C, 3.3V, FRC (4 MIPS) 274
Power-Down Current (IPD) DC60 IPD 0.1 1 µA -40°C, 2.0V, PMD bits set, PMSLP bit 0 276
Power-Down Current (IPD) DC60h IPD 11 36 µA +85°C, 3.3V, PMD bits set, PMSLP bit 0 276
Power-Down Current (IPD) DC60l IPD 36 120 µA +125°C, 3.3V, PMD bits set, PMSLP bit 0 276
Watchdog Timer Current DC61 IWDT 1.75 3 µA -40°C, 2.0V 276
RTCC + Timer1 w/32 kHz Crystal DC62 ITI32 2.5 7 µA -40°C, 2.0V 277
CNx Pull-up Current DI30 ICNPU 50 250 400 µA VDD = 3.3V, VPIN = 0 278
CNx Pull-Down Current DI30A ICNPD 80 µA VDD = 3.3V, VPIN = VDD 278
Input Leakage Current I/O Ports DI50 IIL 1 µA VSS≤VPIN≤VDD, pin high-impedance, -40°C≤TA≤+85°C 279
Input Leakage Current I/O Ports DI50 extended IIL 3 µA VSS≤VPIN≤VDD, pin high-impedance, -40°C≤TA≤+125°C 279
Total Input Injection Current IICT IICT -20 20 mA Absolute instantaneous sum of all input injection currents from I/O pins 280
Output Low Voltage I/O Ports DO10 VOL 0.4 V IOL = 8.5 mA, VDD = 3.6V 281
Output Low Voltage I/O Ports DO10 at 2.0V VOL 0.4 V IOL = 6.0 mA, VDD = 2.0V 281
Output High Voltage I/O Ports DO20 VOH 3 V IOH = -3.0 mA, VDD = 3.6V 281
Output High Voltage I/O Ports DO20 at 6 mA VOH 2.4 V IOH = -6.0 mA, VDD = 3.6V 281
Output High Voltage I/O Ports DO20 at 2.0V VOH 1.65 V IOH = -1.0 mA, VDD = 2.0V 281
Output High Voltage I/O Ports DO20 at 2.0V, 3 mA VOH 1.4 V IOH = -3.0 mA, VDD = 2.0V 281
Cell Endurance D130 EP 10000 E/W -40C to +85C 281
Self-Timed Write Supply Voltage VDD D132B VDD 2.35 3.6 V VPEW supply voltage for self-timed writes 281
Self-Timed Page Erase Time D133B TIE 40 ms 281
Characteristic Retention D134 TRETD 20 Year Provided no other specifications are violated 281
Supply Current During Programming D135 IDDP 7 mA 281
Regulator Output Voltage VRGOUT 2.5 V 282
Internal Band Gap Reference VBG 1.14 1.2 1.26 V Parameter characterized but not tested 282
External Filter Capacitor Value CEFC 4.7 10 µF Series resistance < 3 Ohm recommended; < 5 Ohm required 282
Regulator Start-up Time TVREG 10 µs PMSLP = 1, or any POR or BOR 282
Band Gap Reference Start-up Time TBG 1 ms 282
External CLKI Frequency EC, -40°C to +85°C FOSC 32 MHz EC, -40°C ≤ TA ≤ +85°C 285
External CLKI Frequency ECPLL, -40°C to +85°C FOSC 4 8 MHz ECPLL, -40°C ≤ TA ≤ +85°C 285
External CLKI Frequency EC, -40°C to +125°C FOSC 24 MHz EC, -40°C ≤ TA ≤ +125°C 285
External CLKI Frequency ECPLL, -40°C to +125°C FOSC 4 6 MHz ECPLL, -40°C ≤ TA ≤ +125°C 285
External Clock in (OSCI) Rise or Fall Time TosR,TosF 20 ns EC 285
CLKO Rise Time TckR 6 10 ns 285
CLKO Fall Time TckF 6 10 ns 285
PLL Output Frequency Range FSYS 16 32 MHz 286
PLL Start-up Time (Lock Time) TLOCK 2 ms 286
CLKO Stability (Jitter) DCLK -2 1 2 % 286
FRC Accuracy @ 8 MHz at +25°C -2 2 % +25°C, 3.0V≤VDD≤3.6V 286
LPRC Start-up Time TLPRC 40 µs 286
LPRC Accuracy @ 31 kHz -40 to +85°C -20 20 % -40°C≤TA≤+85°C, 3.0V≤VDD≤3.6V 286
Port Output Rise Time DO31 TIOR 10 25 ns 287
Port Output Fall Time DO32 TIOF 10 25 ns 287
INTx Pin High or Low Time DI35 TINP 20 ns output 287
CNx High or Low Time DI40 TRBP 2 TCY input 287
Power-up Time TPOR 2 µs 287
Internal State Reset Time TRST 50 µs 287
Reference Input Impedance AD09 ZVREF 10 K Impedance during sampling at 3.3V, +25°C 287
Recommended Impedance of Analog Voltage Source AD17 RIN 2.5 K 10-bit 287
Reference Voltage Input Current AD08 IVREF 1.25 mA External reference applied to VREF+/- pins 287
ADC Clock Period AD50 TAD 75 ns TCY = 75 ns, AD1CON3 in default state 288
Throughput Rate AD56 FCNV 500 ksps AVDD > 2.7V 288
Integral Nonlinearity AD21b INL 1 2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V 287
Differential Nonlinearity AD22b DNL 0.5 1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V 287
Gain Error AD23b GERR 1 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V 287
Offset Error AD24b EOFF 1 2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V 287
MCLR Pulse Width (low) SY10 TmcL 2 µs 289
Power-on Reset Delay SY12 TPOR 1 5 10 µs 289
I/O High-Impedance from MCLR Low or WDT Reset SY13 TIOZ 100 ns 289
Watchdog Timer Time-out Period SY20 1:32 prescaler TWDT 0.85 1 1.15 ms 1:32 prescaler 289
Watchdog Timer Time-out Period SY20 1:128 prescaler TWDT 3.4 4 4.6 ms 1:128 prescaler 289
Brown-out Reset Pulse Width SY25 TBOR 1 µs VDD < VBOR, voltage regulator disabled 289
Input Injection Setup Time UART TSETUP TSETUP 3 ns Start bit falling edge to system clock rising edge 290
SCKx Output Fall Time SP20 TscF 10 25 ns Assumes 50 pF load on all SPIx pins 292
SDOx Data Output Valid after SCKx Edge SP35 TscH2doV 30 ns 292
Setup Time of SDIx Data Input to SCKx Edge SP40 TdiV2scH 20 ns 292
Hold Time of SDIx Data Input to SCKx Edge SP41 TscH2diL 20 ns 292
OSCO/CLKO Pin Load Capacitance DO50 COSC2 15 pF In XT and HS modes when external clock is used to drive OSCI 283
All I/O Pins and OSCO Load Capacitance DO56 CIO 50 pF EC mode 283
SCLx, SDAx Bus Capacitance DO58 CB 400 pF In I2C mode 283

CAD (KiCad official)

  • Symbol: PIC24FJ256GA106-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: pic24fj256ga106-i-etched.step / pic24fj256ga106-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic24fj256ga106-i.step / pic24fj256ga106-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (332 pp, sha256 a3c9f7848654cb8b, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF