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PIC24FJ256DA210-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-100(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC24FJ256DA210-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-100(12x12)

PIC24FJ256DA210-I from Microchip Tech, in a TQFP-100(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GCLK/CN82/RG15 bidirectional PORTG digital I/O (RG15) with Schmitt Trigger input, also carrying the graphics display pixel clock GCLK output.
2 VDD power_in Positive supply for peripheral digital logic and I/O pins.
3 PMD5/CN63/RE5 bidirectional PORTE digital I/O (RE5) with Schmitt Trigger input, also used as EPMP data bus bit 5.
4 SCL3/PMD6/CN64/RE6 bidirectional PORTE digital I/O (RE6) with I2C3 serial clock input/output, also used as EPMP data bus bit 6.
5 SDA3/PMD7/CN65/RE7 bidirectional PORTE digital I/O (RE7) with I2C3 data input/output, also used as EPMP data bus bit 7.
6 RPI38/GD0/CN45/RC1 bidirectional PORTC digital I/O (RC1) with Schmitt Trigger input, also a remappable input-only pin (RPI38) and graphics data output GD0.
7 RPI39/GD8/CN46/RC2 bidirectional PORTC digital I/O (RC2) with Schmitt Trigger input, also a remappable input-only pin (RPI39) and graphics data output GD8.
8 RPI40/GD1/CN47/RC3 bidirectional PORTC digital I/O (RC3) with Schmitt Trigger input, also a remappable input-only pin (RPI40) and graphics data output GD1.
9 AN16/RPI41/PMCS2/PMA22/CN48/RC4 bidirectional PORTC digital I/O (RC4) with analog input AN16, also a remappable input-only pin (RPI41) and EPMP function.
10 AN17/C1IND/RP21/PMA5/PMA18/CN8/RG6 bidirectional PORTG digital I/O (RG6) with analog input AN17, comparator 1 input D and remappable output RP21.
11 AN18/C1INC/RP26/PMA4/PMA20/CN9/RG7 bidirectional PORTG digital I/O (RG7) with analog input AN18, comparator 1 input C and remappable output RP26.
12 AN19/C2IND/RP19/PMA3/PMA21/CN10/RG8 bidirectional PORTG digital I/O (RG8) with analog input AN19, comparator 2 input D and remappable output RP19.
13 MCLR input Master Clear input; bringing this line low causes a device Reset.
14 AN20/C2INC/RP27/PMA2/CN11/RG9 bidirectional PORTG digital I/O (RG9) with analog input AN20, comparator 2 input C and remappable output RP27.
15 VSS power_in Ground reference for logic and I/O pins.
16 VDD power_in Positive supply for peripheral digital logic and I/O pins.
17 TMS/CN33/RA0 bidirectional PORTA digital I/O (RA0) with Schmitt Trigger input, also JTAG Test Mode Select input TMS.
18 RPI33/PMCS1/CN66/RE8 bidirectional PORTE digital I/O (RE8) with Schmitt Trigger input, also a remappable input-only pin (RPI33) and EPMP chip select 1.
19 AN21/RPI34/PMA19/CN67/RE9 bidirectional PORTE digital I/O (RE9) with analog input AN21, also a remappable input-only pin (RPI34) and EPMP address bit 19.
20 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 bidirectional PORTB digital I/O (RB5) with analog input AN5, ICSP programming clock 3 and USB OTG charge pump control VBUSON.
21 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 bidirectional PORTB digital I/O (RB4) with analog input AN4, ICSP programming data 3 and USB output enable USBOEN.
22 AN3/C2INA/GD5/VPIO/CN5/RB3 bidirectional PORTB digital I/O (RB3) with analog input AN3 and USB differential plus input/output VPIO for external transceiver.
23 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 bidirectional PORTB digital I/O (RB2) with analog input AN2 and USB differential minus input/output VMIO for external transceiver.
24 PGEC1/AN1/VREF-/RP1/CN3/RB1 bidirectional PORTB digital I/O (RB1) with analog input AN1, ICSP programming clock 1 and negative A/D reference VREF-.
25 PGED1/AN0/VREF+/RP0/CN2/RB0 bidirectional PORTB digital I/O (RB0) with analog input AN0, ICSP programming data 1 and positive A/D reference VREF+.
26 PGEC2/AN6/RP6/CN24/RB6 bidirectional PORTB digital I/O (RB6) with analog input AN6, ICSP programming clock 2 and remappable output RP6.
27 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 bidirectional PORTB digital I/O (RB7) with analog input AN7, ICSP programming data 2, USB receive input RCV and graphics power enable GPWR.
28 VREF-/PMA7/CN41/RA9 power_in PORTA digital I/O (RA9) with alternate negative A/D reference VREF- and EPMP address bit 7.
29 VREF+/PMA6/CN42/RA10 power_in PORTA digital I/O (RA10) with alternate positive A/D reference VREF+ and EPMP address bit 6.
30 AVDD power_in Positive supply for analog modules; must always be connected regardless of analog feature use.
31 AVSS power_in Ground reference for analog modules; must always be connected regardless of analog feature use.
32 AN8/RP8/GD12/CN26/RB8 bidirectional PORTB digital I/O (RB8) with analog input AN8, remappable output RP8 and graphics data output GD12.
33 AN9/RP9/GD13/CN27/RB9 bidirectional PORTB digital I/O (RB9) with analog input AN9, remappable output RP9 and graphics data output GD13.
34 AN10/CVREF/PMA13/CN28/RB10 bidirectional PORTB digital I/O (RB10) with analog input AN10 and comparator voltage reference output CVREF.
35 AN11/PMA12/CN29/RB11 bidirectional PORTB digital I/O (RB11) with analog input AN11 and EPMP address bit 12.
36 VSS power_in Ground reference for logic and I/O pins.
37 VDD power_in Positive supply for peripheral digital logic and I/O pins.
38 TCK/CN34/RA1 bidirectional PORTA digital I/O (RA1) with Schmitt Trigger input, also JTAG Test Clock input TCK.
39 RP31/GD2/CN76/RF13 bidirectional PORTF digital I/O (RF13) with Schmitt Trigger input, remappable output RP31 and graphics data output GD2.
40 RPI32/PMA18/PMA5/CN75/RF12 bidirectional PORTF digital I/O (RF12) with Schmitt Trigger input, also a remappable input-only pin (RPI32) and EPMP address function.
41 AN12/PMA11/CTEDG2/CN30/RB12 bidirectional PORTB digital I/O (RB12) with analog input AN12, CTMU external edge input 2 and EPMP address bit 11.
42 AN13/PMA10/CTEDG1/CN31/RB13 bidirectional PORTB digital I/O (RB13) with analog input AN13, CTMU external edge input 1 and EPMP address bit 10.
43 AN14/CTPLS/RP14/PMA1/CN32/RB14 bidirectional PORTB digital I/O (RB14) with analog input AN14, CTMU pulse output CTPLS and remappable output RP14.
44 AN15/REFO/RP29/PMA0/CN12/RB15 bidirectional PORTB digital I/O (RB15) with analog input AN15, reference clock output REFO and remappable output RP29.
45 VSS power_in Ground reference for logic and I/O pins.
46 VDD power_in Positive supply for peripheral digital logic and I/O pins.
47 RPI43/GD14/CN20/RD14 bidirectional PORTD digital I/O (RD14) with Schmitt Trigger input, also a remappable input-only pin (RPI43) and graphics data output GD14.
48 RP5/GD15/CN21/RD15 bidirectional PORTD digital I/O (RD15) with Schmitt Trigger input, remappable output RP5 and graphics data output GD15.
49 RP10/PMA9/CN17/RF4 bidirectional PORTF digital I/O (RF4) with Schmitt Trigger input, remappable output RP10 and EPMP address bit 9.
50 RP17/PMA8/CN18/RF5 bidirectional PORTF digital I/O (RF5) with Schmitt Trigger input, remappable output RP17 and EPMP address bit 8.
51 RP16/USBID/CN71/RF3 bidirectional PORTF digital I/O (RF3) with Schmitt Trigger input, remappable output RP16 and USB OTG ID input USBID.
52 RP30/GD3/CN70/RF2 bidirectional PORTF digital I/O (RF2) with Schmitt Trigger input, remappable output RP30 and graphics data output GD3.
53 RP15/GD9/CN74/RF8 bidirectional PORTF digital I/O (RF8) with Schmitt Trigger input, remappable output RP15 and graphics data output GD9.
54 VBUS/CN73/RF7 power_in PORTF digital I/O (RF7) with Schmitt Trigger input; also USB VBUS voltage input (5V in host mode).
55 VUSB power_in USB voltage supply (3.3V) for the internal USB transceiver.
56 D-/CN84/RG3 bidirectional USB differential minus line (internal transceiver), also PORTG digital I/O RG3 with Schmitt Trigger input.
57 D+/CN83/RG2 bidirectional USB differential plus line (internal transceiver), also PORTG digital I/O RG2 with Schmitt Trigger input.
58 SCL2/CN35/RA2 bidirectional PORTA digital I/O (RA2) with I2C2 serial clock input/output.
59 SDA2/PMA20/PMA4/CN36/RA3 bidirectional PORTA digital I/O (RA3) with I2C2 data input/output and EPMP address function.
60 TDI/PMA21/PMA3/CN37/RA4 bidirectional PORTA digital I/O (RA4) with Schmitt Trigger input, also JTAG Test Data Input TDI.
61 TDO/CN38/RA5 bidirectional PORTA digital I/O (RA5) with JTAG Test Data Output TDO.
62 VDD power_in Positive supply for peripheral digital logic and I/O pins.
63 OSCI/CLKI/CN23/RC12 input Main oscillator input connection, also external clock input CLKI and PORTC digital I/O RC12.
64 OSCO/CLKO/CN22/RC15 output Main oscillator output connection, also system clock output CLKO (FOSC/2) when configured.
65 VSS power_in Ground reference for logic and I/O pins.
66 SCL1/RPI36/PMA22/PMCS2/CN43/RA14 bidirectional PORTA digital I/O (RA14) with I2C1 serial clock input/output and a remappable input-only pin (RPI36).
67 SDA1/RPI35/PMBE1/CN44/RA15 bidirectional PORTA digital I/O (RA15) with I2C1 data input/output and a remappable input-only pin (RPI35).
68 DMLN/RTCC/RP2/CN53/RD8 bidirectional PORTD digital I/O (RD8) with Schmitt Trigger input, D- external pull-down control DMLN and RTCC alarm output.
69 DPLN/RP4/GD10/PMACK2/CN54/RD9 bidirectional PORTD digital I/O (RD9) with Schmitt Trigger input, D+ external pull-down control DPLN and remappable output RP4.
70 RP3/PMA15/PMCS2/CN55/RD10 bidirectional PORTD digital I/O (RD10) with Schmitt Trigger input and remappable output RP3.
71 RP12/PMA14/PMCS1/CN56/RD11 bidirectional PORTD digital I/O (RD11) with Schmitt Trigger input and remappable output RP12.
72 DMH/RP11/INT0/CN49/RD0 bidirectional PORTD digital I/O (RD0) with Schmitt Trigger input, D- external pull-up control DMH, external interrupt INT0 and remappable output RP11.
73 SOSCI/C3IND/CN1/RC13 bidirectional Secondary oscillator/Timer1 clock input, also PORTC digital I/O RC13 and comparator 3 input D.
74 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 bidirectional Secondary oscillator/Timer1 clock output, also PORTC digital I/O RC14, Timer1 clock input T1CK and remappable input RPI37.
75 VSS power_in Ground reference for logic and I/O pins.
76 VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 bidirectional PORTD digital I/O (RD1) with Schmitt Trigger input, USB OTG VBUS PWM/charge output VCPCON and remappable output RP24.
77 DPH/RP23/GD11/PMACK1/CN51/RD2 bidirectional PORTD digital I/O (RD2) with Schmitt Trigger input, D+ external pull-up control DPH and remappable output RP23.
78 RP22/PMBE0/CN52/RD3 bidirectional PORTD digital I/O (RD3) with Schmitt Trigger input and remappable output RP22.
79 RPI42/PMD12/CN57/RD12 bidirectional PORTD digital I/O (RD12) with Schmitt Trigger input and remappable input-only pin RPI42.
80 PMD13/CN19/RD13 bidirectional PORTD digital I/O (RD13) with Schmitt Trigger input and EPMP data bus bit 13.
81 RP25/PMWR/CN13/RD4 bidirectional PORTD digital I/O (RD4) with Schmitt Trigger input, remappable output RP25 and EPMP write strobe PMWR.
82 RP20/PMRD/CN14/RD5 bidirectional PORTD digital I/O (RD5) with Schmitt Trigger input, remappable output RP20 and EPMP read strobe PMRD.
83 C3INB/PMD14/CN15/RD6 bidirectional PORTD digital I/O (RD6) with Schmitt Trigger input, comparator 3 input B and EPMP data bus bit 14.
84 C3INA/SESSEND/PMD15/CN16/RD7 bidirectional PORTD digital I/O (RD7) with Schmitt Trigger input, comparator 3 input A and USB VBUS boost comparator input SESSEND.
85 VCAP passive External filter capacitor connection for the on-chip voltage regulator; requires a low-ESR capacitor of 10 uF to ground when the regulator is enabled.
86 ENVREG input Voltage regulator enable; must be tied directly to VDD to enable the regulator or to ground to disable it.
87 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 bidirectional PORTF digital I/O (RF0) with Schmitt Trigger input, USB VBUS boost comparator input and EPMP data bus bit 11.
88 VCMPST2/SESSVLD/PMD10/CN69/RF1 bidirectional PORTF digital I/O (RF1) with Schmitt Trigger input, USB VBUS boost comparator input 2 and EPMP data bus bit 10.
89 PMD9/CN78/RG1 bidirectional PORTG digital I/O (RG1) with Schmitt Trigger input and EPMP data bus bit 9.
90 PMD8/CN77/RG0 bidirectional PORTG digital I/O (RG0) with Schmitt Trigger input and EPMP data bus bit 8.
91 AN23/GEN/CN39/RA6 bidirectional PORTA digital I/O (RA6) with analog input AN23 and graphics display enable output GEN.
92 AN22/PMA17/CN40/RA7 bidirectional PORTA digital I/O (RA7) with analog input AN22 and EPMP address bit 17.
93 PMD0/CN58/RE0 bidirectional PORTE digital I/O (RE0) with Schmitt Trigger input and EPMP data bus bit 0.
94 PMD1/CN59/RE1 bidirectional PORTE digital I/O (RE1) with Schmitt Trigger input and EPMP data bus bit 1.
95 PMA16/CN81/RG14 bidirectional PORTG digital I/O (RG14) with Schmitt Trigger input and EPMP address bit 16.
96 VSYNC/CN79/RG12 bidirectional PORTG digital I/O (RG12) with Schmitt Trigger input and graphics display vertical sync pulse output VSYNC.
97 HSYNC/CN80/RG13 bidirectional PORTG digital I/O (RG13) with Schmitt Trigger input and graphics display horizontal sync pulse output HSYNC.
98 PMD2/CN60/RE2 bidirectional PORTE digital I/O (RE2) with Schmitt Trigger input and EPMP data bus bit 2.
99 PMD3/CN61/RE3 bidirectional PORTE digital I/O (RE3) with Schmitt Trigger input and EPMP data bus bit 3.
100 PMD4/CN62/RE4 bidirectional PORTE digital I/O (RE4) with Schmitt Trigger input and EPMP data bus bit 4.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-100(12x12)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD VDD 3.6 V Regulator enabled; min is VBOR (Standard Operating Conditions 2.2V to 3.6V) 373
RAM Data Retention Voltage VDR 1.5 V 373
VDD Rise Rate to Ensure Internal Power-on Reset Signal SVDD 0.05 V/ms 0-3.3V in 66 ms; 0-2.5V in 50 ms 373
Brown-out Reset Voltage on VDD Transition, High-to-Low VBOR 2 2.1 2.2 V Regulator enabled 373
Regulator Output Voltage (VCAP) VCAP 1.8 V Regulator enabled 373
Operating Junction Temperature Range TJ -40 125 °C 372
Operating Ambient Temperature Range TA -40 85 °C 372
Package Thermal Resistance, 12x12x1 mm TQFP JA 69.4 °C/W Junction to ambient, package simulation (Note 1) 372
Ambient temperature under bias -40 100 °C 371
Storage temperature -65 150 °C 371
Voltage on VDD with respect to VSS VDD -0.3 4 V 371
Voltage on any digital only pin with respect to VSS when VDD > 3.0V -0.3 5.5 V 371
Voltage on VBUS pin with respect to VSS -0.3 5.5 V Independent of VDD or VUSB 371
Operating Current (IDD) IDD 0.8 1.3 mA -40°C, 3.3V, 1 MIPS 374
Operating Current (IDD) IDD 3 4.8 mA -40°C, 3.3V, 4 MIPS 374
Operating Current (IDD) IDD 12 18 mA -40°C, 3.3V, 16 MIPS 374
Operating Current (IDD) LPRC 31 kHz IDD 55 95 µA -40°C, 3.3V, LPRC (31 kHz) 374
Operating Current (IDD) LPRC 31 kHz IDD 135 225 µA +85°C, 3.3V, LPRC (31 kHz) 374
Base Power-Down Current (IPD) IPD 20 45 µA -40°C, 3.3V 376
Base Power-Down Current (IPD) IPD 55 105 µA +60°C, 3.3V 376
Base Power-Down Current (IPD) IPD 95 185 µA +85°C, 3.3V 376
Power-Down Current with 31 kHz LPRC and RTCC, WDT or Timer1 ILPRC 1 3.5 µA -40°C, 3.3V 376
Power-Down Current with 31 kHz LPRC and RTCC, WDT or Timer1 ILPRC 2.5 6.5 µA +85°C, 3.3V 376
Power-Down Current, 32 kHz crystal with RTCC or Timer1, SOSCSEL<1:0>=11 ISOSC 4 18 µA -40°C, 3.3V 376
Power-Down Current, 32 kHz crystal with RTCC or Timer1, SOSCSEL<1:0>=11 ISOSC 6.5 18 µA +60°C, 3.3V 376
Power-Down Current, 32 kHz crystal with RTCC or Timer1, SOSCSEL<1:0>=11 ISOSC 12 25 µA +85°C, 3.3V 376
Input Low Voltage, I/O pins with I2C Buffer VIL 0.8 V SMBus enabled (DI19) 377
CNxx Pull-up Current ICNPU 150 350 550 µA AVDD = 3.3V, VPIN = VSS 377
CNxx Pull-down Current ICNPD 15 70 150 µA AVDD = 3.3V, VPIN = VDD 377
Input Leakage Current, I/O Ports IIL 1 µA VSS VPIN VDD, pin at high-impedance 377
Input Leakage Current, Analog Input Pins IIL 1 µA VSS VPIN VDD, pin at high-impedance 377
Input Leakage Current, MCLR IIL 1 µA VSS VPIN VDD 377
Input Leakage Current, OSCI/CLKI IIL 1 µA VSS VPIN VDD, EC, XT and HS modes 377
Output Low Voltage, I/O Ports VOL 0.4 V IOL = 6.6 mA, VDD = 3.6V 378
Output Low Voltage, OSCO/CLKO VOL 0.4 V IOL = 6.6 mA, VDD = 3.6V 378
Output High Voltage, I/O Ports VOH 3 V IOH = -3.0 mA, VDD = 3.6V 378
Output High Voltage, I/O Ports VOH 2.4 V IOH = -6.0 mA, VDD = 3.6V 378
Output High Voltage, I/O Ports VOH 1.65 V IOH = -1.0 mA, VDD = 2.2V 378
Output High Voltage, I/O Ports VOH 1.4 V IOH = -3.0 mA, VDD = 2.2V 378
Output High Voltage, OSCO/CLKO VOH 2.4 V IOH = -6.0 mA, VDD = 3.6V 378
Output High Voltage, OSCO/CLKO VOH 1.4 V IOH = -1.0 mA, VDD = 2.2V 378
Program Flash Cell Endurance EP 10000 E/W -40C to +85C 378
Characteristic Retention TRETD 20 Year If no other specifications are violated 378
Self-Timed Page Erase Time TIE 20 40 ms 378
Regulator Output Voltage VRGOUT 1.8 V 379
Internal Band Gap Reference VBG 1.2 V 379
External Filter Capacitor Value CEFC 4.7 10 µF Series resistance < 3 Ohm recommended; < 5 Ohm required. 379
Regulator Wake-up Time TVREG TVREG 10 µs VREGS = 1, VREGS = 0 with WUTSEL<1:0> = 01 or any POR or BOR 379
Sleep Wake-up Time with VREGS=0 and WUTSEL<1:0>=11 TVREG 190 µs 379
Band Gap Reference Start-up Time TBG 1 ms 379
PLL Input Frequency Range FPLLI 4 48 MHz ECPLL mode 381
PLL Output Frequency Range FSYS 95.76 96.24 MHz 381
PLL Start-up Time (Lock Time) TLOCK 200 µs 381
CLKO Stability (Jitter) DCLK -0.25 0.25 % 381
FRC Accuracy @ 8 MHz F20 -1 1 % -40°C TA +85°C 2.2V VDD 3.6V 382
LPRC @ 31 kHz F21 -20 20 % -40°C TA +85°C; VCAP = 1.8V 382
RC Oscillator Start-up Time FRC TFRC 15 µs 382
RC Oscillator Start-up Time LPRC TLPRC 50 µs 382
MCLR Pulse Width (Low) TMCL 2 µs 382
Power-on Reset Delay TPOR 2 µs 382
Brown-out Reset Pulse Width TBOR 1 µs VDD VBOR 382
Internal State Reset Time TRST 50 µs 382

CAD (KiCad official)

  • Symbol: PIC24FJ256DA210-I
  • Footprint: Package_QFP:TQFP-100_12x12mm_P0.4mm
  • 3D model: TQFP-100(12x12) (KiCad packages3D, STEP)
  • 3D model files: pic24fj256da210-i-etched.step / pic24fj256da210-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic24fj256da210-i.step / pic24fj256da210-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (408 pp, sha256 0668570d82cb7b4e, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF