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PIC24FJ128GC010T-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-100(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC24FJ128GC010T-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-100(12x12)

PIC24FJ128GC010T-I from Microchip Tech, in a TQFP-100(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RG15 bidirectional Digital I/O, 5.5V tolerant, shared with AN33 analog input, SEG50 LCD segment output, CTED3 CTMU edge input and CN82 change notification.
2 VDD power_in Positive supply for peripheral digital logic and I/O pins, supply range 2.0V to 3.6V.
3 RE5 bidirectional Digital I/O, VDD-only input tolerance, shared with CTED4 CTMU edge input, PMD5 EPMP data, LCDBIAS2 LCD bias input and CN63.
4 RE6 bidirectional Digital I/O, VDD-only input tolerance, shared with PMD6 EPMP data, LCDBIAS1 LCD bias input and CN64.
5 RE7 bidirectional Digital I/O, VDD-only input tolerance, shared with PMD7 EPMP data, LCDBIAS0 LCD bias input and CN65.
6 RC1 bidirectional Digital I/O, 5.5V tolerant, shared with AN8 analog input, OA1N1 op amp input, SEG32 LCD segment output, RPI38 remappable input and CN45.
7 RC2 bidirectional Digital I/O, 5.5V tolerant, shared with SEG51 LCD segment output, RPI39 remappable input and CN46.
8 RC3 bidirectional Digital I/O, 5.5V tolerant, shared with AN9 analog input, SEG33 LCD segment output, RPI40 remappable input and CN47.
9 RC4 bidirectional Digital I/O, 5.5V tolerant, shared with AN16 analog input, SEG52 LCD segment output, RPI41 remappable input, PMCS2 EPMP chip select and CN48.
10 RG6 bidirectional Digital I/O, VDD-only input tolerance, shared with BGBUF2 band gap buffer output, AN17 analog input, SEG0 LCD segment output, RP21, T5CK, PMA5 and CN8.
11 VLCAP1 passive LCD drive charge pump capacitor pin; the same pin is also RG7 digital I/O (VDD-only input tolerance) with AN18, OA1N4, C1INC, RP26, PMA4 and CN9.
12 VLCAP2 passive LCD drive charge pump capacitor pin; the same pin is also RG8 digital I/O (VDD-only input tolerance) with AN19, OA1N2, C2IND, RP19, PMA3 and CN10.
13 MCLR input Master Clear (device Reset) input with ST buffer; the line is brought low to cause a Reset.
14 RG9 bidirectional Digital I/O, VDD-only input tolerance, shared with AN49 analog input, OA1P0, C2INC, SEG1, DAC1 output, RP27, PMA2 and CN11.
15 VSS power_in Ground reference for logic and I/O pins.
16 VDD power_in Positive supply for peripheral digital logic and I/O pins, supply range 2.0V to 3.6V.
17 RA0 bidirectional Digital I/O, 5.5V tolerant, shared with TMS JTAG input, SEG48 LCD segment output, CTED0 CTMU edge input and CN33.
18 RE8 bidirectional Digital I/O, 5.5V tolerant, shared with SEG34 LCD segment output, RPI33 remappable input, PMCS1 EPMP chip select and CN66.
19 RE9 bidirectional Digital I/O, 5.5V tolerant, shared with AN21 analog input, SEG35 LCD segment output, RPI34, PMA19 and CN67.
20 RB5 bidirectional Digital I/O, VDD-only input tolerance, shared with PGEC3 ICSP clock, AN5 analog input, OA1OUT op amp output, C1INA, SEG2, RP18 and CN7.
21 RB4 bidirectional Digital I/O, 5.5V tolerant, shared with PGED3 ICSP data, AN4 analog input, OA1N0, C1INB, SEG3, RP28, USBOEN and CN6.
22 RB3 bidirectional Digital I/O, VDD-only input tolerance, shared with AN3 analog input, OA2OUT op amp output, C2INA, SEG4, VPIO USB external transceiver I/O and CN5.
23 RB2 bidirectional Digital I/O, 5.5V tolerant, shared with AN2 analog input, OA2N2, CTCMP, C2INB, SEG5, RP13, T4CK, VMIO USB external transceiver I/O, CTED13 and CN4.
24 RB1 bidirectional Digital I/O, VDD-only input tolerance, shared with PGEC1 ICSP clock, CVREF-/AVREF- reference input (alternate location set by configuration bits), AN1, OA2P1, SEG6, RP1, CTED12 and CN3.
25 RB0 bidirectional Digital I/O, VDD-only input tolerance, shared with PGED1 ICSP data, CVREF+/AVREF+/DVREF+ reference input, BGBUF1 band gap buffer output, AN0, SEG7, RP0 and CN2.
26 RB6 bidirectional Digital I/O, VDD-only input tolerance, shared with PGEC2 ICSP clock, AN6 analog input, OA1P3, RP6, LCDBIAS3 and CN24.
27 RB7 bidirectional Digital I/O, 5.5V tolerant, shared with PGED2 ICSP data, AN7 analog input, COM6, SEG30, RP7 and CN25.
28 RA9 bidirectional Digital I/O, VDD-only input tolerance, shared with CVREF-/AVREF- reference input (alternate location set by configuration bits), SEG36, PMA7 and CN41.
29 RA10 bidirectional Digital I/O, VDD-only input tolerance, shared with CVREF+/AVREF+ reference input (alternate location set by configuration bits), SEG37, PMA6 and CN42.
30 AVDD power_in Positive supply for analog modules.
31 AVSS power_in Ground reference for analog modules.
32 SVSS power_in Ground reference for Sigma-Delta A/D converter.
33 CH0+ input Sigma-Delta A/D converter channel 0 non-inverting analog input.
34 CH0- input Sigma-Delta A/D converter channel 0 inverting analog input.
35 CH1+ input Sigma-Delta A/D converter channel 1 non-inverting analog input, also the SVREF+ reference input.
36 CH1- input Sigma-Delta A/D converter channel 1 inverting analog input, also the CH1SE single-ended input and SVREF- reference input.
37 SVDD power_in Positive supply for Sigma-Delta A/D converter.
38 RA1 bidirectional Digital I/O, 5.5V tolerant, shared with TCK JTAG clock input, AN26, SEG31 LCD segment output and CN34.
39 RF13 bidirectional Digital I/O, 5.5V tolerant, shared with AN27 analog input, SEG53 LCD segment output, RP31 and CN76.
40 RF12 bidirectional Digital I/O, 5.5V tolerant, shared with SEG54 LCD segment output, RPI32, CTED7, PMA18 and CN75.
41 RB12 bidirectional Digital I/O, 5.5V tolerant, shared with AN12 analog input, COM5 LCD common output, SEG18, T1CK, CTED2, PMA11 and CN30.
42 RB13 bidirectional Digital I/O, VDD-only input tolerance, shared with AN13 analog input, OA2P3, SEG19, DAC2 output, CTED1, PMA10 and CN31.
43 RB14 bidirectional Digital I/O, 5.5V tolerant, shared with AN14 analog input, OA2N4, SEG8, RP14, CTED5, CTPLS, PMA1 and CN32.
44 RB15 bidirectional Digital I/O, 5.5V tolerant, shared with AN15 analog input, SEG9, RP29, T2CK, REFO output, CTED6, PMA0 and CN12.
45 VSS power_in Ground reference for logic and I/O pins.
46 VDD power_in Positive supply for peripheral digital logic and I/O pins, supply range 2.0V to 3.6V.
47 RD14 bidirectional Digital I/O, 5.5V tolerant, shared with AN28 analog input, SEG38 LCD segment output, RPI43 and CN20.
48 RD15 bidirectional Digital I/O, 5.5V tolerant, shared with AN29 analog input, SEG39 LCD segment output, RP5 and CN21.
49 RF4 bidirectional Digital I/O, 5.5V tolerant, shared with AN11 analog input, OA2N3, SEG10, RP10, SDA2 (alternate location set by I2C2SEL), T3CK, PMA9 and CN17.
50 RF5 bidirectional Digital I/O, 5.5V tolerant, shared with CVREF output, AN10 analog input, OA2P2, SEG11, RP17, SCL2 (alternate location set by I2C2SEL), PMA8 and CN18.
51 RF3 bidirectional Digital I/O, 5.5V tolerant, shared with AN30 analog input, SEG12, RP16, USBID, PMA12 and CN71.
52 RF2 bidirectional Digital I/O, 5.5V tolerant, shared with AN31 analog input, SEG40 LCD segment output, RP30 and CN70.
53 RF8 bidirectional Digital I/O, 5.5V tolerant, shared with AN32 analog input, SEG41 LCD segment output, RP15 and CN74.
54 VBUS power_in USB VBUS connection (5V nominal); the same pin is also RF7 digital I/O and CN83.
55 VUSB3V3 power_in USB transceiver power input voltage (3.3V nominal), which must be connected regardless of whether the USB module is used.
56 D- bidirectional USB differential minus line for the internal transceiver; the same pin is also RG3 digital I/O (VDD-only input tolerance) and CN73.
57 D+ bidirectional USB differential plus line for the internal transceiver; the same pin is also RG2 digital I/O (VDD-only input tolerance) and CN72.
58 RA2 bidirectional Digital I/O, 5.5V tolerant, shared with SEG55 LCD segment output, SCL2 I2C2 clock and CN35.
59 RA3 bidirectional Digital I/O, 5.5V tolerant, shared with SEG56 LCD segment output, SDA2 I2C2 data, PMA20 and CN36.
60 RA4 bidirectional Digital I/O, 5.5V tolerant, shared with TDI JTAG data input, AN36 analog input, SEG29, PMA21 and CN37.
61 RA5 bidirectional Digital I/O, 5.5V tolerant, shared with TDO JTAG data output, AN37 analog input, SEG28 LCD segment output and CN38.
62 VDD power_in Positive supply for peripheral digital logic and I/O pins, supply range 2.0V to 3.6V.
63 RC12 bidirectional Digital I/O, VDD-only input tolerance, shared with OSCI/CLKI main oscillator or clock input and CN23.
64 RC15 bidirectional Digital I/O, VDD-only input tolerance, shared with OSCO/CLKO main oscillator output or system clock output (FOSC/2, selected by OSCIOFCN) and CN22.
65 VSS power_in Ground reference for logic and I/O pins.
66 RA14 bidirectional Digital I/O, 5.5V tolerant, shared with AN38 analog input, SEG42 LCD segment output, RPI36, SCL1 I2C1 clock, OCTRIG2, PMA22 and CN43.
67 RA15 bidirectional Digital I/O, 5.5V tolerant, shared with AN39 analog input, SEG43 LCD segment output, RPI35, SDA1 I2C1 data, PMBE1 and CN44.
68 RD8 bidirectional Digital I/O, 5.5V tolerant, shared with AN40 analog input, SEG13, RP2, RTCC output, DMLN, OCTRIG1, PMA13 and CN53.
69 RD9 bidirectional Digital I/O, 5.5V tolerant, shared with AN24 analog input, SEG14, RP4, DPLN, PMACK2 and CN54.
70 RD10 bidirectional Digital I/O, 5.5V tolerant, shared with AN41 analog input, C3IND, SEG15, RP3, PMA15, CS2 and CN55.
71 RD11 bidirectional Digital I/O, 5.5V tolerant, shared with AN42 analog input, OA2P0, C3INC, SEG16, RP12, PMA14, CS1 and CN56.
72 RD0 bidirectional Digital I/O, 5.5V tolerant, shared with AN43 analog input, OA2N0, SEG17, RP11, VCMPST3, DMH, INT0 and CN49.
73 RC13 input Input-only pin with VDD-only input tolerance, shared with SOSCI secondary oscillator input and cannot be configured as an output.
74 RC14 input Input-only pin with VDD-only input tolerance, shared with SOSCO, PWRLCLK 50/60 Hz RTCC input, SCLKI digital clock input and RPI37; cannot be configured as an output.
75 VSS power_in Ground reference for logic and I/O pins.
76 RD1 bidirectional Digital I/O, 5.5V tolerant, shared with AN35 analog input, SEG20, RP24 and CN50; using it as AN35 raises worst-case device current by 500 uA because there is no ANSx bit for this pin.
77 RD2 bidirectional Digital I/O, 5.5V tolerant, shared with AN25 analog input, OA2N1, SEG21, RP23, DPH, PMACK1 and CN51.
78 RD3 bidirectional Digital I/O, 5.5V tolerant, shared with AN44 analog input, OA2P4, SEG22, RP22, PMBE0 and CN52.
79 RD12 bidirectional Digital I/O, 5.5V tolerant, shared with AN45 analog input, SEG44, RPI42, PMD12 and CN57.
80 RD13 bidirectional Digital I/O, 5.5V tolerant, shared with AN46 analog input, SEG45, PMD13 and CN19.
81 RD4 bidirectional Digital I/O, 5.5V tolerant, shared with AN47 analog input, OA1P4, SEG23, RP25, PMWR and CN13.
82 RD5 bidirectional Digital I/O, 5.5V tolerant, shared with AN48 analog input, OA1N1, SEG24, RP20, PMRD and CN14.
83 RD6 bidirectional Digital I/O, 5.5V tolerant, shared with AN34 analog input, OA1P2, C3INB, SEG25, PMD14 and CN15.
84 RD7 bidirectional Digital I/O, 5.5V tolerant, shared with AN20 analog input, C3INA, SEG26, PMD15 and CN16.
85 VCAP passive External filter capacitor connection for the on-chip voltage regulator; it must not be connected to VDD and must use a 10 uF capacitor to ground.
86 VBAT power_in Backup battery (B+) input for VBAT operation.
87 RF0 bidirectional Digital I/O, 5.5V tolerant, shared with COM7 LCD common output, SEG27, VCMPST1, PMD11 and CN68.
88 RF1 bidirectional Digital I/O, 5.5V tolerant, shared with COM4 LCD common output, SEG47, VCMPST2, PMD10 and CN69.
89 RG1 bidirectional Digital I/O, 5.5V tolerant, shared with SEG46 LCD segment output, PMD9 and CN78.
90 RG0 bidirectional Digital I/O, 5.5V tolerant, shared with SEG49 LCD segment output, PMD8 and CN77.
91 RA6 bidirectional Digital I/O, 5.5V tolerant, shared with AN23 analog input, SEG57 LCD segment output and CN39.
92 RA7 bidirectional Digital I/O, 5.5V tolerant, shared with AN22 analog input, SEG58 LCD segment output, PMA17 and CN40.
93 RE0 bidirectional Digital I/O, 5.5V tolerant, shared with COM3 LCD common output, PMD0 and CN58.
94 RE1 bidirectional Digital I/O, 5.5V tolerant, shared with COM2 LCD common output, PMD1 and CN59.
95 RG14 bidirectional Digital I/O, 5.5V tolerant, shared with SEG59 LCD segment output, CTED11, PMA16 and CN81.
96 RG12 bidirectional Digital I/O, 5.5V tolerant, shared with SEG60 LCD segment output and CN79.
97 RG13 bidirectional Digital I/O, 5.5V tolerant, shared with SEG61 LCD segment output, CTED10 and CN80.
98 RE2 bidirectional Digital I/O, 5.5V tolerant, shared with COM1 LCD common output, PMD2 and CN60.
99 RE3 bidirectional Digital I/O, 5.5V tolerant, shared with COM0 LCD common output, CTED9, PMD3 and CN61.
100 RE4 bidirectional Digital I/O, 5.5V tolerant, shared with HLVDIN high/low-voltage detect input, SEG62 LCD segment output, CTED8, PMD4 and CN62.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-100(12x12)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (Standard Operating Conditions) VDD 2 3.6 V Standard Operating Conditions, unless otherwise stated (DC table header) 439
Operating temperature range, Industrial TA -40 85 °C Industrial grade 439
USB supply voltage VUSB3V3 3 3.3 3.6 V USB module enabled; min printed as greater of 3.0 or (VDD, 0.3V) 439
USB supply voltage, USB disabled, RG2/RG3 unused and externally pulled low or left high-impedance VUSB3V3 3.6 V USB disabled; RG2/RG3 unused and externally pulled low or high-impedance; min printed as (VDD, 0.3V), not numeric 439
USB supply voltage, USB disabled, RG2/RG3 used as general purpose I/O VUSB3V3 3.6 V USB disabled; RG2/RG3 used as general purpose I/O; min printed as (VDD, 0.3V), typ printed as VDD, not numeric 439
Internal FRC oscillator accuracy with run-time self-calibration -0.2 0.2 % Run-time self-calibration capability for maintaining better than ±0.20% accuracy 2
VCAP ceramic capacitor minimum DC rating 16 V Ceramic capacitor on VCAP pin (external component requirement) 36
VCAP capacitor equivalent series resistance ESR 5 Ω Low-ESR capacitor required on VCAP pin (external component requirement) 35

CAD (KiCad official)

  • Symbol: PIC24FJ128GC010T-I
  • Footprint: Package_QFP:TQFP-100_12x12mm_P0.4mm
  • 3D model: TQFP-100(12x12) (KiCad packages3D, STEP)
  • 3D model files: pic24fj128gc010t-i-etched.step / pic24fj128gc010t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic24fj128gc010t-i.step / pic24fj128gc010t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (504 pp, sha256 0feacdfee854238f, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF