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PIC24FJ128GA204-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), QFN-44-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC24FJ128GA204-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-44-EP(8x8)

PIC24FJ128GA204-I from Microchip Tech, in a QFN-44-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RB9 bidirectional PORTB I/O (ST) shared with RP9, SDA1 (I2C1 data), T1CK, CTED4, PMD3, CN21 and comparator inputs C1INC/C2INC/C3INC.
2 RC6 bidirectional PORTC I/O (ST) shared with RP22, PMA1/PMALH and CN18.
3 RC7 bidirectional PORTC I/O (ST) shared with RP23, PMA0/PMALL and CN17.
4 RC8 bidirectional PORTC I/O (ST) shared with RP24, PMA5 and CN20.
5 RC9 bidirectional PORTC I/O (ST) shared with RP25, CTED7, PMA6 and CN19.
6 VBAT power_in Backup battery (B+) input, 1.2V nominal.
7 VCAP passive External filter capacitor connection (VCAP/VDDCORE) for the core regulator; use a low-ESR 10 µF capacitor to ground and do not connect to VDD.
8 RB10 bidirectional PORTB I/O (ST) shared with RP10, CTED11, PMD2, CN16 and PGD2 (ICSP data).
9 RB11 bidirectional PORTB I/O (ST) shared with REFI, RP11, CTED9, PMD1, CN15 and PGC2 (ICSP clock).
10 RB12 bidirectional PORTB I/O (ST) shared with AN8, HLVDIN, RP12, PMD0 and CN14.
11 RB13 bidirectional PORTB I/O (ST) shared with AN7, C1INC, REFO, RP13, CTPLS, PMRD/PMWR and CN13.
12 RA10 bidirectional PORTA I/O (ST) shared with TMS (JTAG mode select), PMA2/PMALU and CN36.
13 RA7 bidirectional PORTA I/O (ST) shared with TCK (JTAG clock), PMA7 and CN33.
14 RB14 bidirectional PORTB I/O (ST) shared with CVREF, AN6, C3INB, RP14, PMWR/PMNEB, RTCC, CTED5 and CN12.
15 RB15 bidirectional PORTB I/O (ST) shared with AN9, C3INA, RP15, T2CK/T3CK, CTED6, PMA14/PMCS/PMCS1 and CN11.
16 AVSS/VSS power_in Ground reference for analog modules; must always be connected.
17 AVDD power_in Positive supply for analog modules; must always be connected.
18 MCLR input Master Clear (device Reset) input, ST buffer; brought low to cause a Reset.
19 RA0 bidirectional PORTA I/O (ST) shared with CVREF+/VREF+, AN0, C3INC, CTED1 and CN2.
20 RA1 bidirectional PORTA I/O (ST) shared with CVREF-/VREF-, AN1, C3IND, CTED2 and CN3.
21 RB0 bidirectional PORTB I/O (ST) shared with AN2, CTCMP, C2INB, RP0, CN4 and PGD1 (ICSP data).
22 RB1 bidirectional PORTB I/O (ST) shared with AN3, C2INA, RP1, CTED12, CN5 and PGC1 (ICSP clock).
23 RB2 bidirectional PORTB I/O (ST) shared with AN4, C1INB, RP2, SDA2, T4CK/T5CK, CTED13 and CN6.
24 RB3 bidirectional PORTB I/O (ST) shared with AN5, C1INA, RP3, SCL2, CTED8 and CN7.
25 RC0 bidirectional PORTC I/O (ST) shared with AN10, RP16, PMBE1 and CN8.
26 RC1 bidirectional PORTC I/O (ST) shared with AN11, RP17, PMCS2 and CN9.
27 RC2 bidirectional PORTC I/O (ST) shared with AN12, RP18, PMACK1 and CN10.
28 VDD power_in Positive supply for peripheral digital logic and I/O pins.
29 VSS power_in Ground reference for logic and I/O pins.
30 RA2 bidirectional PORTA I/O (ST) shared with OSCI/CLKI main oscillator input, C1IND, PMCS1 and CN30.
31 RA3 bidirectional PORTA I/O (ST) shared with OSCO/CLKO main oscillator output, C2IND and CN29.
32 RA8 bidirectional PORTA I/O (ST) shared with TDO (JTAG data out), PMA8 and CN34.
33 RB4 input PORTB input (ST) shared with SOSCI secondary oscillator input, RPI4 and CN1.
34 RA4 input PORTA input (ST) shared with SOSCO secondary oscillator output, SCLKI and CN0.
35 RA9 bidirectional PORTA I/O (ST) shared with TDI (JTAG data in), PMA9 and CN35.
36 RC3 bidirectional PORTC I/O (ST) shared with RP19, PMBE0 and CN28.
37 RC4 bidirectional PORTC I/O (ST) shared with RP20, PMA4 and CN25.
38 RC5 bidirectional PORTC I/O (ST) shared with RP21, PMA3 and CN26.
39 VSS power_in Ground reference for logic and I/O pins.
40 VDD power_in Positive supply for peripheral digital logic and I/O pins.
41 RB5 bidirectional PORTB I/O (ST) shared with PGD3 (ICSP data), RP5, ASDA1, PMD7 and CN27.
42 RB6 bidirectional PORTB I/O (ST) shared with PGC3 (ICSP clock), RP6, ASCL1, PMD6 and CN24.
43 RB7 bidirectional PORTB I/O (ST) shared with RP7, CTED3, INT0, PMD5 and CN23.
44 RB8 bidirectional PORTB I/O (ST) shared with RP8, SCL1 (I2C1 clock), CTED10, PMD4 and CN22.
45 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-44-EP(8x8)
Category Single Chip Microcomputer/Microcontroller
Pins 45

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage on VDD with respect to VSS VDD -0.3 4 V 375
Voltage on 5.5V tolerant pin incl. MCLR wrt VSS -0.3 4 V When VDD = 0V 375
Voltage on 5.5V tolerant pin incl. MCLR wrt VSS -0.3 6 V When VDD >= 2.0V 375
Voltage on VBAT with respect to VSS VBAT -0.3 4 V 375
Voltage on AVSS with respect to VSS AVSS -0.3 0.3 V 375
Ambient temperature under bias -40 100 °C 375
Storage temperature -65 150 °C 375
Maximum current out of VSS pin 300 mA 375
Operating Junction Temperature Range TJ -40 125 °C 376
Operating Ambient Temperature Range TA -40 85 °C 376
Package Thermal Resistance, 8x8 mm 44-Pin QFN θJA 28 °C/W Note 1 376
Supply Voltage VDD 2 3.6 V BOR disabled 377
Supply Voltage VDD 3.6 V BOR enabled (min is VBOR) 377
VDD Power-on Reset Release Voltage VPORREL 1.8 1.88 1.95 V (Note 3) 377
Recommended VDD Rise Rate SRVDD 0.05 V/ms 0-3.3V in 66 ms, 0-2.5V in 50 ms (Note 2) 377
Brown-out Reset Voltage on VDD Transition, High-to-Low VBOR 2 2.1 2.2 V (Note 3) 377
Operating Current IDD 5.7 7.6 mA 16 MIPS, FOSC = 32 MHz, 3.3V, -40°C to +125°C 378
Operating Current IDD 1.5 2 mA 4 MIPS, FOSC = 8 MHz, 3.3V, -40°C to +125°C 378
Operating Current IDD 0.21 0.28 mA 0.5 MIPS, FOSC = 1 MHz, 3.3V, -40°C to +125°C 378
Operating Current LPRC IDD 25 80 µA LPRC (15.5 KIPS), FOSC = 31 kHz, 3.3V, -40°C to +85°C 378
Idle Current IIDLE 1.6 2 mA 16 MIPS, FOSC = 32 MHz, 3.3V, -40°C to +85°C 379
Idle Current IIDLE 123 160 µA 1 MIPS, FOSC = 2 MHz, 3.3V, -40°C to +85°C 379
Power-Down Current Sleep IPD 4.3 18 µA Sleep, 3.3V, +25°C 380
Power-Down Current Sleep IPD 20.5 28 µA Sleep, 3.3V, +85°C 380
Power-Down Current Deep Sleep IPD 1.5 6 µA Deep Sleep, 3.3V, +85°C 380
Power-Down Current Deep Sleep IPD 75 900 nA Deep Sleep, 3.3V, +25°C 380
RTCC with VBAT mode IPD 0.4 2 µA 0V, -40°C to +125°C, RTCC with VBAT mode (LPRC/SOSC) 380
Incremental Current BOR 4.3 6 µA 3.3V, -40°C to +125°C 381
Incremental Current WDT 0.8 1.5 µA 3.3V, -40°C to +125°C 381
Incremental Current HLVD 4.2 15 µA 3.3V, -40°C to +125°C 381
Input Low Voltage ST Buffer VIL 0 0.2 V I/O pins with ST buffer; max is 0.2 VDD, min VSS 382
Input Low Voltage TTL Buffer VIL 0 0.15 V max is 0.15 VDD, min VSS 382
Input High Voltage ST Buffer, digital only VIH 0.8 5.5 V min is 0.8 VDD 382
CNxx Pull-up Current ICNPU 150 340 550 µA VDD = 3.3V, VPIN = VSS 382
CNxx Pull-Down Current ICNPD 150 310 550 µA VDD = 3.3V, VPIN = VDD 382
Input Leakage Current I/O Ports IIL -1 1 µA VSS <= VPIN <= VDD, pin at high-impedance 382
Output Low Voltage I/O Ports VOL 0.4 V IOL = 6.6 mA, VDD = 3.6V 383
Output High Voltage I/O Ports VOH 2.4 V IOH = -6.0 mA, VDD = 3.6V 383
Flash Cell Endurance EP 20000 E/W -40C to +125C 383
Flash Characteristic Retention TRETD 20 Year If no other specifications are violated 383
Voltage Regulator Output VRGOUT 1.8 V VDD > 1.9V 384
External Filter Capacitor Value CEFC 4.7 10 µF Series resistance < 3 Ω recommended; < 5 Ω required 384
HLVD Voltage on VDD Transition VHLVD 3.45 3.59 3.74 V HLVDL<3:0> = 0100 384
HLVD Voltage on VDD Transition VHLVD 2 2.08 2.17 V HLVDL<3:0> = 1110 384
Comparator Input Offset Voltage VIOFF 20 40 mV (Note 1) 385
Comparator Input Common-Mode Voltage VICM 0 3.6 V max printed as VDD (Note 1) 385
Comparator CMRR CMRR 55 dB (Note 1) 385
Comparator Mode Change to Valid Output TMC2OV 10 µs 385
CVREF Absolute Accuracy CVRAA -100 100 mV 385
CVREF Settling Time TSET 10 µs (Note 1) 385
Fault Input to PWM I/O Change TFD 50 ns 399
Fault Input Pulse Width TFLT 50 ns 399

CAD (KiCad official)

  • Symbol: PIC24FJ128GA204-I
  • Footprint: Package_DFN_QFN:QFN-44-1EP_8x8mm_P0.65mm_EP6.45x6.45mm
  • 3D model: QFN-44-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: pic24fj128ga204-i-etched.step / pic24fj128ga204-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic24fj128ga204-i.step / pic24fj128ga204-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (438 pp, sha256 2aa1b00881370cec, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF