component
PIC24FJ128GA106T-I
Public Made by Adomby adom
Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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PCB Footprint
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README
markdownPIC24FJ128GA106T-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)
PIC24FJ128GA106T-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RE5/PMD5/RP-none/CN63 | bidirectional | PORTE digital I/O RE5 (Schmitt Trigger) shared with Parallel Master Port data bit 5 (PMD5) and interrupt-on-change input CN63. |
| 2 | RE6/PMD6/SCL3/CN64 | bidirectional | PORTE digital I/O RE6 shared with PMP data bit 6 (PMD6), I2C3 clock SCL3 and interrupt-on-change input CN64. |
| 3 | RE7/PMD7/SDA3/CN65 | bidirectional | PORTE digital I/O RE7 shared with PMP data bit 7 (PMD7), I2C3 data SDA3 and interrupt-on-change input CN65. |
| 4 | RG6/PMA5/RP21/C1IND/CN8 | bidirectional | PORTG digital I/O RG6 shared with PMP address bit 5, remappable pin RP21, Comparator 1 input D and interrupt-on-change CN8. |
| 5 | RG7/PMA4/RP26/C1INC/CN9 | bidirectional | PORTG digital I/O RG7 shared with PMP address bit 4, remappable pin RP26, Comparator 1 input C and interrupt-on-change CN9. |
| 6 | RG8/PMA3/RP19/C2IND/CN10 | bidirectional | PORTG digital I/O RG8 shared with PMP address bit 3, remappable pin RP19, Comparator 2 input D and interrupt-on-change CN10. |
| 7 | MCLR | input | Master Clear (device Reset) input, Schmitt Trigger; brought low to cause a Reset. |
| 8 | RG9/PMA2/RP27/C2INC/CN11 | bidirectional | PORTG digital I/O RG9 shared with PMP address bit 2, remappable pin RP27, Comparator 2 input C and interrupt-on-change CN11. |
| 9 | VSS | power_in | Ground reference for logic and I/O pins. |
| 10 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins. |
| 11 | PGEC3/AN5/C1INA/RP18/CN7/RB5 | bidirectional | PORTB I/O RB5 shared with A/D analog input AN5, Comparator 1 input A, remappable pin RP18, ICSP/debug clock PGEC3 and interrupt-on-change CN7. |
| 12 | PGED3/AN4/C1INB/RP28/CN6/RB4 | bidirectional | PORTB I/O RB4 shared with A/D analog input AN4, Comparator 1 input B, remappable pin RP28, ICSP/debug data PGED3 and interrupt-on-change CN6. |
| 13 | AN3/C2INA/CN5/RB3 | bidirectional | PORTB I/O RB3 shared with A/D analog input AN3, Comparator 2 input A and interrupt-on-change CN5. |
| 14 | AN2/C2INB/RP13/CN4/RB2 | bidirectional | PORTB I/O RB2 shared with A/D analog input AN2, Comparator 2 input B, remappable pin RP13 and interrupt-on-change CN4. |
| 15 | PGEC1/AN1/VREF-/RP1/CN3/RB1 | bidirectional | PORTB I/O RB1 shared with A/D analog input AN1, A/D and comparator low reference VREF-, ICSP/debug clock PGEC1, remappable pin RP1 and CN3. |
| 16 | RB0/AN0/VREF+/PGED1/RP0/PMA6/CN2 | bidirectional | PORTB I/O RB0 shared with A/D analog input AN0, A/D and comparator high reference VREF+, ICSP/debug data PGED1, remappable pin RP0, PMP address bit 6 and CN2. |
| 17 | PGEC2/AN6/RP6/CN24/RB6 | bidirectional | PORTB I/O RB6 shared with A/D analog input AN6, remappable pin RP6, ICSP/debug clock PGEC2 and interrupt-on-change CN24. |
| 18 | PGED2/AN7/RP7/CN25/RB7 | bidirectional | PORTB I/O RB7 shared with A/D analog input AN7, remappable pin RP7, ICSP/debug data PGED2 and interrupt-on-change CN25. |
| 19 | AVDD | power_in | Positive supply for analog modules; must always be connected, even if analog features are unused. |
| 20 | AVSS | power_in | Ground reference for analog modules; must always be connected, even if analog features are unused. |
| 21 | AN8/RP8/CN26/RB8 | bidirectional | PORTB I/O RB8 shared with A/D analog input AN8, remappable pin RP8 and interrupt-on-change CN26. |
| 22 | RB9/AN9/RP9/PMA7/CN27 | bidirectional | PORTB I/O RB9 shared with A/D analog input AN9, remappable pin RP9, PMP address bit 7 and interrupt-on-change CN27. |
| 23 | RB10/AN10/CVREF/PMA13/TMS/CN28 | bidirectional | PORTB I/O RB10 shared with A/D analog input AN10, comparator voltage reference output CVREF, PMP address bit 13, JTAG test mode select TMS and CN28. |
| 24 | RB11/AN11/PMA12/TDO/CN29 | bidirectional | PORTB I/O RB11 shared with A/D analog input AN11, PMP address bit 12, JTAG test data output TDO and interrupt-on-change CN29. |
| 25 | VSS | power_in | Ground reference for logic and I/O pins. |
| 26 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins. |
| 27 | RB12/AN12/CTED2/PMA11/TCK/CN30 | bidirectional | PORTB I/O RB12 shared with A/D analog input AN12, CTMU external edge input 2, PMP address bit 11, JTAG test clock TCK and CN30. |
| 28 | RB13/AN13/CTED1/PMA10/TDI/CN31 | bidirectional | PORTB I/O RB13 shared with A/D analog input AN13, CTMU external edge input 1, PMP address bit 10, JTAG test data input TDI and CN31. |
| 29 | RB14/AN14/CTPLS/PMA1/RP14/CN32 | bidirectional | PORTB I/O RB14 shared with A/D analog input AN14, CTMU pulse output CTPLS, PMP address bit 1, remappable pin RP14 and CN32. |
| 30 | RB15/AN15/REFO/RP29/PMA0/CN12 | bidirectional | PORTB I/O RB15 shared with A/D analog input AN15, reference clock output REFO, remappable pin RP29, PMP address bit 0 and CN12. |
| 31 | RF4/SDA2/PMA9/RP10/CN17 | bidirectional | PORTF I/O RF4 shared with I2C2 data SDA2, PMP address bit 9, remappable pin RP10 and interrupt-on-change CN17. |
| 32 | RF5/SCL2/PMA8/RP17/CN18 | bidirectional | PORTF I/O RF5 shared with I2C2 clock SCL2, PMP address bit 8, remappable pin RP17 and interrupt-on-change CN18. |
| 33 | RP16/CN71/RF3 | bidirectional | PORTF I/O RF3 shared with remappable pin RP16 and interrupt-on-change CN71. |
| 34 | RP30/CN70/RF2 | bidirectional | PORTF I/O RF2 shared with remappable pin RP30 and interrupt-on-change CN70. |
| 35 | RF6/INT0/RPI45/CN72 | bidirectional | PORTF I/O RF6 shared with external interrupt input INT0, remappable input-only pin RPI45 and interrupt-on-change CN72. |
| 36 | SDA1/CN84/RG3 | bidirectional | PORTG I/O RG3 shared with I2C1 data SDA1 and interrupt-on-change CN84. |
| 37 | SCL1/CN83/RG2 | bidirectional | PORTG I/O RG2 shared with I2C1 clock SCL1 and interrupt-on-change CN83. |
| 38 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins. |
| 39 | OSCI/CLKI/CN23/RC12 | bidirectional | PORTC I/O RC12 shared with main oscillator input OSCI, main clock input CLKI and interrupt-on-change CN23. |
| 40 | OSCO/CLKO/CN22/RC15 | bidirectional | PORTC I/O RC15 shared with main oscillator output OSCO, system clock output CLKO and interrupt-on-change CN22. |
| 41 | VSS | power_in | Ground reference for logic and I/O pins. |
| 42 | RTCC/RP2/CN53/RD8 | bidirectional | PORTD I/O RD8 shared with remappable pin RP2, RTCC alarm/seconds pulse output and interrupt-on-change CN53. |
| 43 | RP4/CN54/RD9 | bidirectional | PORTD I/O RD9 shared with remappable pin RP4 and interrupt-on-change CN54. |
| 44 | RD10/RP3/PMCS2/CN55 | bidirectional | PORTD I/O RD10 shared with remappable pin RP3, PMP Chip Select 2 strobe/address bit 14 and interrupt-on-change CN55. |
| 45 | RD11/RP12/PMCS1/CN56 | bidirectional | PORTD I/O RD11 shared with remappable pin RP12, PMP Chip Select 1 strobe/address bit 15 and interrupt-on-change CN56. |
| 46 | RP11/CN49/RD0 | bidirectional | PORTD I/O RD0 shared with remappable pin RP11 and interrupt-on-change CN49. |
| 47 | SOSCI/C3IND/CN1/RC13 | bidirectional | PORTC I/O RC13 shared with secondary oscillator/Timer1 clock input SOSCI, Comparator 3 input D and interrupt-on-change CN1. |
| 48 | RC14/SOSCO/T1CK/C3INC/RPI37/CN0 | bidirectional | PORTC I/O RC14 shared with secondary oscillator output SOSCO, Timer1 clock T1CK, Comparator 3 input C, remappable input RPI37 and CN0. |
| 49 | RP24/CN50/RD1 | bidirectional | PORTD I/O RD1 shared with remappable pin RP24 and interrupt-on-change CN50. |
| 50 | RP23/CN51/RD2 | bidirectional | PORTD I/O RD2 shared with remappable pin RP23 and interrupt-on-change CN51. |
| 51 | RD3/RP22/PMBE/CN52 | bidirectional | PORTD I/O RD3 shared with remappable pin RP22, PMP byte enable strobe and interrupt-on-change CN52. |
| 52 | RD4/RP25/PMWR/CN13 | bidirectional | PORTD I/O RD4 shared with remappable pin RP25, PMP write strobe and interrupt-on-change CN13. |
| 53 | RD5/RP20/PMRD/CN14 | bidirectional | PORTD I/O RD5 shared with remappable pin RP20, PMP read strobe and interrupt-on-change CN14. |
| 54 | C3INB/CN15/RD6 | bidirectional | PORTD I/O RD6 shared with Comparator 3 input B and interrupt-on-change CN15. |
| 55 | C3INA/CN16/RD7 | bidirectional | PORTD I/O RD7 shared with Comparator 3 input A and interrupt-on-change CN16. |
| 56 | VCAP/VDDCORE | power_in | External filter capacitor connection when the regulator is enabled (10 µF, low ESR, not tied to VDD) or core logic supply input when the regulator is disabled. |
| 57 | ENVREG | input | Voltage regulator enable input, Schmitt Trigger; tie to VDD to enable the regulator or to ground to disable it. |
| 58 | CN68/RF0 | bidirectional | PORTF I/O RF0 shared with interrupt-on-change input CN68. |
| 59 | CN69/RF1 | bidirectional | PORTF I/O RF1 shared with interrupt-on-change input CN69. |
| 60 | RE0/PMD0/CN58 | bidirectional | PORTE I/O RE0 shared with PMP data bit 0 (PMD0) and interrupt-on-change CN58. |
| 61 | RE1/PMD1/CN59 | bidirectional | PORTE I/O RE1 shared with PMP data bit 1 (PMD1) and interrupt-on-change CN59. |
| 62 | RE2/PMD2/CN60 | bidirectional | PORTE I/O RE2 shared with PMP data bit 2 (PMD2) and interrupt-on-change CN60. |
| 63 | RE3/PMD3/CN61 | bidirectional | PORTE I/O RE3 shared with PMP data bit 3 (PMD3) and interrupt-on-change CN61. |
| 64 | RE4/PMD4/CN62 | bidirectional | PORTE I/O RE4 shared with PMP data bit 4 (PMD4) and interrupt-on-change CN62. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (regulator enabled) | VDD | 3.6 | V | Regulator enabled; min is VBOR | 271 | ||
| Supply Voltage VDDCORE (regulator disabled) | VDDCORE | 2 | 2.75 | V | Regulator disabled | 271 | |
| RAM Data Retention Voltage | VDR | 1.5 | V | 271 | |||
| VDD Rise Rate for POR | SVDD | 0.05 | V/ms | 0-3.3V in 0.1s; 0-2.5V in 60 ms | 271 | ||
| Brown-Out Reset Voltage | VBOR | 1.9 | 2.1 | 2.25 | V | 271 | |
| Operating Current | IDD | 18.2 | 24 | mA | 16 MIPS, 3.3V, +25°C, regulator enabled | 273 | |
| Operating Current | IDD | 0.83 | 1.2 | mA | 1 MIPS, 2.0V, +25°C, regulator disabled | 273 | |
| Power-Down Current | IPD | 4 | 10 | µA | 3.3V, +25°C, base power-down current | 276 | |
| Power-Down Current | IPD | 0.15 | 1 | µA | 2.0V, +25°C, base power-down current | 276 | |
| Input Low Voltage ST buffer | VIL | 0 | 0.2 | V | Max is 0.2 VDD; min VSS | 278 | |
| Input High Voltage ST buffer, digital only | VIH | 0.8 | 5.5 | V | Min is 0.8 VDD | 278 | |
| CNx Pull-up Current | ICNPU | 50 | 250 | 400 | µA | VDD = 3.3V, VPIN = 0 | 278 |
| Input Leakage Current I/O Ports | IIL | 1 | µA | VSS ≤ VPIN ≤ VDD, pin at high-impedance, -40°C ≤ TA ≤ +85°C | 279 | ||
| Output Low Voltage I/O Ports | VOL | 0.4 | V | IOL = 8.5 mA, VDD = 3.6V | 281 | ||
| Output High Voltage I/O Ports | VOH | 3 | V | IOH = -3.0 mA, VDD = 3.6V | 281 | ||
| Flash Cell Endurance | EP | 10000 | E/W | -40C to +85C | 281 | ||
| Characteristic Retention | TRETD | 20 | Year | Provided no other specifications are violated | 281 | ||
| Internal Band Gap Reference | VBG | 1.14 | 1.2 | 1.26 | V | 282 | |
| External Filter Capacitor Value | CEFC | 4.7 | 10 | µF | Series resistance < 3 Ohm recommended; < 5 Ohm required | 282 | |
| Regulator Output Voltage | VRGOUT | 2.5 | V | 282 | |||
| FRC Accuracy @ 8 MHz | -5 | 5 | % | -40°C ≤ TA ≤ +85°C, 3.0V ≤ VDD ≤ 3.6V | 285 | ||
| LPRC Accuracy @ 31 kHz | -20 | 20 | % | -40°C ≤ TA ≤ +85°C, 3.0V ≤ VDD ≤ 3.6V | 285 | ||
| A/D Integral Nonlinearity | INL | 1 | 2 | LSb | VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V; printed ±1 typ, < ±2 max | 287 | |
| A/D Gain Error | GERR | 1 | 3 | LSb | VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V; printed ± | 287 | |
| Watchdog Timer Time-out Period | TWDT | 0.85 | 1 | 1.15 | ms | 1:32 prescaler | 289 |
| Operating Junction Temperature Range | TJ | -40 | 140 | °C | 270 | ||
| Operating Ambient Temperature Range | TA | -40 | 125 | °C | Family; Industrial -40 to +85 | 270 | |
| Ambient temperature under bias | -40 | 135 | °C | 269 | |||
| Storage temperature | -65 | 150 | °C | 269 | |||
| Voltage on VDD with respect to VSS | VDD | -0.3 | 4 | V | 269 | ||
| Voltage on any combined analog and digital pin, and MCLR | -0.3 | V | Max is VDD + 0.3V | 269 | |||
| Voltage on any digital only pin | -0.3 | 6 | V | 269 | |||
| Voltage on VDDCORE with respect to VSS | VDDCORE | -0.3 | 3 | V | 269 | ||
| Package Thermal Resistance, 10x10x1 mm TQFP | θJA | 76.6 | °C/W | Note 1: package simulations | 270 |
CAD (KiCad official)
- Symbol:
PIC24FJ128GA106T-I - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
pic24fj128ga106t-i-etched.step/pic24fj128ga106t-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic24fj128ga106t-i.step/pic24fj128ga106t-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (332 pp, sha256
a3c9f7848654cb8b, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).