component
PIC24FJ1024GB610-I
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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-100(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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Datasheet
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README
markdownPIC24FJ1024GB610-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-100(12x12)
PIC24FJ1024GB610-I from Microchip Tech, in a TQFP-100(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OCM1C/CTED3/RG15 | bidirectional | Shared I/O RG15 with MCCP1 output OCM1C and CTMU external edge input CTED3; Schmitt Trigger input, 5.5V tolerant per Table 11-2. |
| 2 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins (device supply range 2.0V to 3.6V). |
| 3 | IC4/CTED4/PMD5/RE5 | bidirectional | Shared I/O RE5 with input capture IC4, CTMU external edge input CTED4 and parallel master port data PMD5; Schmitt Trigger input, 5.5V tolerant. |
| 4 | SCL3/IC5/PMD6/RE6 | bidirectional | Shared I/O RE6 with I2C3 clock SCL3, input capture IC5 and parallel master port data PMD6; Schmitt Trigger input, 5.5V tolerant. |
| 5 | SDA3/IC6/PMD7/RE7 | bidirectional | Shared I/O RE7 with I2C3 data SDA3, input capture IC6 and parallel master port data PMD7; Schmitt Trigger input, 5.5V tolerant. |
| 6 | RPI38/OCM1D/RC1 | bidirectional | Shared I/O RC1 with input-only remappable peripheral RPI38 and MCCP1 output OCM1D; Schmitt Trigger input, 5.5V tolerant. |
| 7 | RPI39/OCM2C/RC2 | bidirectional | Shared I/O RC2 with input-only remappable peripheral RPI39 and MCCP2 output OCM2C; Schmitt Trigger input, 5.5V tolerant. |
| 8 | RPI40/OCM2D/RC3 | bidirectional | Shared I/O RC3 with input-only remappable peripheral RPI40 and MCCP2 output OCM2D; Schmitt Trigger input, 5.5V tolerant. |
| 9 | AN16/RPI41/OCM3C/PMCS2/RC4 | bidirectional | Analog input AN16 shared with I/O RC4, input-only remappable RPI41, MCCP3 output OCM3C and parallel chip select PMCS2; RC4 is 5.5V tolerant. |
| 10 | AN17/C1IND/RP21/ICM1/OCM1A/PMA5/RG6 | bidirectional | Analog input AN17 and comparator 1 input C1IND shared with I/O RG6, remappable RP21, MCCP1 input ICM1/output OCM1A and parallel address PMA5; input tolerance limited to VDD. |
| 11 | AN18/C1INC/RP26/OCM1B/PMA4/RG7 | bidirectional | Analog input AN18 and comparator 1 input C1INC shared with I/O RG7, remappable RP26, MCCP1 output OCM1B and parallel address PMA4; input tolerance limited to VDD. |
| 12 | AN19/C2IND/RP19/ICM2/OCM2A/PMA3/RG8 | bidirectional | Analog input AN19 and comparator 2 input C2IND shared with I/O RG8, remappable RP19, MCCP2 input ICM2/output OCM2A and parallel address PMA3; input tolerance limited to VDD. |
| 13 | MCLR | input | Master Clear input; driving this line low causes a device Reset. |
| 14 | AN20/C1INC/C2INC/C3INC/RP27/OCM2B/PMA2/PMALU/RG9 | bidirectional | Analog input AN20 and comparator 1/2/3 C-inputs shared with I/O RG9, remappable RP27, MCCP2 output OCM2B and parallel address PMA2/PMALU; input tolerance limited to VDD. |
| 15 | VSS | power_in | Ground reference for peripheral digital logic and I/O pins. |
| 16 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins (device supply range 2.0V to 3.6V). |
| 17 | TMS/OCM3D/RA0 | bidirectional | JTAG test mode select input TMS shared with I/O RA0 and MCCP3 output OCM3D; Schmitt Trigger input, 5.5V tolerant. |
| 18 | RPI33/PMCS1/RE8 | bidirectional | Shared I/O RE8 with input-only remappable peripheral RPI33 and parallel master chip select PMCS1; Schmitt Trigger input, 5.5V tolerant. |
| 19 | AN21/RPI34/PMA19/RE9 | bidirectional | Analog input AN21 shared with I/O RE9, input-only remappable RPI34 and parallel address PMA19; input tolerance limited to VDD. |
| 20 | PGEC3/AN5/C1INA/RP18/ICM3/OCM3A/RB5 | bidirectional | ICSP programming clock PGEC3 shared with analog input AN5, comparator 1 input C1INA, remappable RP18, MCCP3 input ICM3/output OCM3A and I/O RB5; input tolerance limited to VDD. |
| 21 | PGED3/AN4/C1INB/RP28/USBOEN/OCM3B/RB4 | bidirectional | ICSP programming data PGED3 shared with analog input AN4, comparator 1 input C1INB, remappable RP28, USB output enable USBOEN (GB devices), MCCP3 output OCM3B and I/O RB4; input tolerance limited to VDD. |
| 22 | AN3/C2INA/RB3 | bidirectional | Analog input AN3 and comparator 2 input C2INA shared with I/O RB3; input tolerance limited to VDD. |
| 23 | AN2/CTCMP/C2INB/RP13/CTED13/RB2 | bidirectional | Analog input AN2 shared with CTMU comparator output CTCMP, comparator 2 input C2INB, remappable RP13, CTMU edge input CTED13 and I/O RB2; input tolerance limited to VDD. |
| 24 | PGEC1/ALTCVREF-/ALTVREF-/AN1/RP1/CTED12/RB1 | bidirectional | ICSP programming clock PGEC1 shared with alternate low reference input ALTCVREF-/ALTVREF-, analog input AN1, remappable RP1, CTMU edge input CTED12 and I/O RB1; input tolerance limited to VDD. |
| 25 | PGED1/ALTCVREF+/ALTVREF+/AN0/RP0/RB0 | bidirectional | ICSP programming data PGED1 shared with alternate high reference input ALTCVREF+/ALTVREF+, analog input AN0, remappable RP0 and I/O RB0; input tolerance limited to VDD. |
| 26 | PGEC2/AN6/RP6/RB6 | bidirectional | ICSP programming clock PGEC2 shared with analog input AN6, remappable RP6 and I/O RB6; input tolerance limited to VDD. |
| 27 | PGED2/AN7/RP7/U6TX/RB7 | bidirectional | ICSP programming data PGED2 shared with analog input AN7, remappable RP7, UART6 transmit U6TX and I/O RB7; input tolerance limited to VDD. |
| 28 | CVREF-/VREF-/PMA7/RA9 | bidirectional | Comparator and A/D low reference input CVREF-/VREF- shared with parallel address PMA7 and I/O RA9; input tolerance limited to VDD. |
| 29 | CVREF+/VREF+/PMA6/RA10 | bidirectional | Comparator and A/D high reference input CVREF+/VREF+ shared with parallel address PMA6 and I/O RA10; input tolerance limited to VDD. |
| 30 | AVDD | power_in | Positive supply for analog modules; must always be connected, whether or not the analog features are used. |
| 31 | AVSS | power_in | Ground reference for analog modules; must always be connected, whether or not the analog features are used. |
| 32 | AN8/RP8/PWRGT/RB8 | bidirectional | Analog input AN8 shared with remappable RP8, RTCC power control output PWRGT and I/O RB8; input tolerance limited to VDD. |
| 33 | AN9/TMPR/RP9/T1CK/RB9 | bidirectional | Analog input AN9 shared with tamper detect input TMPR, remappable RP9, Timer1 clock T1CK and I/O RB9; input tolerance limited to VDD. |
| 34 | CVREF/AN10/PMA13/RB10 | bidirectional | Comparator voltage reference output CVREF shared with analog input AN10, parallel address PMA13 and I/O RB10; input tolerance limited to VDD. |
| 35 | AN11/REFI/PMA12/RB11 | bidirectional | Analog input AN11 shared with reference clock input REFI, parallel address PMA12 and I/O RB11; input tolerance limited to VDD. |
| 36 | VSS | power_in | Ground reference for peripheral digital logic and I/O pins. |
| 37 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins (device supply range 2.0V to 3.6V). |
| 38 | TCK/RA1 | bidirectional | JTAG test clock/programming clock input TCK shared with I/O RA1; Schmitt Trigger input, 5.5V tolerant. |
| 39 | RP31/RF13 | bidirectional | Shared I/O RF13 with remappable peripheral RP31; Schmitt Trigger input, 5.5V tolerant. |
| 40 | RPI32/CTED7/PMA18/RF12 | bidirectional | Shared I/O RF12 with input-only remappable peripheral RPI32, CTMU edge input CTED7 and parallel address PMA18; Schmitt Trigger input, 5.5V tolerant. |
| 41 | AN12/U6RX/CTED2/PMA11/RB12 | bidirectional | Analog input AN12 shared with UART6 receive U6RX, CTMU edge input CTED2, parallel address PMA11 and I/O RB12; input tolerance limited to VDD. |
| 42 | AN13/CTED1/PMA10/RB13 | bidirectional | Analog input AN13 shared with CTMU edge input CTED1, parallel address PMA10 and I/O RB13; input tolerance limited to VDD. |
| 43 | AN14/RP14/CTED5/CTPLS/PMA1/PMALH/RB14 | bidirectional | Analog input AN14 shared with remappable RP14, CTMU edge input CTED5, CTMU pulse output CTPLS, parallel address PMA1/PMALH and I/O RB14; input tolerance limited to VDD. |
| 44 | AN15/RP29/CTED6/PMA0/PMALL/RB15 | bidirectional | Analog input AN15 shared with remappable RP29, CTMU edge input CTED6, parallel address PMA0/PMALL and I/O RB15; input tolerance limited to VDD. |
| 45 | VSS | power_in | Ground reference for peripheral digital logic and I/O pins. |
| 46 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins (device supply range 2.0V to 3.6V). |
| 47 | RPI43/RD14 | bidirectional | Shared I/O RD14 with input-only remappable peripheral RPI43; Schmitt Trigger input, 5.5V tolerant. |
| 48 | RP5/RD15 | bidirectional | Shared I/O RD15 with remappable peripheral RP5; Schmitt Trigger input, 5.5V tolerant. |
| 49 | RP10/PMA9/RF4 | bidirectional | Shared I/O RF4 with remappable peripheral RP10 and parallel address PMA9; Schmitt Trigger input, 5.5V tolerant. |
| 50 | RP17/PMA8/RF5 | bidirectional | Shared I/O RF5 with remappable peripheral RP17 and parallel address PMA8; Schmitt Trigger input, 5.5V tolerant. |
| 51 | RP16/USBID/RF3 | bidirectional | Shared I/O RF3 with remappable peripheral RP16 and USB OTG ID input USBID; Schmitt Trigger input, 5.5V tolerant. |
| 52 | RP30/RF2 | bidirectional | Shared I/O RF2 with remappable peripheral RP30; Schmitt Trigger input, 5.5V tolerant. |
| 53 | RP15/RF8 | bidirectional | Shared I/O RF8 with remappable peripheral RP15; Schmitt Trigger input, 5.5V tolerant. |
| 54 | VBUS/RF7 | power_in | USB VBUS supply detect input shared with I/O RF7; Schmitt Trigger input, 5.5V tolerant. |
| 55 | VUSB3V3 | power_in | 3.3V USB transceiver supply; must always be connected, regardless of whether the USB module is used. |
| 56 | D-/RG3 | bidirectional | USB D- signal of the dedicated transceiver shared with I/O RG3, SCL/SDA-capable I2C1 SDA1 function on other packages; input tolerance limited to VDD. |
| 57 | D+/RG2 | bidirectional | USB D+ signal of the dedicated transceiver shared with I/O RG2; input tolerance limited to VDD. |
| 58 | PMPCS1/SCL2/RA2 | bidirectional | Parallel master chip select 1 PMPCS1 shared with I2C2 clock SCL2 and I/O RA2; Schmitt Trigger input, 5.5V tolerant. |
| 59 | SDA2/PMA20/RA3 | bidirectional | I2C2 data SDA2 shared with parallel address PMA20 and I/O RA3; Schmitt Trigger input, 5.5V tolerant. |
| 60 | TDI/PMA21/RA4 | bidirectional | JTAG test data input TDI shared with parallel address PMA21 and I/O RA4; Schmitt Trigger input, 5.5V tolerant. |
| 61 | TDO/RA5 | bidirectional | JTAG test data output TDO shared with I/O RA5; Schmitt Trigger input, 5.5V tolerant. |
| 62 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins (device supply range 2.0V to 3.6V). |
| 63 | OSCI/CLKI/RC12 | bidirectional | Primary oscillator / external clock input OSCI (CLKI) shared with I/O RC12; the tolerance of RC12 is not stated in Table 11-2. |
| 64 | OSCO/CLKO/RC15 | bidirectional | Primary oscillator output OSCO (CLKO) shared with I/O RC15; input tolerance limited to VDD. |
| 65 | VSS | power_in | Ground reference for peripheral digital logic and I/O pins. |
| 66 | RPI36/SCL1/PMA22/RA14 | bidirectional | Shared I/O RA14 with input-only remappable peripheral RPI36, I2C1 clock SCL1 and parallel address PMA22; Schmitt Trigger input, 5.5V tolerant. |
| 67 | RPI35/SDA1/PMBE1/RA15 | bidirectional | Shared I/O RA15 with input-only remappable peripheral RPI35, I2C1 data SDA1 and parallel byte enable PMBE1; Schmitt Trigger input, 5.5V tolerant. |
| 68 | CLC4OUT/RP2/U6RTS/U6BCLK/ICM5/RD8 | bidirectional | Shared I/O RD8 with CLC4 output, remappable RP2, UART6 RTS/baud clock output and MCCP5 input ICM5; Schmitt Trigger input, 5.5V tolerant. |
| 69 | RP4/PMACK2/RD9 | bidirectional | Shared I/O RD9 with remappable peripheral RP4 and parallel acknowledge input PMACK2; Schmitt Trigger input, 5.5V tolerant. |
| 70 | RP3/PMA15/PMCS2/RD10 | bidirectional | Shared I/O RD10 with remappable peripheral RP3, parallel address PMA15 and chip select PMCS2; Schmitt Trigger input, 5.5V tolerant. |
| 71 | RP12/PMA14/PMCS1/RD11 | bidirectional | Shared I/O RD11 with remappable peripheral RP12, parallel address PMA14 and chip select PMCS1; Schmitt Trigger input, 5.5V tolerant. |
| 72 | CLC3OUT/RP11/U6CTS/ICM6/INT0/RD0 | bidirectional | Shared I/O RD0 with CLC3 output, remappable RP11, UART6 CTS, MCCP6 input ICM6 and external interrupt INT0; Schmitt Trigger input, 5.5V tolerant. |
| 73 | SOSCI/C3IND/RC13 | bidirectional | Secondary oscillator input SOSCI shared with comparator 3 input C3IND and I/O RC13; input tolerance limited to VDD. |
| 74 | SOSCO/C3INC/RPI37/PWRLCLK/RC14 | bidirectional | Secondary oscillator output SOSCO shared with comparator 3 input C3INC, input-only remappable RPI37, RTC 50/60 Hz clock input PWRLCLK and I/O RC14; input tolerance limited to VDD. |
| 75 | VSS | power_in | Ground reference for peripheral digital logic and I/O pins. |
| 76 | RP24/U5TX/ICM4/RD1 | bidirectional | Shared I/O RD1 with remappable RP24, UART5 transmit U5TX and MCCP4 input ICM4; Schmitt Trigger input, 5.5V tolerant. |
| 77 | RP23/PMACK1/RD2 | bidirectional | Shared I/O RD2 with remappable RP23 and parallel acknowledge input PMACK1; Schmitt Trigger input, 5.5V tolerant. |
| 78 | RP22/ICM7/PMBE0/RD3 | bidirectional | Shared I/O RD3 with remappable RP22, MCCP7 input ICM7 and parallel byte enable PMBE0; Schmitt Trigger input, 5.5V tolerant. |
| 79 | RPI42/OCM3E/PMD12/RD12 | bidirectional | Shared I/O RD12 with input-only remappable RPI42, MCCP3 output OCM3E and parallel data PMD12; Schmitt Trigger input, 5.5V tolerant. |
| 80 | OCM3F/PMD13/RD13 | bidirectional | Shared I/O RD13 with MCCP3 output OCM3F and parallel data PMD13; Schmitt Trigger input, 5.5V tolerant. |
| 81 | RP25/PMWR/PMENB/RD4 | bidirectional | Shared I/O RD4 with remappable RP25 and parallel write strobe/enable PMWR/PMENB; Schmitt Trigger input, 5.5V tolerant. |
| 82 | RP20/PMRD/PMWR/RD5 | bidirectional | Shared I/O RD5 with remappable RP20 and parallel read/write strobe PMRD/PMWR; Schmitt Trigger input, 5.5V tolerant. |
| 83 | C3INB/U5RX/OC4/PMD14/RD6 | bidirectional | Comparator 3 input C3INB shared with UART5 receive U5RX, output compare OC4, parallel data PMD14 and I/O RD6; input tolerance limited to VDD. |
| 84 | C3INA/U5RTS/U5BCLK/OC5/PMD15/RD7 | bidirectional | Comparator 3 input C3INA shared with UART5 RTS/baud clock, output compare OC5, parallel data PMD15 and I/O RD7; input tolerance limited to VDD. |
| 85 | VCAP | passive | External filter capacitor connection for the on-chip voltage regulator; requires a low-ESR (<5 Ω) 10 µF capacitor to ground and must not be connected to VDD. |
| 86 | N/C | unconnected | No internal connection on this package. |
| 87 | U5CTS/OC6/PMD11/RF0 | bidirectional | Shared I/O RF0 with UART5 CTS, output compare OC6 and parallel data PMD11; Schmitt Trigger input, 5.5V tolerant. |
| 88 | PMD10/RF1 | bidirectional | Shared I/O RF1 with parallel master port data PMD10; Schmitt Trigger input, 5.5V tolerant. |
| 89 | PMD9/RG1 | bidirectional | Shared I/O RG1 with parallel master port data PMD9; Schmitt Trigger input, 5.5V tolerant. |
| 90 | PMD8/RG0 | bidirectional | Shared I/O RG0 with parallel master port data PMD8; Schmitt Trigger input, 5.5V tolerant. |
| 91 | AN23/OCM1E/RA6 | bidirectional | Analog input AN23 shared with MCCP1 output OCM1E and I/O RA6; input tolerance limited to VDD. |
| 92 | AN22/OCM1F/PMA17/RA7 | bidirectional | Analog input AN22 shared with MCCP1 output OCM1F, parallel address PMA17 and I/O RA7; input tolerance limited to VDD. |
| 93 | PMD0/RE0 | bidirectional | Shared I/O RE0 with parallel master port data PMD0; Schmitt Trigger input, 5.5V tolerant. |
| 94 | PMD1/RE1 | bidirectional | Shared I/O RE1 with parallel master port data PMD1; Schmitt Trigger input, 5.5V tolerant. |
| 95 | CTED11/PMA16/RG14 | bidirectional | Shared I/O RG14 with CTMU edge input CTED11 and parallel address PMA16; Schmitt Trigger input, 5.5V tolerant. |
| 96 | OCM2E/RG12 | bidirectional | Shared I/O RG12 with MCCP2 output OCM2E; Schmitt Trigger input, 5.5V tolerant. |
| 97 | OCM2F/CTED10/RG13 | bidirectional | Shared I/O RG13 with MCCP2 output OCM2F and CTMU edge input CTED10; Schmitt Trigger input, 5.5V tolerant. |
| 98 | PMD2/RE2 | bidirectional | Shared I/O RE2 with parallel master port data PMD2; Schmitt Trigger input, 5.5V tolerant. |
| 99 | CTED9/PMD3/RE3 | bidirectional | Shared I/O RE3 with CTMU edge input CTED9 and parallel master port data PMD3; Schmitt Trigger input, 5.5V tolerant. |
| 100 | HLVDIN/CTED8/PMD4/RE4 | bidirectional | High/Low-Voltage Detect analog input HLVDIN shared with CTMU edge input CTED8, parallel data PMD4 and I/O RE4; input tolerance limited to VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-100(12x12) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2 | 3.6 | V | BOR is disabled | 413 | |
| Supply Voltage (BOR enabled) | VBOR | 3.6 | V | BOR is enabled | 413 | ||
| Brown-out Reset Voltage on VDD Transition, High-to-Low | VBOR | 2 | 2.2 | V | -40°C < TA < +85°C | 413 | |
| Recommended VDD Rise Rate to Ensure Internal Power-on Reset Signal | SVDD | 0.05 | V/mS | 0-3.3V in 66 ms, 0-2.0V in 40 ms | 413 |
CAD (KiCad official)
- Symbol:
PIC24FJ1024GB610-I - Footprint:
Package_QFP:TQFP-100_12x12mm_P0.4mm - 3D model: TQFP-100(12x12) (KiCad packages3D, STEP)
- 3D model files:
pic24fj1024gb610-i-etched.step/pic24fj1024gb610-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic24fj1024gb610-i.step/pic24fj1024gb610-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (470 pp, sha256
a294f3b10e36c406, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).