component
PIC18LF45K22-I
Public Made by Adomby adom
Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PIC18LF45K22-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-40-EP(5x5)
PIC18LF45K22-I from Microchip Tech, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC7/RX1/DT1/AN19 | bidirectional | PORTC bit 7 digital I/O (ST), also EUSART1 asynchronous receive (RX1), synchronous data (DT1) and analog input 19. |
| 2 | RD4/P2D/SDO2/AN24 | bidirectional | PORTD bit 4 digital I/O (ST), also Enhanced CCP2 PWM output P2D, MSSP2 SPI data out (SDO2) and analog input 24. |
| 3 | RD5/P1B/AN25 | bidirectional | PORTD bit 5 digital I/O (ST), also Enhanced CCP1 PWM output P1B and analog input 25. |
| 4 | RD6/P1C/TX2/CK2/AN26 | bidirectional | PORTD bit 6 digital I/O (ST), also Enhanced CCP1 PWM output P1C, EUSART2 transmit (TX2), synchronous clock (CK2) and analog input 26. |
| 5 | RD7/P1D/RX2/DT2/AN27 | bidirectional | PORTD bit 7 digital I/O (ST), also Enhanced CCP1 PWM output P1D, EUSART2 receive (RX2), synchronous data (DT2) and analog input 27. |
| 6 | VSS | power_in | Ground reference for logic and I/O pins. |
| 7 | VDD | power_in | Positive supply for logic and I/O pins. |
| 8 | RB0/INT0/FLT0/SRI/AN12 | bidirectional | PORTB bit 0 digital I/O (TTL), also external interrupt 0, ECCP auto-shutdown fault input FLT0, SR latch input SRI and analog input 12. |
| 9 | RB1/INT1/C12IN3-/AN10 | bidirectional | PORTB bit 1 digital I/O (TTL), also external interrupt 1, comparators C1/C2 inverting input C12IN3- and analog input 10. |
| 10 | RB2/INT2/CTED1/AN8 | bidirectional | PORTB bit 2 digital I/O (TTL), also external interrupt 2, CTMU edge 1 input and analog input 8. |
| 11 | RB3/CTED2/P2A/CCP2/C12IN2-/AN9 | bidirectional | PORTB bit 3 digital I/O (TTL), also CTMU edge 2 input, alternate P2A/CCP2 pin, comparator inverting input C12IN2- and analog input 9. |
| 12 | RB4/IOC0/T5G/AN11 | bidirectional | PORTB bit 4 digital I/O (TTL), also interrupt-on-change 0, Timer5 gate input and analog input 11. |
| 13 | RB5/IOC1/P3A/CCP3/T3CKI/T1G/AN13 | bidirectional | PORTB bit 5 digital I/O (TTL), also interrupt-on-change 1, P3A/CCP3 and T3CKI per configuration bits, Timer1 gate input and analog input 13. |
| 14 | RB6/IOC2/PGC | bidirectional | PORTB bit 6 digital I/O (TTL), also interrupt-on-change 2 and In-Circuit Debugger/ICSP programming clock pin. |
| 15 | RB7/IOC3/PGD | bidirectional | PORTB bit 7 digital I/O (TTL), also interrupt-on-change 3 and In-Circuit Debugger/ICSP programming data pin. |
| 16 | RE3/VPP/MCLR | input | Input-only digital pin (ST) that serves as active-low Master Clear (device Reset) input and as programming voltage input VPP. |
| 17 | RA0/C12IN0-/AN0 | bidirectional | PORTA bit 0 digital I/O (TTL), also comparators C1/C2 inverting input C12IN0- and analog input 0. |
| 18 | RA1/C12IN1-/AN1 | bidirectional | PORTA bit 1 digital I/O (TTL), also comparators C1/C2 inverting input C12IN1- and analog input 1. |
| 19 | RA2/C2IN+/AN2/DACOUT/VREF- | bidirectional | PORTA bit 2 digital I/O (TTL), also comparator C2 noninverting input, analog input 2, DAC reference output and A/D low reference voltage input. |
| 20 | RA3/C1IN+/AN3/VREF+ | bidirectional | PORTA bit 3 digital I/O (TTL), also comparator C1 noninverting input, analog input 3 and A/D high reference voltage input. |
| 21 | RA4/C1OUT/SRQ/T0CKI | bidirectional | PORTA bit 4 digital I/O (ST), also comparator C1 output, SR latch Q output and Timer0 external clock input. |
| 22 | RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4 | bidirectional | PORTA bit 5 digital I/O (TTL), also comparator C2 output, SR latch inverted output, MSSP1 SPI client select, High/Low-Voltage Detect input and analog input 4. |
| 23 | RE0/P3A/CCP3/AN5 | bidirectional | PORTE bit 0 digital I/O (ST), also alternate P3A/CCP3 pin when CCP3MX is clear and analog input 5. |
| 24 | RE1/P3B/AN6 | bidirectional | PORTE bit 1 digital I/O (ST), also Enhanced CCP3 PWM output P3B and analog input 6. |
| 25 | RE2/CCP5/AN7 | bidirectional | PORTE bit 2 digital I/O (ST), also Capture 5 input/Compare 5 output/PWM 5 output and analog input 7. |
| 26 | VDD | power_in | Positive supply for logic and I/O pins. |
| 27 | VSS | power_in | Ground reference for logic and I/O pins. |
| 28 | RA7/CLKI/OSC1 | bidirectional | PORTA bit 7 digital I/O (TTL), also external clock input CLKI and oscillator crystal/external clock input OSC1. |
| 29 | RA6/CLKO/OSC2 | bidirectional | PORTA bit 6 digital I/O (TTL), also CLKOUT (1/4 OSC1 frequency in RC mode) and oscillator crystal output OSC2. |
| 30 | RC0/P2B/T3CKI/T3G/T1CKI/SOSCO | bidirectional | PORTC bit 0 digital I/O (ST), also alternate P2B/T3CKI pin, Timer3 gate, Timer1 clock input and secondary oscillator output. |
| 31 | RC1/P2A/CCP2/SOSCI | bidirectional | PORTC bit 1 digital I/O (ST), also default P2A/CCP2 pin and secondary oscillator input. |
| 32 | RC2/CTPLS/P1A/CCP1/T5CKI/AN14 | bidirectional | PORTC bit 2 digital I/O (ST), also CTMU pulse generator output, Enhanced CCP1 P1A/CCP1, Timer5 clock input and analog input 14. |
| 33 | RC3/SCK1/SCL1/AN15 | bidirectional | PORTC bit 3 digital I/O (ST), also MSSP1 SPI clock (SCK1), I2C clock (SCL1) and analog input 15. |
| 34 | RD0/SCK2/SCL2/AN20 | bidirectional | PORTD bit 0 digital I/O (ST), also MSSP2 SPI clock (SCK2), I2C clock (SCL2) and analog input 20. |
| 35 | RD1/CCP4/SDI2/SDA2/AN21 | bidirectional | PORTD bit 1 digital I/O (ST), also CCP4, MSSP2 SPI data in (SDI2), I2C data (SDA2) and analog input 21. |
| 36 | RD2/P2B/AN22 | bidirectional | PORTD bit 2 digital I/O (ST), also Enhanced CCP2 PWM output P2B and analog input 22. |
| 37 | RD3/P2C/SS2/AN23 | bidirectional | PORTD bit 3 digital I/O (ST), also Enhanced CCP2 PWM output P2C, MSSP2 SPI client select (SS2) and analog input 23. |
| 38 | RC4/SDI1/SDA1/AN16 | bidirectional | PORTC bit 4 digital I/O (ST), also MSSP1 SPI data in (SDI1), I2C data (SDA1) and analog input 16. |
| 39 | RC5/SDO1/AN17 | bidirectional | PORTC bit 5 digital I/O (ST), also MSSP1 SPI data out (SDO1) and analog input 17. |
| 40 | RC6/TX1/CK1/AN18 | bidirectional | PORTC bit 6 digital I/O (ST), also EUSART1 transmit (TX1), synchronous clock (CK1) and analog input 18. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-40-EP(5x5) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 41 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (PIC18LF2X/4XK22) | VDD | 1.8 | 3.6 | V | PIC18LF2X/4XK22 | 417 | |
| RAM Data Retention Voltage | VDR | 1.5 | V | 417 | |||
| VDD Start Voltage to ensure internal Power-on Reset | VPOR | 0.7 | V | See section on Power-on Reset for details | 417 | ||
| VDD Rise Rate to ensure internal Power-on Reset | SVDD | 0.05 | V/ms | See section on Power-on Reset for details | 417 | ||
| Brown-out Reset Voltage | VBOR | 1.75 | 1.9 | 2.05 | V | BORV<1:0> = 11 | 417 |
| Brown-out Reset Voltage | VBOR | 2.05 | 2.2 | 2.35 | V | BORV<1:0> = 10 | 417 |
| Brown-out Reset Voltage | VBOR | 2.35 | 2.5 | 2.65 | V | BORV<1:0> = 01 | 417 |
| Brown-out Reset Voltage | VBOR | 2.65 | 2.85 | 3.05 | V | BORV<1:0> = 00 | 417 |
| Operating temperature | TA | -40 | 125 | °C | Standard Operating Conditions | 417 | |
| Ambient temperature under bias | -40 | 125 | °C | 414 | |||
| Storage temperature | -65 | 150 | °C | 414 | |||
| Voltage on any pin with respect to VSS (except VDD and MCLR) | -0.3 | V | max is (VDD + 0.3V) | 414 | |||
| Voltage on MCLR with respect to VSS | 0 | 11 | V | Note 2 | 414 | ||
| Total power dissipation | 1 | W | Note 1 | 414 | |||
| Maximum current out of VSS pin | 300 | mA | -40°C to +85°C | 414 | |||
| Maximum current out of VSS pin | 125 | mA | +85°C to +125°C | 414 | |||
| Maximum current into VDD pin | 200 | mA | -40°C to +85°C | 414 | |||
| Maximum current into VDD pin | 85 | mA | +85°C to +125°C | 414 | |||
| Input clamp current | IIK | 20 | mA | VI < 0 or VI > VDD | 414 | ||
| Output clamp current | IOK | 20 | mA | VO < 0 or VO > VDD | 414 | ||
| Maximum current sunk by all ports | 200 | mA | -40°C to +85°C | 414 | |||
| Sleep mode power-down base current | IPD | 0.01 | 2 | µA | VDD=1.8V, Max at +85°C (Max +125°C: 10); WDT, BOR, FVR and SOSC disabled | 418 | |
| Watchdog Timer delta current | ΔIPD | 0.3 | 2.5 | µA | VDD=1.8V, typ at +25°C, max at +85°C | 418 | |
| Supply current RC_RUN LFINTOSC 31 kHz | IDD | 3.6 | 23 | µA | VDD=1.8V, FOSC=31 kHz, -40°C | 420 | |
| Supply current RC_RUN HFINTOSC 16 MHz | IDD | 1.3 | 2 | mA | VDD=1.8V, FOSC=16 MHz, -40°C to +125°C | 421 |
CAD (KiCad official)
- Symbol:
PIC18LF45K22-I - Footprint:
Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm - 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
pic18lf45k22-i-etched.step/pic18lf45k22-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic18lf45k22-i.step/pic18lf45k22-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (539 pp, sha256
d0ba745eb6a13bdb, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PIC18LF45K22-I
**Microchip Tech** · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-40-EP(5x5)
PIC18LF45K22-I from Microchip Tech, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC7/RX1/DT1/AN19 | bidirectional | PORTC bit 7 digital I/O (ST), also EUSART1 asynchronous receive (RX1), synchronous data (DT1) and analog input 19. |
| 2 | RD4/P2D/SDO2/AN24 | bidirectional | PORTD bit 4 digital I/O (ST), also Enhanced CCP2 PWM output P2D, MSSP2 SPI data out (SDO2) and analog input 24. |
| 3 | RD5/P1B/AN25 | bidirectional | PORTD bit 5 digital I/O (ST), also Enhanced CCP1 PWM output P1B and analog input 25. |
| 4 | RD6/P1C/TX2/CK2/AN26 | bidirectional | PORTD bit 6 digital I/O (ST), also Enhanced CCP1 PWM output P1C, EUSART2 transmit (TX2), synchronous clock (CK2) and analog input 26. |
| 5 | RD7/P1D/RX2/DT2/AN27 | bidirectional | PORTD bit 7 digital I/O (ST), also Enhanced CCP1 PWM output P1D, EUSART2 receive (RX2), synchronous data (DT2) and analog input 27. |
| 6 | VSS | power_in | Ground reference for logic and I/O pins. |
| 7 | VDD | power_in | Positive supply for logic and I/O pins. |
| 8 | RB0/INT0/FLT0/SRI/AN12 | bidirectional | PORTB bit 0 digital I/O (TTL), also external interrupt 0, ECCP auto-shutdown fault input FLT0, SR latch input SRI and analog input 12. |
| 9 | RB1/INT1/C12IN3-/AN10 | bidirectional | PORTB bit 1 digital I/O (TTL), also external interrupt 1, comparators C1/C2 inverting input C12IN3- and analog input 10. |
| 10 | RB2/INT2/CTED1/AN8 | bidirectional | PORTB bit 2 digital I/O (TTL), also external interrupt 2, CTMU edge 1 input and analog input 8. |
| 11 | RB3/CTED2/P2A/CCP2/C12IN2-/AN9 | bidirectional | PORTB bit 3 digital I/O (TTL), also CTMU edge 2 input, alternate P2A/CCP2 pin, comparator inverting input C12IN2- and analog input 9. |
| 12 | RB4/IOC0/T5G/AN11 | bidirectional | PORTB bit 4 digital I/O (TTL), also interrupt-on-change 0, Timer5 gate input and analog input 11. |
| 13 | RB5/IOC1/P3A/CCP3/T3CKI/T1G/AN13 | bidirectional | PORTB bit 5 digital I/O (TTL), also interrupt-on-change 1, P3A/CCP3 and T3CKI per configuration bits, Timer1 gate input and analog input 13. |
| 14 | RB6/IOC2/PGC | bidirectional | PORTB bit 6 digital I/O (TTL), also interrupt-on-change 2 and In-Circuit Debugger/ICSP programming clock pin. |
| 15 | RB7/IOC3/PGD | bidirectional | PORTB bit 7 digital I/O (TTL), also interrupt-on-change 3 and In-Circuit Debugger/ICSP programming data pin. |
| 16 | RE3/VPP/MCLR | input | Input-only digital pin (ST) that serves as active-low Master Clear (device Reset) input and as programming voltage input VPP. |
| 17 | RA0/C12IN0-/AN0 | bidirectional | PORTA bit 0 digital I/O (TTL), also comparators C1/C2 inverting input C12IN0- and analog input 0. |
| 18 | RA1/C12IN1-/AN1 | bidirectional | PORTA bit 1 digital I/O (TTL), also comparators C1/C2 inverting input C12IN1- and analog input 1. |
| 19 | RA2/C2IN+/AN2/DACOUT/VREF- | bidirectional | PORTA bit 2 digital I/O (TTL), also comparator C2 noninverting input, analog input 2, DAC reference output and A/D low reference voltage input. |
| 20 | RA3/C1IN+/AN3/VREF+ | bidirectional | PORTA bit 3 digital I/O (TTL), also comparator C1 noninverting input, analog input 3 and A/D high reference voltage input. |
| 21 | RA4/C1OUT/SRQ/T0CKI | bidirectional | PORTA bit 4 digital I/O (ST), also comparator C1 output, SR latch Q output and Timer0 external clock input. |
| 22 | RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4 | bidirectional | PORTA bit 5 digital I/O (TTL), also comparator C2 output, SR latch inverted output, MSSP1 SPI client select, High/Low-Voltage Detect input and analog input 4. |
| 23 | RE0/P3A/CCP3/AN5 | bidirectional | PORTE bit 0 digital I/O (ST), also alternate P3A/CCP3 pin when CCP3MX is clear and analog input 5. |
| 24 | RE1/P3B/AN6 | bidirectional | PORTE bit 1 digital I/O (ST), also Enhanced CCP3 PWM output P3B and analog input 6. |
| 25 | RE2/CCP5/AN7 | bidirectional | PORTE bit 2 digital I/O (ST), also Capture 5 input/Compare 5 output/PWM 5 output and analog input 7. |
| 26 | VDD | power_in | Positive supply for logic and I/O pins. |
| 27 | VSS | power_in | Ground reference for logic and I/O pins. |
| 28 | RA7/CLKI/OSC1 | bidirectional | PORTA bit 7 digital I/O (TTL), also external clock input CLKI and oscillator crystal/external clock input OSC1. |
| 29 | RA6/CLKO/OSC2 | bidirectional | PORTA bit 6 digital I/O (TTL), also CLKOUT (1/4 OSC1 frequency in RC mode) and oscillator crystal output OSC2. |
| 30 | RC0/P2B/T3CKI/T3G/T1CKI/SOSCO | bidirectional | PORTC bit 0 digital I/O (ST), also alternate P2B/T3CKI pin, Timer3 gate, Timer1 clock input and secondary oscillator output. |
| 31 | RC1/P2A/CCP2/SOSCI | bidirectional | PORTC bit 1 digital I/O (ST), also default P2A/CCP2 pin and secondary oscillator input. |
| 32 | RC2/CTPLS/P1A/CCP1/T5CKI/AN14 | bidirectional | PORTC bit 2 digital I/O (ST), also CTMU pulse generator output, Enhanced CCP1 P1A/CCP1, Timer5 clock input and analog input 14. |
| 33 | RC3/SCK1/SCL1/AN15 | bidirectional | PORTC bit 3 digital I/O (ST), also MSSP1 SPI clock (SCK1), I2C clock (SCL1) and analog input 15. |
| 34 | RD0/SCK2/SCL2/AN20 | bidirectional | PORTD bit 0 digital I/O (ST), also MSSP2 SPI clock (SCK2), I2C clock (SCL2) and analog input 20. |
| 35 | RD1/CCP4/SDI2/SDA2/AN21 | bidirectional | PORTD bit 1 digital I/O (ST), also CCP4, MSSP2 SPI data in (SDI2), I2C data (SDA2) and analog input 21. |
| 36 | RD2/P2B/AN22 | bidirectional | PORTD bit 2 digital I/O (ST), also Enhanced CCP2 PWM output P2B and analog input 22. |
| 37 | RD3/P2C/SS2/AN23 | bidirectional | PORTD bit 3 digital I/O (ST), also Enhanced CCP2 PWM output P2C, MSSP2 SPI client select (SS2) and analog input 23. |
| 38 | RC4/SDI1/SDA1/AN16 | bidirectional | PORTC bit 4 digital I/O (ST), also MSSP1 SPI data in (SDI1), I2C data (SDA1) and analog input 16. |
| 39 | RC5/SDO1/AN17 | bidirectional | PORTC bit 5 digital I/O (ST), also MSSP1 SPI data out (SDO1) and analog input 17. |
| 40 | RC6/TX1/CK1/AN18 | bidirectional | PORTC bit 6 digital I/O (ST), also EUSART1 transmit (TX1), synchronous clock (CK1) and analog input 18. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-40-EP(5x5) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 41 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (PIC18LF2X/4XK22) | VDD | 1.8 | | 3.6 | V | PIC18LF2X/4XK22 | 417 |
| RAM Data Retention Voltage | VDR | 1.5 | | | V | | 417 |
| VDD Start Voltage to ensure internal Power-on Reset | VPOR | | | 0.7 | V | See section on Power-on Reset for details | 417 |
| VDD Rise Rate to ensure internal Power-on Reset | SVDD | 0.05 | | | V/ms | See section on Power-on Reset for details | 417 |
| Brown-out Reset Voltage | VBOR | 1.75 | 1.9 | 2.05 | V | BORV<1:0> = 11 | 417 |
| Brown-out Reset Voltage | VBOR | 2.05 | 2.2 | 2.35 | V | BORV<1:0> = 10 | 417 |
| Brown-out Reset Voltage | VBOR | 2.35 | 2.5 | 2.65 | V | BORV<1:0> = 01 | 417 |
| Brown-out Reset Voltage | VBOR | 2.65 | 2.85 | 3.05 | V | BORV<1:0> = 00 | 417 |
| Operating temperature | TA | -40 | | 125 | °C | Standard Operating Conditions | 417 |
| Ambient temperature under bias | | -40 | | 125 | °C | | 414 |
| Storage temperature | | -65 | | 150 | °C | | 414 |
| Voltage on any pin with respect to VSS (except VDD and MCLR) | | -0.3 | | | V | max is (VDD + 0.3V) | 414 |
| Voltage on MCLR with respect to VSS | | 0 | | 11 | V | Note 2 | 414 |
| Total power dissipation | | | | 1 | W | Note 1 | 414 |
| Maximum current out of VSS pin | | | | 300 | mA | -40°C to +85°C | 414 |
| Maximum current out of VSS pin | | | | 125 | mA | +85°C to +125°C | 414 |
| Maximum current into VDD pin | | | | 200 | mA | -40°C to +85°C | 414 |
| Maximum current into VDD pin | | | | 85 | mA | +85°C to +125°C | 414 |
| Input clamp current | IIK | | | 20 | mA | VI < 0 or VI > VDD | 414 |
| Output clamp current | IOK | | | 20 | mA | VO < 0 or VO > VDD | 414 |
| Maximum current sunk by all ports | | | | 200 | mA | -40°C to +85°C | 414 |
| Sleep mode power-down base current | IPD | | 0.01 | 2 | µA | VDD=1.8V, Max at +85°C (Max +125°C: 10); WDT, BOR, FVR and SOSC disabled | 418 |
| Watchdog Timer delta current | ΔIPD | | 0.3 | 2.5 | µA | VDD=1.8V, typ at +25°C, max at +85°C | 418 |
| Supply current RC_RUN LFINTOSC 31 kHz | IDD | | 3.6 | 23 | µA | VDD=1.8V, FOSC=31 kHz, -40°C | 420 |
| Supply current RC_RUN HFINTOSC 16 MHz | IDD | | 1.3 | 2 | mA | VDD=1.8V, FOSC=16 MHz, -40°C to +125°C | 421 |
## CAD (KiCad official)
- Symbol: `PIC18LF45K22-I`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm`
- 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `pic18lf45k22-i-etched.step` / `pic18lf45k22-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic18lf45k22-i.step` / `pic18lf45k22-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/pic18lf45k22-i-datasheet.pdf) (539 pp, sha256 `d0ba745eb6a13bdb`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pic18lf45k22-i-datasheet.pdf)