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PIC18F97J60-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), TQFP-100(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC18F97J60-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-100(12x12)

PIC18F97J60-I from Microchip Tech, in a TQFP-100(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RH2/A18 bidirectional Digital I/O (Schmitt Trigger input, 5.5V tolerant) also used as external memory address line A18.
2 RH3/A19 bidirectional Digital I/O (Schmitt Trigger input, 5.5V tolerant) also used as external memory address line A19.
3 RE1/AD9/WR/P2C bidirectional Digital I/O with TTL input levels also used as external memory AD9, Parallel Slave Port write control, and ECCP2 PWM output C.
4 RE0/AD8/RD/P2D bidirectional Digital I/O with TTL input levels also used as external memory AD8, Parallel Slave Port read control, and ECCP2 PWM output D.
5 RB0/INT0/FLT0 bidirectional Digital I/O with TTL input levels, weak pull-up, External Interrupt 0 and ECCP Fault input.
6 RB1/INT1 bidirectional Digital I/O with TTL input levels, weak pull-up and External Interrupt 1.
7 RB2/INT2 bidirectional Digital I/O with TTL input levels, weak pull-up and External Interrupt 2.
8 RB3/INT3/ECCP2/P2A bidirectional Digital I/O with TTL input levels, weak pull-up, External Interrupt 3, and alternate ECCP2 capture/compare/PWM output A.
9 NC unconnected No connect; not internally connected on this package.
10 RG6 bidirectional Digital I/O only, Schmitt Trigger input, tolerates up to 5.5V.
11 RG5 bidirectional Digital I/O only, Schmitt Trigger input, tolerates up to 5.5V.
12 RF0/AN5 bidirectional Digital I/O with Schmitt Trigger input and Analog Input 5 for the A/D converter.
13 MCLR input Master Clear (Reset) input, active-low Reset to the device.
14 RG4/CCP5/P1D bidirectional Digital I/O with Schmitt Trigger input, also CCP5 capture/compare/PWM and ECCP1 PWM output D.
15 VSS power_in Ground reference for logic and I/O pins.
16 VDDCORE/VCAP power_in Core logic power supply when regulator disabled, or external filter capacitor connection (10 uF, ESR under 5 ohm) when regulator enabled.
17 VDD power_in Positive supply for peripheral digital logic and I/O pins.
18 RF7/SS1 bidirectional Digital I/O with Schmitt Trigger input, also SPI slave select input for MSSP1 (TTL levels).
19 RF6/AN11 bidirectional Digital I/O with Schmitt Trigger input and Analog Input 11.
20 RF5/AN10/CVREF bidirectional Digital I/O with Schmitt Trigger input, Analog Input 10, and comparator voltage reference output.
21 RF4/AN9 bidirectional Digital I/O with Schmitt Trigger input and Analog Input 9.
22 RF3/AN8 bidirectional Digital I/O with Schmitt Trigger input and Analog Input 8.
23 RF2/AN7/C1OUT bidirectional Digital I/O with Schmitt Trigger input, Analog Input 7, and Comparator 1 output.
24 RH7/AN15/P1B bidirectional Digital I/O with Schmitt Trigger input, Analog Input 15, and ECCP1 PWM output B.
25 RH6/AN14/P1C bidirectional Digital I/O with Schmitt Trigger input, Analog Input 14, and ECCP1 PWM output C.
26 RH5/AN13/P3B bidirectional Digital I/O with Schmitt Trigger input, Analog Input 13, and ECCP3 PWM output B.
27 RH4/AN12/P3C bidirectional Digital I/O with Schmitt Trigger input, Analog Input 12, and ECCP3 PWM output C.
28 RF1/AN6/C2OUT bidirectional Digital I/O with Schmitt Trigger input, Analog Input 6, and Comparator 2 output.
29 ENVREG input Enable for on-chip voltage regulator; must be tied to VDD to enable or to ground to disable.
30 AVDD power_in Positive supply for analog modules; must always be connected.
31 AVSS power_in Ground reference for analog modules; must always be connected.
32 RA3/AN3/VREF+ bidirectional Digital I/O with TTL input levels, Analog Input 3, and A/D high reference voltage input.
33 RA2/AN2/VREF- bidirectional Digital I/O with TTL input levels, Analog Input 2, and A/D low reference voltage input.
34 RA1/LEDB/AN1 bidirectional Digital I/O with TTL input levels, Ethernet LEDB indicator output, and Analog Input 1.
35 RA0/LEDA/AN0 bidirectional Digital I/O with TTL input levels, Ethernet LEDA indicator output, and Analog Input 0.
36 VSS power_in Ground reference for logic and I/O pins.
37 VDD power_in Positive supply for peripheral digital logic and I/O pins.
38 RG7 bidirectional Digital I/O only, Schmitt Trigger input, tolerates up to 5.5V.
39 RJ7/UB bidirectional Digital I/O with Schmitt Trigger input, also external memory upper byte enable control output.
40 VSS power_in Ground reference for logic and I/O pins.
41 RA5/AN4 bidirectional Digital I/O with TTL input levels and Analog Input 4.
42 RA4/T0CKI bidirectional Digital I/O with Schmitt Trigger input and Timer0 external clock input.
43 RC1/T1OSI/ECCP2/P2A bidirectional Digital I/O with Schmitt Trigger input, Timer1 oscillator input, and default ECCP2 capture/compare/PWM output A.
44 RC0/T1OSO/T13CKI bidirectional Digital I/O with Schmitt Trigger input, Timer1 oscillator output, and Timer1/Timer3 external clock input.
45 RC6/TX1/CK1 bidirectional Digital I/O with Schmitt Trigger input, EUSART1 asynchronous transmit and synchronous clock.
46 RC7/RX1/DT1 bidirectional Digital I/O with Schmitt Trigger input, EUSART1 asynchronous receive and synchronous data.
47 RJ4/BA0 bidirectional Digital I/O with Schmitt Trigger input, also external memory byte address 0 control output.
48 RJ5/CE bidirectional Digital I/O with Schmitt Trigger input, also external memory chip enable control output.
49 RJ0/ALE bidirectional Digital I/O with Schmitt Trigger input, also external memory address latch enable output.
50 RJ1/OE bidirectional Digital I/O with Schmitt Trigger input, also external memory output enable control output.
51 RG3/CCP4/P3D bidirectional Digital I/O with Schmitt Trigger input, CCP4 capture/compare/PWM, and ECCP3 PWM output D.
52 RG2/RX2/DT2 bidirectional Digital I/O with Schmitt Trigger input, EUSART2 asynchronous receive and synchronous data.
53 RC2/ECCP1/P1A bidirectional Digital I/O with Schmitt Trigger input, ECCP1 capture/compare/PWM and PWM output A.
54 RC3/SCK1/SCL1 bidirectional Digital I/O with Schmitt Trigger input, MSSP1 SPI clock and I2C clock.
55 RC4/SDI1/SDA1 bidirectional Digital I/O with Schmitt Trigger input, MSSP1 SPI data in and I2C data.
56 RC5/SDO1 bidirectional Digital I/O with Schmitt Trigger input and MSSP1 SPI data output.
57 RB7/KBI3/PGD bidirectional Digital I/O with TTL input levels, weak pull-up, interrupt-on-change and ICSP data pin.
58 RJ6/LB bidirectional Digital I/O with Schmitt Trigger input, also external memory lower byte enable control output.
59 VDD power_in Positive supply for peripheral digital logic and I/O pins.
60 VSS power_in Ground reference for logic and I/O pins.
61 RJ3/WRH bidirectional Digital I/O with Schmitt Trigger input, also external memory write high byte control output.
62 VDD power_in Positive supply for peripheral digital logic and I/O pins.
63 OSC1/CLKI input Oscillator crystal input or external clock source input (ST buffer in internal RC mode, CMOS otherwise).
64 OSC2/CLKO output Oscillator crystal output, or CLKO output at one quarter of OSC1 frequency in internal RC mode.
65 VSS power_in Ground reference for logic and I/O pins.
66 RJ2/WRL bidirectional Digital I/O with Schmitt Trigger input, also external memory write low byte control output.
67 RB6/KBI2/PGC bidirectional Digital I/O with TTL input levels, weak pull-up, interrupt-on-change and ICSP clock pin.
68 RB5/KBI1 bidirectional Digital I/O with TTL input levels, weak pull-up and interrupt-on-change.
69 RB4/KBI0 bidirectional Digital I/O with TTL input levels, weak pull-up and interrupt-on-change.
70 RG1/TX2/CK2 bidirectional Digital I/O with Schmitt Trigger input, EUSART2 asynchronous transmit and synchronous clock.
71 RG0/ECCP3/P3A bidirectional Digital I/O with Schmitt Trigger input, ECCP3 capture/compare/PWM and PWM output A.
72 VSSRX power_in Ground reference for Ethernet PHY receive subsystem.
73 TPIN- input Analog Ethernet differential signal input (negative).
74 TPIN+ input Analog Ethernet differential signal input (positive).
75 VDDRX power_in Positive 3.3V supply for Ethernet PHY receive subsystem.
76 VDDTX power_in Positive 3.3V supply for Ethernet PHY transmit subsystem.
77 TPOUT- output Ethernet differential signal output (negative).
78 TPOUT+ output Ethernet differential signal output (positive).
79 VSSTX power_in Ground reference for Ethernet PHY transmit subsystem.
80 RBIAS passive Analog bias current for Ethernet PHY; must be tied to VSS via a resistor (see Section 19.0 for specification).
81 VDDPLL power_in Positive 3.3V supply for Ethernet PHY PLL.
82 VSSPLL power_in Ground reference for Ethernet PHY PLL.
83 RD7/AD7/PSP7/SS2 bidirectional Digital I/O with Schmitt Trigger input, also external memory AD7, Parallel Slave Port data and MSSP2 SPI slave select.
84 RD6/AD6/PSP6/SCK2/SCL2 bidirectional Digital I/O with Schmitt Trigger input, also external memory AD6, Parallel Slave Port data and MSSP2 SPI/I2C clock.
85 VSS power_in Ground reference for logic and I/O pins.
86 VDD power_in Positive supply for peripheral digital logic and I/O pins.
87 RD5/AD5/PSP5/SDI2/SDA2 bidirectional Digital I/O with Schmitt Trigger input, also external memory AD5, Parallel Slave Port data and MSSP2 SPI data in / I2C data.
88 RD4/AD4/PSP4/SDO2 bidirectional Digital I/O with Schmitt Trigger input, also external memory AD4, Parallel Slave Port data and MSSP2 SPI data output.
89 RD3/AD3/PSP3 bidirectional Digital I/O with Schmitt Trigger input, also external memory AD3 and Parallel Slave Port data.
90 RD2/AD2/PSP2 bidirectional Digital I/O with Schmitt Trigger input, also external memory AD2 and Parallel Slave Port data.
91 RD1/AD1/PSP1 bidirectional Digital I/O with Schmitt Trigger input, also external memory AD1 and Parallel Slave Port data.
92 RD0/AD0/PSP0 bidirectional Digital I/O with Schmitt Trigger input, also external memory AD0 and Parallel Slave Port data.
93 RE7/AD15/ECCP2/P2A bidirectional Digital I/O with Schmitt Trigger input, also external memory AD15, ECCP2 capture/compare and PWM output A.
94 RE6/AD14/P1B bidirectional Digital I/O with Schmitt Trigger input, also external memory AD14 and ECCP1 PWM output B.
95 RE5/AD13/P1C bidirectional Digital I/O with Schmitt Trigger input, also external memory AD13 and ECCP1 PWM output C.
96 RE4/AD12/P3B bidirectional Digital I/O with Schmitt Trigger input, also external memory AD12 and ECCP3 PWM output B.
97 RE3/AD11/P3C bidirectional Digital I/O with Schmitt Trigger input, also external memory AD11 and ECCP3 PWM output C.
98 RE2/AD10/CS/P2B bidirectional Digital I/O with Schmitt Trigger input, also external memory AD10, Parallel Slave Port chip select and ECCP2 PWM output B.
99 RH0/A16 bidirectional Digital I/O with Schmitt Trigger input, also external memory address line A16.
100 RH1/A17 bidirectional Digital I/O with Schmitt Trigger input, also external memory address line A17.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-100(12x12)
Category Single Chip Microcomputer/Microcontroller
Pins 100

CAD (KiCad official)

  • Symbol: PIC18F97J60-I
  • Footprint: Package_QFP:TQFP-100_12x12mm_P0.4mm
  • 3D model: TQFP-100(12x12) (KiCad packages3D, STEP)
  • 3D model files: pic18f97j60-i-etched.step / pic18f97j60-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic18f97j60-i.step / pic18f97j60-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (492 pp, sha256 a5190601007a9ae0, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF