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PIC18F87K90-I

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Microchip Tech MICROCHIP, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC18F87K90-I

Microchip Tech · MICROCHIP · TQFP-80(12x12)

PIC18F87K90-I from Microchip Tech, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RH2/SEG45/AN21 bidirectional PORTH digital I/O RH2, multiplexed with LCD segment 45 output and analog input 21.
2 RH3/SEG44/AN20 bidirectional PORTH digital I/O RH3, multiplexed with LCD segment 44 output and analog input 20.
3 RE1/LCDBIAS2/P2C bidirectional PORTE digital I/O RE1, LCD BIAS2 input, or ECCP2 PWM Output C.
4 RE0/LCDBIAS1/P2D bidirectional PORTE digital I/O RE0, LCD BIAS1 input, or ECCP2 PWM Output D.
5 RG0/ECCP3/P3A bidirectional PORTG digital I/O RG0, ECCP3 capture input/compare output/PWM3 output, or ECCP3 PWM Output A.
6 RG1/TX2/CK2/AN19/C3OUT bidirectional PORTG digital I/O RG1, EUSART2 asynchronous transmit or synchronous clock, analog input 19, or comparator 3 output.
7 RG2/RX2/DT2/AN18/C3INA bidirectional PORTG digital I/O RG2, EUSART2 asynchronous receive or synchronous data, analog input 18, or comparator 3 input A.
8 RG3/CCP4/AN17/P3D/C3INB bidirectional PORTG digital I/O RG3, CCP4 capture/compare/PWM, analog input 17, ECCP3 PWM Output D, or comparator 3 input B.
9 MCLR/RG5 input Active-low Master Clear Reset input or programming voltage input; also general purpose input-only pin RG5.
10 RG4/SEG26/RTCC/T7CKI/T5G/CCP5/AN16/P1D/C3INC bidirectional PORTG digital I/O RG4 multiplexed with LCD segment 26, RTCC output, Timer7 clock input, Timer5 gate, CCP5, analog input 16, ECCP1 PWM Output D and comparator 3 input C.
11 VSS power_in Ground reference for logic and I/O pins.
12 VDDCORE/VCAP power_in Core logic power or external filter capacitor connection (regulator enabled/disabled).
13 RF7/AN5/SS1/SEG25 bidirectional PORTF digital I/O RF7, analog input 5, SPI1 slave select input, or LCD segment 25 output.
14 RF6/AN11/SEG24/C1INA bidirectional PORTF digital I/O RF6, analog input 11, LCD segment 24 output, or comparator 1 input A.
15 RF5/AN10/CVREF/SEG23/C1INB bidirectional PORTF digital I/O RF5, analog input 10, comparator reference voltage output, LCD segment 23, or comparator 1 input B.
16 RF4/AN9/SEG22/C2INA bidirectional PORTF digital I/O RF4, analog input 9, LCD segment 22 output, or comparator 2 input A.
17 RF3/AN8/SEG21/C2INB bidirectional PORTF digital I/O RF3, analog input 8, LCD segment 21 output, or comparator 2 input B.
18 RF2/AN7/C1OUT/SEG20/CTMUI bidirectional PORTF digital I/O RF2, analog input 7, comparator 1 output, LCD segment 20, or CTMU pulse generator charger output.
19 RH7/SEG43/CCP6/P1B/AN15 bidirectional PORTH digital I/O RH7, LCD segment 43, CCP6, ECCP1 PWM Output B, or analog input 15.
20 RH6/SEG42/CCP7/P1C/AN14/C1INC bidirectional PORTH digital I/O RH6, LCD segment 42, CCP7, ECCP1 PWM Output C, analog input 14, or comparator 1 input C.
21 RH5/SEG41/CCP8/P3B/AN13/C2IND bidirectional PORTH digital I/O RH5, LCD segment 41, CCP8, ECCP3 PWM Output B, analog input 13, or comparator input D.
22 RH4/SEG40/CCP9/P3C/AN12/C2INC bidirectional PORTH digital I/O RH4, LCD segment 40, CCP9, ECCP3 PWM Output C, analog input 12, or comparator 2 input C.
23 RF1/AN6/C2OUT/SEG19/CTDIN bidirectional PORTF digital I/O RF1, analog input 6, comparator 2 output, LCD segment 19, or CTMU pulse delay input.
24 ENVREG input Enable input for the on-chip voltage regulator; tie to VDD to enable or to ground to disable.
25 AVDD power_in Positive supply for analog modules; must always be connected.
26 AVSS power_in Ground reference for analog modules; must always be connected.
27 RA3/AN3/VREF+ bidirectional PORTA digital I/O RA3, analog input 3, or A/D reference voltage (high) input.
28 RA2/AN2/VREF- bidirectional PORTA digital I/O RA2, analog input 2, or A/D reference voltage (low) input.
29 RA1/AN1/SEG18 bidirectional PORTA digital I/O RA1, analog input 1, or LCD segment 18 output.
30 RA0/AN0/ULPWU bidirectional PORTA digital I/O RA0, analog input 0, or ultra low-power wake-up input.
31 VSS power_in Ground reference for logic and I/O pins.
32 VDD power_in Positive supply for logic and I/O pins.
33 RA5/AN4/SEG15/T1CKI/T3G/HLVDIN bidirectional PORTA digital I/O RA5, analog input 4, LCD segment 15, Timer1 clock input, Timer3 gate input, or HLVD input.
34 RA4/T0CKI/SEG14 bidirectional PORTA digital I/O RA4 (Schmitt Trigger), Timer0 external clock input, or LCD segment 14 output.
35 RC1/SOSCI/ECCP2/SEG32/P2A bidirectional PORTC digital I/O RC1, SOSC oscillator input, ECCP2 capture/compare/PWM, LCD segment 32, or ECCP2 PWM Output A.
36 RC0/SOSCO/SCKLI bidirectional PORTC digital I/O RC0, SOSC oscillator output, or digital SOSC clock input.
37 RC6/TX1/CK1/SEG27 bidirectional PORTC digital I/O RC6, EUSART1 asynchronous transmit or synchronous clock, or LCD segment 27 output.
38 RC7/RX1/DT1/SEG28 bidirectional PORTC digital I/O RC7, EUSART1 asynchronous receive or synchronous data, or LCD segment 28 output.
39 RJ4/SEG39 bidirectional PORTJ digital I/O RJ4 or LCD segment 39 output.
40 RJ5/SEG38 bidirectional PORTJ digital I/O RJ5 or LCD segment 38 output.
41 RJ6/SEG37 bidirectional PORTJ digital I/O RJ6 or LCD segment 37 output.
42 RJ7/SEG36 bidirectional PORTJ digital I/O RJ7 or LCD segment 36 output.
43 RC2/ECCP1/P1A/SEG13 bidirectional PORTC digital I/O RC2, ECCP1 capture/compare/PWM, ECCP1 PWM Output A, or LCD segment 13 output.
44 RC3/SCK1/SCL1/SEG17 bidirectional PORTC digital I/O RC3, SPI/I2C clock for MSSP1, or LCD segment 17 output.
45 RC4/SDI1/SDA1/SEG16 bidirectional PORTC digital I/O RC4, SPI data in or I2C data I/O for MSSP1, or LCD segment 16 output.
46 RC5/SDO1/SEG12 bidirectional PORTC digital I/O RC5, SPI data out, or LCD segment 12 output.
47 RB7/KBI3/PGD bidirectional PORTB digital I/O RB7, interrupt-on-change, or In-Circuit Debugger and ICSP programming data pin.
48 VDD power_in Positive supply for logic and I/O pins.
49 OSC1/CLKI/RA7 bidirectional Oscillator crystal or external clock input (CMOS), or general purpose I/O RA7.
50 OSC2/CLKO/RA6 bidirectional Oscillator crystal output or FOSC/4 clock output, or general purpose I/O RA6.
51 VSS power_in Ground reference for logic and I/O pins.
52 RB6/KBI2/PGC bidirectional PORTB digital I/O RB6, interrupt-on-change, or In-Circuit Debugger and ICSP programming clock pin.
53 RB5/KBI1/SEG29/T3CKI/T1G bidirectional PORTB digital I/O RB5, interrupt-on-change, LCD segment 29, Timer3 clock input, or Timer1 gate input.
54 RB4/KBI0/SEG11 bidirectional PORTB digital I/O RB4, interrupt-on-change, or LCD segment 11 output.
55 RB3/INT3/SEG10/CTED2/ECCP2/P2A bidirectional PORTB digital I/O RB3, external interrupt 3, LCD segment 10, CTMU edge 2 input, ECCP2, or ECCP2 PWM Output A.
56 RB2/INT2/SEG9/CTED1 bidirectional PORTB digital I/O RB2, external interrupt 2, LCD segment 9 output, or CTMU edge 1 input.
57 RB1/INT1/SEG8 bidirectional PORTB digital I/O RB1, external interrupt 1, or LCD segment 8 output.
58 RB0/INT0/SEG30/FLT0 bidirectional PORTB digital I/O RB0, external interrupt 0, LCD segment 30, or Enhanced PWM Fault input for ECCP1/2/3.
59 RJ3/SEG35 bidirectional PORTJ digital I/O RJ3 or LCD segment 35 output.
60 RJ2/SEG34 bidirectional PORTJ digital I/O RJ2 or LCD segment 34 output.
61 RJ1/SEG33 bidirectional PORTJ digital I/O RJ1 or LCD segment 33 output.
62 RJ0 bidirectional PORTJ general purpose digital I/O RJ0 (Schmitt Trigger input).
63 RD7/SEG7/SS2 bidirectional PORTD digital I/O RD7, LCD segment 7 output, or SPI2 slave select input.
64 RD6/SEG6/SCK2/SCL2 bidirectional PORTD digital I/O RD6, LCD segment 6, or SPI/I2C clock for MSSP2.
65 RD5/SEG5/SDI2/SDA2 bidirectional PORTD digital I/O RD5, LCD segment 5, SPI data in, or I2C data for MSSP2.
66 RD4/SEG4/SDO2 bidirectional PORTD digital I/O RD4, LCD segment 4 output, or SPI data out.
67 RD3/SEG3 bidirectional PORTD digital I/O RD3 or LCD segment 3 output.
68 RD2/SEG2 bidirectional PORTD digital I/O RD2 or LCD segment 2 output.
69 RD1/SEG1/T5CKI/T7G bidirectional PORTD digital I/O RD1, LCD segment 1, Timer5 clock input, or Timer7 gate input.
70 VSS power_in Ground reference for logic and I/O pins.
71 VDD power_in Positive supply for logic and I/O pins.
72 RD0/SEG0/CTPLS bidirectional PORTD digital I/O RD0, LCD segment 0 output, or CTMU pulse generator output.
73 RE7/ECCP2/P2A/SEG31 bidirectional PORTE digital I/O RE7, alternate ECCP2 capture/compare/PWM, ECCP2 PWM Output A, or LCD segment 31 output.
74 RE6/COM3/P1B/CCP6 bidirectional PORTE digital I/O RE6, LCD COM3 output, ECCP1 PWM Output B, or CCP6.
75 RE5/COM2/P1C/CCP7 bidirectional PORTE digital I/O RE5, LCD COM2 output, ECCP1 PWM Output C, or CCP7.
76 RE4/COM1/P3B/CCP8 bidirectional PORTE digital I/O RE4, LCD COM1 output, ECCP3 PWM Output B, or CCP8.
77 RE3/COM0/P3C/CCP9/REFO bidirectional PORTE digital I/O RE3, LCD COM0 output, ECCP3 PWM Output C, CCP9, or reference clock output.
78 RE2/LCDBIAS3/P2B/CCP10 bidirectional PORTE digital I/O RE2, LCD BIAS3 input, ECCP2 PWM Output B, or CCP10.
79 RH0/SEG47/AN23 bidirectional PORTH digital I/O RH0, LCD segment 47 output, or analog input 23.
80 RH1/SEG46/AN22 bidirectional PORTH digital I/O RH1, LCD segment 46 output, or analog input 22.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Frequency 0 64 MHz DC, 64 MHz 11
Internal oscillator accuracy (16 MHz clock) -2 16 2 % internal oscillator block 16 MHz clock (±2% accuracy); typ is nominal frequency in MHz 9
VCAP/VDDCORE external capacitor ESR (regulator enabled) ESR 5 Ω low-ESR (< 5Ω) capacitor of 10 µF required on VCAP/VDDCORE when regulator is enabled 37
VCAP/VDDCORE external capacitance 10 µF regulator enabled, capacitor connected to ground 37

CAD (KiCad official)

  • Symbol: PIC18F87K90-I
  • Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
  • 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: pic18f87k90-i-etched.step / pic18f87k90-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic18f87k90-i.step / pic18f87k90-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (570 pp, sha256 fcd95dc4fd3f723d, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF