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PIC18F66K22-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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PIC18F66K22-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)

PIC18F66K22-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RE1/WR/P2C bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port write strobe, ECCP2 PWM output C, and external write control in PSP mode.
2 RE0/RD/P2D bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port read strobe and ECCP2 PWM output D.
3 RG0/ECCP3/P3A bidirectional Digital I/O with Schmitt Trigger input; also Capture 3 input/Compare 3 output/PWM3 output and ECCP3 PWM output A.
4 RG1/TX2/CK2/AN19/C3OUT bidirectional Digital I/O; also EUSART2 asynchronous transmit or synchronous clock, Analog Input 19, and Comparator 3 output.
5 RG2/RX2/DT2/AN18/C3INA bidirectional Digital I/O with Schmitt Trigger input; also EUSART2 asynchronous receive or synchronous data, Analog Input 18, and Comparator 3 Input A.
6 RG3/CCP4/AN17/P3D/C3INB bidirectional Digital I/O; also Capture 4 input/Compare 4 output/PWM4 output, Analog Input 17, ECCP3 PWM output D, and Comparator 3 Input B.
7 MCLR/RG5 input Master Clear input (programming voltage input) that is an active-low Reset to the device; when MCLR is disabled this pin is a general purpose input-only pin (RG5).
8 RG4/RTCC/T7CKI/T5G/CCP5/AN16/P1D/C3INC bidirectional Digital I/O with Schmitt Trigger input; also RTCC output, Timer7 clock input, Timer5 external clock gate input, Capture 5/Compare 5/PWM5 output, Analog Input 16, ECCP1 PWM output D, and Comparator 3 Input C.
9 VSS power_in Ground reference for logic and I/O pins.
10 VDDCORE/VCAP power_in Core logic power (VDDCORE) when the on-chip regulator is disabled, or external filter capacitor connection (VCAP) when the regulator is enabled.
11 RF7/AN5/SS1 bidirectional Digital I/O with Schmitt Trigger input; also Analog Input 5 and SPI1 slave select input.
12 RF6/AN11/C1INA bidirectional Digital I/O with Schmitt Trigger input; also Analog Input 11 and Comparator 1 Input A.
13 RF5/AN10/CVREF/C1INB bidirectional Digital I/O with Schmitt Trigger input; also Analog Input 10, comparator reference voltage output CVREF (enabling it disables digital I/O), and Comparator 1 Input B.
14 RF4/AN9/C2INA bidirectional Digital I/O with Schmitt Trigger input; also Analog Input 9 and Comparator 2 Input A.
15 RF3/AN8/C2INB/CTMUI bidirectional Digital I/O with Schmitt Trigger input; also Analog Input 8, Comparator 2 Input B, and CTMU pulse generator charger for the C2INB input.
16 RF2/AN7/C1OUT bidirectional Digital I/O with Schmitt Trigger input; also Analog Input 7 and Comparator 1 output.
17 RF1/AN6/C2OUT/CTDIN bidirectional Digital I/O with Schmitt Trigger input; also Analog Input 6, Comparator 2 output, and CTMU pulse delay input.
18 ENVREG input Enable for the on-chip voltage regulator; tie to VDD to enable the regulator or to ground to disable it.
19 AVDD power_in Positive supply for analog modules.
20 AVSS power_in Ground reference for analog modules.
21 RA3/AN3/VREF+ bidirectional Digital I/O with TTL input; also Analog Input 3 and A/D reference voltage (high) input.
22 RA2/AN2/VREF- bidirectional Digital I/O with TTL input; also Analog Input 2 and A/D reference voltage (low) input.
23 RA1/AN1 bidirectional Digital I/O with TTL input; also Analog Input 1.
24 RA0/AN0/ULPWU bidirectional Digital I/O with TTL input; also Analog Input 0 and Ultra Low-Power Wake-up input.
25 VSS power_in Ground reference for logic and I/O pins.
26 VDD power_in Positive supply for logic and I/O pins.
27 RA5/AN4/T1CKI/T3G/HLVDIN bidirectional Digital I/O with TTL input; also Analog Input 4, Timer1 clock input, Timer3 external clock gate input, and High/Low-Voltage Detect input.
28 RA4/T0CKI bidirectional Digital I/O with Schmitt Trigger input; also Timer0 external clock input.
29 RC1/SOSCI/ECCP2/P2A bidirectional Digital I/O with Schmitt Trigger input; also SOSC oscillator input, ECCP2 capture/compare/PWM (default assignment when CCP2MX is set), and ECCP2 PWM output A.
30 RC0/SOSCO/SCLKI bidirectional Digital I/O with Schmitt Trigger input; also SOSC oscillator output and digital SOSC clock input (SCLKI).
31 RC6/TX1/CK1 bidirectional Digital I/O with Schmitt Trigger input; also EUSART1 asynchronous transmit or synchronous clock.
32 RC7/RX1/DT1 bidirectional Digital I/O with Schmitt Trigger input; also EUSART1 asynchronous receive or synchronous data.
33 RC2/ECCP1/P1A bidirectional Digital I/O with Schmitt Trigger input; also Capture 1 input/Compare 1 output/PWM1 output and ECCP1 PWM output A.
34 RC3/SCK1/SCL1 bidirectional Digital I/O with Schmitt Trigger input; also MSSP1 SPI clock input/output or I2C clock input/output.
35 RC4/SDI1/SDA1 bidirectional Digital I/O with Schmitt Trigger input; also MSSP1 SPI data input or I2C data I/O.
36 RC5/SDO1 bidirectional Digital I/O with Schmitt Trigger input; also MSSP1 SPI data output.
37 RB7/KBI3/PGD bidirectional Digital I/O with TTL input and weak pull-up; also interrupt-on-change KBI3 and ICSP/ICD serial data pin.
38 VDD power_in Positive supply for logic and I/O pins.
39 OSC1/CLKI/RA7 input Oscillator crystal or external clock input (OSC1/CLKI); pin is general purpose I/O RA7 only in oscillator modes where it is not used as the oscillator input.
40 OSC2/CLKO/RA6 output Oscillator crystal output or clock output (CLKO, FOSC/4); pin is general purpose I/O RA6 only in oscillator modes where it is not used as the oscillator output.
41 VSS power_in Ground reference for logic and I/O pins.
42 RB6/KBI2/PGC bidirectional Digital I/O with TTL input and weak pull-up; also interrupt-on-change KBI2 and ICSP/ICD programming clock pin.
43 RB5/KBI1/T3CKI/T1G bidirectional Digital I/O with TTL input and weak pull-up; also interrupt-on-change KBI1, Timer3 clock input, and Timer1 external clock gate input.
44 RB4/KBI0 bidirectional Digital I/O with TTL input and weak pull-up; also interrupt-on-change KBI0.
45 RB3/INT3/CTED2/ECCP2/P2A bidirectional Digital I/O with TTL input and weak pull-up; also External Interrupt 3, CTMU Edge 2 input, ECCP2 capture/compare/PWM, and ECCP2 PWM output A.
46 RB2/INT2/CTED1 bidirectional Digital I/O with TTL input and weak pull-up; also External Interrupt 2 and CTMU Edge 1 input.
47 RB1/INT1 bidirectional Digital I/O with TTL input and weak pull-up; also External Interrupt 1.
48 RB0/INT0/FLT0 bidirectional Digital I/O with TTL input and weak pull-up; also External Interrupt 0 and Enhanced PWM Fault input for ECCP1/2/3.
49 RD7/PSP7/SS2 bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port data and SPI slave select input for MSSP2.
50 RD6/PSP6/SCK2/SCL2 bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port data, MSSP2 SPI clock input/output, and I2C clock input/output.
51 RD5/PSP5/SDI2/SDA2 bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port data, MSSP2 SPI data input, and I2C data I/O.
52 RD4/PSP4/SDO2 bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port data and MSSP2 SPI data output.
53 RD3/PSP3 bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port data.
54 RD2/PSP2 bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port data.
55 RD1/PSP1/T5CKI/T7G bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port data, Timer5 clock input, and Timer7 external clock gate input.
56 VSS power_in Ground reference for logic and I/O pins.
57 VDD power_in Positive supply for logic and I/O pins.
58 RD0/PSP0/CTPLS bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port data and CTMU pulse generator output.
59 RE7/ECCP2/P2A bidirectional Digital I/O with Schmitt Trigger input; also ECCP2 capture/compare/PWM (alternate assignment when CCP2MX is cleared) and ECCP2 PWM output A.
60 RE6/P1B/CCP6 bidirectional Digital I/O with Schmitt Trigger input; also ECCP1 PWM output B and Capture 6/Compare 6/PWM6 output.
61 RE5/P1C/CCP7 bidirectional Digital I/O with Schmitt Trigger input; also ECCP1 PWM output C and Capture 7/Compare 7/PWM7 output.
62 RE4/P3B/CCP8 bidirectional Digital I/O with Schmitt Trigger input; also ECCP3 PWM output B and Capture 8/Compare 8/PWM8 output.
63 RE3/P3C/CCP9/REFO bidirectional Digital I/O with Schmitt Trigger input; also ECCP3 PWM output C, Capture 9/Compare 9/PWM9 output, and reference clock output REFO.
64 RE2/CS/P2B/CCP10 bidirectional Digital I/O with Schmitt Trigger input; also Parallel Slave Port chip select, ECCP2 PWM output B, and Capture 10/Compare 10/PWM10 output.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital port input tolerance 5.5 V All digital ports; analog ports have the same tolerance (clamping diodes internal) 165
HSPLL/ECPLL oscillator input range 4 16 MHz PLL enabled only when HS or EC oscillator frequency is within this range 51
PLL output frequency 64 MHz HSPLL/ECPLL: four times the external oscillator, up to 64 MHz 51
LP oscillator operating frequency 31.25 100 kHz LP mode design operating frequency 48
HS oscillator operating frequency 4 25 MHz HS mode design operating frequency 48
EC oscillator operating frequency 0 64 MHz EC mode, external clock 48
EXTRC oscillator operating frequency 0 4 MHz EXTRC mode, external RC 48
RC oscillator external resistor REXT REXT 3 100 kΩ RC and RCIO oscillator modes; recommended values 49
RC oscillator external capacitor CEXT CEXT 20 300 pF RC and RCIO oscillator modes; recommended values 49
VCAP/VDDCORE external capacitor 10 µF Required on VCAP/VDDCORE to ground when on-chip voltage regulator is enabled; ceramic or tantalum 39
VCAP/VDDCORE capacitor ESR ESR 5 Ω Low-ESR capacitor (< 5 Ω) required on VCAP/VDDCORE when regulator enabled 39
Flash program memory erase/write cycles 10000 cycles Flash program memory rated for up to 10,000 erase/write cycles (family text) 9

CAD (KiCad official)

  • Symbol: PIC18F66K22-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: pic18f66k22-i-etched.step / pic18f66k22-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic18f66k22-i.step / pic18f66k22-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (550 pp, sha256 64337c8891e746c1, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF