# PIC18F66J55-I

**Microchip Tech** · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)

PIC18F66J55-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RE1/PMWR/P2C | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port write strobe and ECCP2 PWM output C. |
| 2 | RE0/PMRD/P2D | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port read strobe and ECCP2 PWM output D. |
| 3 | RG0/PMA8/ECCP3/P3A | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address, ECCP3 capture/compare and PWM output A. |
| 4 | RG1/PMA7/TX2/CK2 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address and EUSART2 asynchronous transmit or synchronous clock. |
| 5 | RG2/PMA6/RX2/DT2 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address and EUSART2 asynchronous receive or synchronous data. |
| 6 | RG3/PMCS1/CCP4/P3D | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port chip select 1, CCP4 capture/compare/PWM output and ECCP3 PWM output D. |
| 7 | MCLR | input | Master Clear (Reset) input, an active-low Reset to the device with Schmitt Trigger buffer. |
| 8 | RG4/PMCS2/CCP5/P1D | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port chip select 2, CCP5 capture/compare/PWM output and ECCP1 PWM output D. |
| 9 | VSS | power_in | Ground reference for logic and I/O pins. |
| 10 | VDDCORE/VCAP | power_in | Core logic power supply when the regulator is disabled, or external filter capacitor connection when the regulator is enabled. |
| 11 | RF7/SS1/C1OUT | bidirectional | Digital I/O with Schmitt Trigger input, also MSSP1 SPI slave select input and Comparator 1 output. |
| 12 | RF6/AN11/C1INA | bidirectional | Digital I/O with Schmitt Trigger input, also A/D analog input channel 11 and Comparator 1 input A. |
| 13 | RF5/AN10/C1INB/CVREF | bidirectional | Digital I/O with Schmitt Trigger input, also A/D analog input channel 10, Comparator 1 input B and comparator reference voltage output. |
| 14 | RF4/D+ | bidirectional | Digital input with Schmitt Trigger buffer, also USB differential plus line (input/output) of the on-chip transceiver. |
| 15 | RF3/D- | bidirectional | Digital input with Schmitt Trigger buffer, also USB differential minus line (input/output) of the on-chip transceiver. |
| 16 | RF2/PMA5/AN7/C2INB | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address, A/D analog input channel 7 and Comparator 2 input B. |
| 17 | VUSB | power_in | USB voltage input pin. |
| 18 | ENVREG | input | Enable input for the on-chip voltage regulator, with Schmitt Trigger buffer. |
| 19 | AVDD | power_in | Positive supply for analog modules. |
| 20 | AVSS | power_in | Ground reference for analog modules. |
| 21 | RA3/AN3/VREF+ | bidirectional | Digital I/O with TTL input, also A/D analog input channel 3 and A/D high reference voltage input. |
| 22 | RA2/AN2/VREF- | bidirectional | Digital I/O with TTL input, also A/D analog input channel 2 and A/D low reference voltage input. |
| 23 | RA1/AN1 | bidirectional | Digital I/O with TTL input, also A/D analog input channel 1. |
| 24 | RA0/AN0 | bidirectional | Digital I/O with TTL input, also A/D analog input channel 0. |
| 25 | VSS | power_in | Ground reference for logic and I/O pins. |
| 26 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins. |
| 27 | RA5/AN4/C2INA | bidirectional | Digital I/O with TTL input, also A/D analog input channel 4 and Comparator 2 input A. |
| 28 | RA4/T0CKI | bidirectional | Digital I/O with Schmitt Trigger input, also Timer0 external clock input. |
| 29 | RC1/T1OSI/ECCP2/P2A | bidirectional | Digital I/O with Schmitt Trigger input, also Timer1 oscillator input, ECCP2 capture/compare output and ECCP2 PWM output A. |
| 30 | RC0/T1OSO/T13CKI | bidirectional | Digital I/O with Schmitt Trigger input, also Timer1 oscillator output and Timer1/Timer3 external clock input. |
| 31 | RC6/TX1/CK1 | bidirectional | Digital I/O with Schmitt Trigger input, also EUSART1 asynchronous transmit or synchronous clock. |
| 32 | RC7/RX1/DT1 | bidirectional | Digital I/O with Schmitt Trigger input, also EUSART1 asynchronous receive or synchronous data. |
| 33 | RC2/ECCP1/P1A | bidirectional | Digital I/O with Schmitt Trigger input, also ECCP1 capture/compare/PWM output and ECCP1 PWM output A. |
| 34 | RC3/SCK1/SCL1 | bidirectional | Digital I/O with Schmitt Trigger input, also MSSP1 SPI clock or I2C clock input/output. |
| 35 | RC4/SDI1/SDA1 | bidirectional | Digital I/O with Schmitt Trigger input, also MSSP1 SPI data input or I2C data input/output. |
| 36 | RC5/SDO1/C2OUT | bidirectional | Digital I/O with Schmitt Trigger input, also MSSP1 SPI data output and Comparator 2 output. |
| 37 | RB7/KBI3/PGD | bidirectional | Digital I/O with TTL input and weak pull-up, also interrupt-on-change pin and ICSP/ICD serial data pin. |
| 38 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins. |
| 39 | OSC1/CLKI/RA7 | input | Oscillator crystal or external clock input, which is also general purpose I/O when OSC1 is not used for the clock function. |
| 40 | OSC2/CLKO/RA6 | output | Oscillator crystal output or clock output (FOSC/4), which is also general purpose I/O when OSC2 is not used for the clock function. |
| 41 | VSS | power_in | Ground reference for logic and I/O pins. |
| 42 | RB6/KBI2/PGC | bidirectional | Digital I/O with TTL input and weak pull-up, also interrupt-on-change pin and ICSP/ICD serial clock input. |
| 43 | RB5/KBI1/PMA0 | bidirectional | Digital I/O with TTL input and weak pull-up, also interrupt-on-change pin and Parallel Master Port address. |
| 44 | RB4/KBI0/PMA1 | bidirectional | Digital I/O with TTL input and weak pull-up, also interrupt-on-change pin and Parallel Master Port address. |
| 45 | RB3/INT3/PMA2 | bidirectional | Digital I/O with TTL input and weak pull-up, also external interrupt 3 input and Parallel Master Port address. |
| 46 | RB2/INT2/PMA3 | bidirectional | Digital I/O with TTL input and weak pull-up, also external interrupt 2 input and Parallel Master Port address. |
| 47 | RB1/INT1/PMA4 | bidirectional | Digital I/O with TTL input and weak pull-up, also external interrupt 1 input and Parallel Master Port address. |
| 48 | RB0/FLT0/INT0 | bidirectional | Digital I/O with TTL input and weak pull-up, also ECCP1/2/3 Fault input and external interrupt 0 input. |
| 49 | RD7/PMD7/SS2 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port data and MSSP2 SPI slave select input. |
| 50 | RD6/PMD6/SCK2/SCL2 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port data and MSSP2 SPI clock or I2C clock input/output. |
| 51 | RD5/PMD5/SDI2/SDA2 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port data and MSSP2 SPI data input or I2C data input/output. |
| 52 | RD4/PMD4/SDO2 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port data and MSSP2 SPI data output. |
| 53 | RD3/PMD3 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port data. |
| 54 | RD2/PMD2 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port data. |
| 55 | RD1/PMD1 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port data. |
| 56 | VSS | power_in | Ground reference for logic and I/O pins. |
| 57 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins. |
| 58 | RD0/PMD0 | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port data. |
| 59 | RE7/PMA9/ECCP2/P2A | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address, ECCP2 capture/compare output and ECCP2 PWM output A. |
| 60 | RE6/PMA10/P1B | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address and ECCP1 PWM output B. |
| 61 | RE5/PMA11/P1C | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address and ECCP1 PWM output C. |
| 62 | RE4/PMA12/P3B | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address and ECCP3 PWM output B. |
| 63 | RE3/PMA13/P3C/REFO | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port address, ECCP3 PWM output C and reference clock output. |
| 64 | RE2/PMBE/P2B | bidirectional | Digital I/O with Schmitt Trigger input, also Parallel Master Port byte enable and ECCP2 PWM output B. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage Range | VDD | 2 |  | 3.6 | V | Family feature list; not per-variant electrical table | 3 |
| Operating Frequency |  |  |  | 48 | MHz | DC, 48 MHz for PIC18F66J55 (Table 1-1) | 11 |
| Digital-only input tolerance (5.5V tolerant) |  |  |  | 5.5 | V | Digital-only pins (PORTB, PORTC[7:2], PORTD, PORTE, PORTF[7], PORTG[4:0]) tolerate input above VDD; analog-capable pins limited to VDD | 137 |
| VBUS minimum before enabling D+/D- pull-up | VBUS | 1.17 |  |  | V | Monitor VBUS; do not enable USB pull-up until VBUS greater than 1.17 V | 315 |
| High-current sink/source (PORTB and PORTC) |  |  |  | 25 | mA | High-current sink/source 25 mA, PORTB and PORTC | 3 |
| External USB pull-up resistor tolerance |  | -5 |  | 5 | % | 1.5 kΩ pull-up on D+ or D-, as required by USB specification | 315 |
| MCLR pull-up resistor to VDD | MCLR | 1 |  | 10 | kΩ | MCLR tied to VDD through resistor for POR (1 kΩ to 10 kΩ) | 57 |
| External USB pull-up resistor nominal |  |  | 1.5 |  | kΩ | External pull-up on VUSB to D+ or D- | 315 |

## CAD (KiCad official)

- Symbol: `PIC18F66J55-I`
- Footprint: `Package_QFP:TQFP-64_10x10mm_P0.5mm`
- 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `pic18f66j55-i-etched.step` / `pic18f66j55-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic18f66j55-i.step` / `pic18f66j55-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/39775c.pdf) (480 pp, sha256 `88bc899e2743258d`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pic18f66j55-i-datasheet.pdf)