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PIC18F65K80-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC18F65K80-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)

PIC18F65K80-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RC7/CCP4 bidirectional General-purpose digital I/O RC7 that can also serve as CCP4 capture input or compare/PWM output.
2 RD4/ECCP1/P1A/PSP4 bidirectional General-purpose digital I/O RD4 that can also serve as ECCP1 capture/compare/PWM output, Enhanced PWM output P1A, or Parallel Slave Port data bit 4.
3 RD5/P1B/PSP5 bidirectional General-purpose digital I/O RD5 that can also serve as Enhanced PWM output P1B or Parallel Slave Port data bit 5.
4 RD6/P1C/PSP6 bidirectional General-purpose digital I/O RD6 that can also serve as Enhanced PWM output P1C or Parallel Slave Port data bit 6.
5 RD7/P1D/PSP7 bidirectional General-purpose digital I/O RD7 that can also serve as Enhanced PWM output P1D or Parallel Slave Port data bit 7.
6 RG0/RX1/DT1 bidirectional General-purpose digital I/O RG0 that can also serve as EUSART1 asynchronous receive input or synchronous data pin.
7 RG1/CANTX2 bidirectional General-purpose digital I/O RG1 that can also serve as the CAN bus complementary transmit output or CAN bus time clock.
8 VSS power_in Ground reference for logic and I/O pins.
9 AVDD power_in Positive supply for analog modules.
10 VDD power_in Positive supply for logic and I/O pins.
11 RG2/T3CKI bidirectional General-purpose digital I/O RG2 that can also serve as Timer3 clock input.
12 RG3/TX1/CK1 bidirectional General-purpose digital I/O RG3 that can also serve as EUSART1 asynchronous transmit or synchronous clock pin.
13 RB0/AN10/FLT0/INT0 bidirectional General-purpose digital I/O RB0 with weak pull-up, also serving as analog input AN10, ECCP Enhanced PWM Fault input FLT0, and external interrupt INT0.
14 RB1/AN8/CTDIN/INT1 bidirectional General-purpose digital I/O RB1 with weak pull-up, also serving as analog input AN8, CTMU pulse delay input CTDIN, and external interrupt INT1.
15 RB2/CANTX/CTED1/INT2 bidirectional General-purpose digital I/O RB2 with weak pull-up, also serving as CAN bus TX output, CTMU Edge 1 input, and external interrupt INT2.
16 RB3/CANRX/CTED2/INT3 bidirectional General-purpose digital I/O RB3 with weak pull-up, also serving as CAN bus RX input, CTMU Edge 2 input, and external interrupt INT3.
17 RF0/MDMIN bidirectional General-purpose digital I/O RF0 with weak pull-up, also serving as Data Signal Modulator source input MDMIN.
18 RG4/T0CKI bidirectional General-purpose digital I/O RG4 that can also serve as Timer0 external clock input.
19 RF1 bidirectional General-purpose digital I/O RF1 with weak pull-up.
20 RB4/AN9/CTPLS/KBI0 bidirectional General-purpose digital I/O RB4 with weak pull-up, also serving as analog input AN9, CTMU pulse generator output CTPLS, and interrupt-on-change KBI0.
21 RB5/T0CKI/T3CKI/CCP5/KBI1 bidirectional General-purpose digital I/O RB5 with weak pull-up, also serving as Timer0/Timer3 clock input, CCP5 capture/compare/PWM, and interrupt-on-change KBI1.
22 RB6/PGC/KBI2 bidirectional General-purpose digital I/O RB6 with weak pull-up, also serving as In-Circuit Debugger and ICSP programming clock PGC and interrupt-on-change KBI2.
23 RB7/PGD/T3G/KBI3 bidirectional General-purpose digital I/O RB7 with weak pull-up, also serving as In-Circuit Debugger and ICSP programming data PGD, Timer3 gate input T3G, and interrupt-on-change KBI3.
24 RE5/CANTX bidirectional General-purpose digital I/O RE5 that can also serve as the alternate CAN bus TX output when CANMX is cleared.
25 VDD power_in Positive supply for logic and I/O pins.
26 VSS power_in Ground reference for logic and I/O pins.
27 RE4/CANRX bidirectional General-purpose digital I/O RE4 that can also serve as the alternate CAN bus RX input when CANMX is cleared.
28 MCLR/RE3 input Master Clear input or programming voltage input that acts as an active-low Reset to the device; the same pin is also the general-purpose input-only pin RE3 when MCLR is disabled.
29 RA0/CVREF/AN0/ULPWU bidirectional General-purpose digital I/O RA0 that can also serve as comparator voltage reference output CVREF, analog input AN0, or Ultra Low-Power Wake-up input ULPWU.
30 RA1/AN1/C1INC bidirectional Digital I/O RA1 that can also serve as analog input AN1 or Comparator 1 Input C.
31 RA2/VREF-/AN2/C2INC bidirectional Digital I/O RA2 that can also serve as A/D reference voltage (low) input VREF-, analog input AN2, or Comparator 2 Input C.
32 RA3/VREF+/AN3 bidirectional Digital I/O RA3 that can also serve as A/D reference voltage (high) input VREF+ or analog input AN3.
33 VDDCORE/VCAP power_out External filter capacitor connection for the on-chip voltage regulator output (VDDCORE) or, when the regulator is disabled, a supply connection at the VDDCORE level.
34 RA5/AN4/HLVDIN/T1CKI/SS bidirectional Digital I/O RA5 that can also serve as analog input AN4, High/Low-Voltage Detect input HLVDIN, Timer1 clock input T1CKI, or SPI slave select SS.
35 RF2/MDCIN1 bidirectional General-purpose digital I/O RF2 with weak pull-up that can also serve as Data Signal Modulator Carrier Input 1.
36 RF3 bidirectional General-purpose digital I/O RF3 with weak pull-up.
37 RE0/AN5/RD bidirectional General-purpose digital I/O RE0 that can also serve as analog input AN5 or Parallel Slave Port read strobe RD.
38 RE1/AN6/C1OUT/WR bidirectional General-purpose digital I/O RE1 that can also serve as analog input AN6, Comparator 1 output C1OUT, or Parallel Slave Port write strobe WR.
39 RE2/AN7/C2OUT/CS bidirectional General-purpose digital I/O RE2 that can also serve as analog input AN7, Comparator 2 output C2OUT, or Parallel Slave Port chip select CS.
40 AVDD power_in Positive supply for analog modules.
41 VDD power_in Positive supply for logic and I/O pins.
42 AVSS power_in Ground reference for analog modules.
43 VSS power_in Ground reference for logic and I/O pins.
44 RF4/MDCIN2 bidirectional General-purpose digital I/O RF4 with weak pull-up that can also serve as Data Signal Modulator Carrier Input 2.
45 RF5 bidirectional General-purpose digital I/O RF5 with weak pull-up.
46 OSC1/CLKIN/RA7 bidirectional Oscillator crystal or external clock input OSC1/CLKIN, which becomes general-purpose digital I/O RA7 in oscillator modes where OSC1 is not used.
47 OSC2/CLKOUT/RA6 bidirectional Oscillator crystal output OSC2 or clock output CLKOUT (FOSC/4), which becomes general-purpose digital I/O RA6 in oscillator modes where OSC2 is not used.
48 RC0/SOSCO/SCLKI bidirectional General-purpose digital I/O RC0 that can also serve as Timer1 oscillator output SOSCO or digital SOSC clock input SCLKI.
49 RC1/SOSCI bidirectional General-purpose digital I/O RC1 that can also serve as SOSC oscillator input SOSCI.
50 RC2/T1G/CCP2 bidirectional General-purpose digital I/O RC2 that can also serve as Timer1 gate input T1G or CCP2 capture/compare/PWM.
51 RC3/REFO/SCL/SCK bidirectional General-purpose digital I/O RC3 that can also serve as reference clock output REFO, MSSP I2C clock SCL, or SPI clock SCK.
52 RF6/MDOUT bidirectional General-purpose digital I/O RF6 with weak pull-up that can also serve as Data Signal Modulator output MDOUT.
53 RF7 bidirectional General-purpose digital I/O RF7 with weak pull-up.
54 RD0/C1INA/PSP0 bidirectional General-purpose digital I/O RD0 that can also serve as Comparator 1 Input A or Parallel Slave Port data bit 0.
55 RD1/C1INB/PSP1 bidirectional General-purpose digital I/O RD1 that can also serve as Comparator 1 Input B or Parallel Slave Port data bit 1.
56 VSS power_in Ground reference for logic and I/O pins.
57 VDD power_in Positive supply for logic and I/O pins.
58 RD2/C2INA/PSP2 bidirectional General-purpose digital I/O RD2 that can also serve as Comparator 2 Input A or Parallel Slave Port data bit 2.
59 RD3/C2INB/CTMUI/PSP3 bidirectional General-purpose digital I/O RD3 that can also serve as Comparator 2 Input B, CTMU pulse generator charger CTMUI, or Parallel Slave Port data bit 3.
60 RE6/RX2/DT2 bidirectional General-purpose digital I/O RE6 that can also serve as EUSART2 asynchronous receive RX2 or synchronous data DT2.
61 RE7/TX2/CK2 bidirectional General-purpose digital I/O RE7 that can also serve as EUSART2 asynchronous transmit TX2 or synchronous clock CK2.
62 RC4/SDA/SDI bidirectional General-purpose digital I/O RC4 that can also serve as MSSP I2C data SDA or SPI data input SDI.
63 RC5/SDO bidirectional General-purpose digital I/O RC5 that can also serve as MSSP SPI data output SDO.
64 RC6/CCP3 bidirectional General-purpose digital I/O RC6 that can also serve as CCP3 capture/compare/PWM input or output.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating voltage range (family feature summary) 1.8 5.5 V 1
Operating speed (family feature summary) 64 MHz 1
HF-INTOSC 16 MHz clock accuracy -2 2 % 10
VCAP/VDDCORE external capacitor (regulator enabled) 10 µF regulator enabled; connected to ground 45
VCAP/VDDCORE capacitor ESR (regulator enabled) ESR 5 Ω regulator enabled; low-ESR capacitor required 45

CAD (KiCad official)

  • Symbol: PIC18F65K80-I
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: pic18f65k80-i-etched.step / pic18f65k80-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic18f65k80-i.step / pic18f65k80-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (598 pp, sha256 95222cf15424a99c, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF