component
PIC18F46K20-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
PIC18F46K20-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)
PIC18F46K20-I from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC7/RX/DT | bidirectional | Digital I/O with Schmitt Trigger input; EUSART asynchronous receive input (RX) or synchronous data I/O (DT). |
| 2 | RD4/PSP4 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 4 (PSP4). |
| 3 | RD5/PSP5/P1B | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 5 or ECCP1 Enhanced PWM output channel B (P1B). |
| 4 | RD6/PSP6/P1C | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 6 or ECCP1 Enhanced PWM output channel C (P1C). |
| 5 | RD7/PSP7/P1D | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 7 or ECCP1 Enhanced PWM output channel D (P1D). |
| 6 | VSS | power_in | Ground reference for logic and I/O pins. |
| 7 | VDD | power_in | Positive supply for logic and I/O pins. |
| 8 | RB0/INT0/FLT0/AN12 | bidirectional | Digital I/O with programmable weak pull-up; external interrupt 0 (INT0), ECCP1 PWM Fault input (FLT0), or ADC analog input channel 12. |
| 9 | RB1/INT1/AN10/C12IN3- | bidirectional | Digital I/O with programmable weak pull-up; external interrupt 1 (INT1), ADC analog input channel 10, or comparator C1/C2 inverting input channel 3. |
| 10 | RB2/INT2/AN8 | bidirectional | Digital I/O with programmable weak pull-up; external interrupt 2 (INT2) or ADC analog input channel 8. |
| 11 | RB3/AN9/C12IN2-/CCP2 | bidirectional | Digital I/O with programmable weak pull-up; ADC analog input channel 9, comparator C1/C2 inverting input channel 2, or CCP2 capture/compare/PWM (alternate pin when CCP2MX is cleared). |
| 12 | NC | unconnected | No connect. |
| 13 | NC | unconnected | No connect. |
| 14 | RB4/KBI0/AN11 | bidirectional | Digital I/O with programmable weak pull-up; interrupt-on-pin-change KBI0 or ADC analog input channel 11. |
| 15 | RB5/KBI1/PGM | bidirectional | Digital I/O with programmable weak pull-up; interrupt-on-pin-change KBI1 or low-voltage ICSP programming enable (PGM). |
| 16 | RB6/KBI2/PGC | bidirectional | Digital I/O with programmable weak pull-up; interrupt-on-pin-change KBI2 or in-circuit debugger and ICSP programming clock (PGC). |
| 17 | RB7/KBI3/PGD | bidirectional | Digital I/O with programmable weak pull-up; interrupt-on-pin-change KBI3 or in-circuit debugger and ICSP programming data (PGD). |
| 18 | MCLR/VPP/RE3 | input | Active-low Master Clear (device Reset) input when MCLRE is enabled, programming voltage input (VPP), or digital input RE3 when MCLR is disabled. |
| 19 | RA0/AN0/C12IN0- | bidirectional | Digital I/O (TTL input); ADC analog input channel 0 or comparator C1/C2 inverting input channel 0. |
| 20 | RA1/AN1/C12IN0- | bidirectional | Digital I/O (TTL input); ADC analog input channel 1 or comparator C1/C2 inverting input (printed as C12IN0- in the 40/44-pin table). |
| 21 | RA2/AN2/VREF-/CVREF/C2IN+ | bidirectional | Digital I/O (TTL input); ADC analog input channel 2, A/D reference voltage (low) input VREF-, comparator reference voltage output CVREF, or comparator C2 non-inverting input. |
| 22 | RA3/AN3/VREF+/C1IN+ | bidirectional | Digital I/O (TTL input); ADC analog input channel 3, A/D reference voltage (high) input VREF+, or comparator C1 non-inverting input. |
| 23 | RA4/T0CKI/C1OUT | bidirectional | Digital I/O with Schmitt Trigger input; Timer0 external clock input (T0CKI) or comparator C1 output. |
| 24 | RA5/AN4/SS/HLVDIN/C2OUT | bidirectional | Digital I/O (TTL input); ADC analog input channel 4, SPI slave select input (SS), high/low-voltage detect input (HLVDIN), or comparator C2 output. |
| 25 | RE0/RD/AN5 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port read control (RD) or ADC analog input channel 5. |
| 26 | RE1/WR/AN6 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port write control (WR) or ADC analog input channel 6. |
| 27 | RE2/CS/AN7 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port chip select (CS) or ADC analog input channel 7. |
| 28 | VDD | power_in | Positive supply for logic and I/O pins. |
| 29 | VSS | power_in | Ground reference for logic and I/O pins. |
| 30 | OSC1/CLKIN/RA7 | bidirectional | Oscillator crystal or external clock input (OSC1/CLKIN) in oscillator modes; otherwise general purpose I/O RA7. |
| 31 | OSC2/CLKOUT/RA6 | bidirectional | Oscillator crystal output (OSC2) or CLKOUT at FOSC/4 in RC mode; otherwise general purpose I/O RA6. |
| 32 | RC0/T1OSO/T13CKI | bidirectional | Digital I/O with Schmitt Trigger input; Timer1 oscillator output (T1OSO) or Timer1/Timer3 external clock input (T13CKI). |
| 33 | NC | unconnected | No connect. |
| 34 | NC | unconnected | No connect. |
| 35 | RC1/T1OSI/CCP2 | bidirectional | Digital I/O with Schmitt Trigger input; Timer1 oscillator input (T1OSI) or CCP2 capture/compare/PWM (default CCP2 pin when CCP2MX is set). |
| 36 | RC2/CCP1/P1A | bidirectional | Digital I/O with Schmitt Trigger input; ECCP1 capture/compare input/output or Enhanced PWM output channel A (P1A). |
| 37 | RC3/SCK/SCL | bidirectional | Digital I/O with Schmitt Trigger input; MSSP synchronous serial clock input/output for SPI (SCK) or I2C (SCL) mode. |
| 38 | RD0/PSP0 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 0 (TTL input when PSP is enabled). |
| 39 | RD1/PSP1 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 1 (TTL input when PSP is enabled). |
| 40 | RD2/PSP2 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 2 (TTL input when PSP is enabled). |
| 41 | RD3/PSP3 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 3 (TTL input when PSP is enabled). |
| 42 | RC4/SDI/SDA | bidirectional | Digital I/O with Schmitt Trigger input; MSSP SPI data input (SDI) or I2C data I/O (SDA). |
| 43 | RC5/SDO | bidirectional | Digital I/O with Schmitt Trigger input; MSSP SPI data output (SDO). |
| 44 | RC6/TX/CK | bidirectional | Digital I/O with Schmitt Trigger input; EUSART asynchronous transmit output (TX) or synchronous clock I/O (CK). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias | -40 | 125 | °C | Under bias | 350 | ||
| Storage temperature | -65 | 150 | °C | 350 | |||
| Voltage on pins with respect to VSS (except VDD and MCLR) | -0.3 | V | Except VDD and MCLR; upper limit printed as (VDD + 0.3V) | 350 | |||
| Voltage on VDD pin with respect to VSS | VDD | -0.3 | 4.5 | V | 350 | ||
| Voltage on MCLR with respect to VSS | MCLR | 0 | 11 | V | 350 | ||
| Total power dissipation | 1 | W | 350 | ||||
| Maximum current out of VSS pin | 350 | mA | -40°C to +85°C for industrial | 350 | |||
| Maximum current into VDD pin (PIC18F4XK20) | 350 | mA | -40°C to +85°C for industrial | 350 | |||
| Input clamp current | IIK | 20 | mA | VI < 0 or VI > VDD | 350 | ||
| Maximum output current sunk by any I/O pin | 50 | mA | 350 | ||||
| Maximum output current sourced by any I/O pin | 50 | mA | 350 | ||||
| VDDMIN (Fosc <= 16 MHz) | VDDMIN | 1.8 | V | Fosc <= 16 MHz | 351 | ||
| VDDMIN (Fosc <= 20 MHz) | VDDMIN | 2 | V | Fosc <= 20 MHz | 351 | ||
| VDDMIN (Fosc <= 64 MHz, Industrial Temperature) | VDDMIN | 3 | V | Fosc <= 64 MHz, industrial temperature | 351 | ||
| VDDMAX | VDDMAX | 3.6 | V | 351 | |||
| TA_MIN operating ambient temperature (industrial) | TA_MIN | -40 | °C | Industrial temperature | 351 | ||
| TA_MAX operating ambient temperature (industrial) | TA_MAX | 85 | °C | Industrial temperature | 351 | ||
| Supply Voltage (D001) | VDD | 1.8 | 3.6 | V | 353 | ||
| RAM Data Retention Voltage (D002) | VDR | 1.5 | V | 353 | |||
| VDD Start Voltage to ensure internal Power-on Reset signal (D003) | VPOR | 0.7 | V | See section on Power-on Reset for details | 353 | ||
| VDD Rise Rate to ensure internal Power-on Reset signal (D004) | SVDD | 0.05 | V/ms | See section on Power-on Reset for details | 353 | ||
| Brown-out Reset Voltage (D005) | VBOR | 1.72 | 1.82 | 1.95 | V | BORV<1:0> = 11 | 353 |
| Brown-out Reset Voltage (D005) | VBOR | 2.15 | 2.27 | 2.4 | V | BORV<1:0> = 10 | 353 |
| Brown-out Reset Voltage (D005) | VBOR | 2.65 | 2.75 | 2.9 | V | BORV<1:0> = 01 | 353 |
| Brown-out Reset Voltage (D005) | VBOR | 2.98 | 3.08 | 3.25 | V | BORV<1:0> = 00 | 353 |
| Power-down Current (IPD) D006 | IPD | 0.05 | 1 | µA | -40°C; VDD = 1.8V, Sleep mode | 353 | |
| Power-down Current (IPD) D006 | IPD | 0.6 | 3 | µA | +85°C; VDD = 1.8V, Sleep mode | 353 | |
| Power-down Current (IPD) D007 | IPD | 0.1 | 1 | µA | -40°C; VDD = 3.0V, Sleep mode | 353 | |
| Power-down Current (IPD) D007 | IPD | 0.7 | 3 | µA | +85°C; VDD = 3.0V, Sleep mode | 353 | |
| Supply Current (IDD) RC_IDLE, LFINTOSC 31 kHz (D011A) | IDD | 3.5 | 8 | µA | -40°C; VDD = 3.0V, FOSC = 31 kHz (RC_IDLE, LFINTOSC) | 355 | |
| Supply Current (IDD) RC_IDLE, LFINTOSC 31 kHz (D011A) | IDD | 4 | 12 | µA | +85°C; VDD = 3.0V, FOSC = 31 kHz (RC_IDLE, LFINTOSC) | 355 | |
| Supply Current (IDD) RC_IDLE, HF-INTOSC 1 MHz (D012) | IDD | 0.3 | 0.4 | mA | -40°C to +125°C; VDD = 1.8V, FOSC = 1 MHz (RC_IDLE, HF-INTOSC) | 355 | |
| Supply Current (IDD) RC_IDLE, HF-INTOSC 1 MHz (D012A) | IDD | 0.4 | 0.6 | mA | -40°C to +125°C; VDD = 3.0V (RC_IDLE, HF-INTOSC) | 355 | |
| Supply Current (IDD) RC_IDLE, HF-INTOSC 16 MHz (D013) | IDD | 1 | 1.2 | mA | -40°C to +125°C; VDD = 1.8V, FOSC = 16 MHz (RC_IDLE, HF-INTOSC) | 355 | |
| Supply Current (IDD) RC_IDLE, HF-INTOSC 16 MHz (D013A) | IDD | 1.6 | 2 | mA | -40°C to +125°C; VDD = 3.0V (RC_IDLE, HF-INTOSC) | 355 | |
| Supply Current (IDD) PRI_RUN 1 MHz EC (D014A) | IDD | 0.5 | 0.75 | mA | -40°C to +125°C; VDD = 3.0V (PRI_RUN, EC oscillator) | 356 | |
| Supply Current (IDD) PRI_RUN 20 MHz EC (D015A) | IDD | 4.3 | 5 | mA | -40°C to +125°C; VDD = 3.0V (PRI_RUN, EC oscillator) | 356 | |
| Supply Current (IDD) PRI_RUN 64 MHz EC (D016) | IDD | 12.2 | 14 | mA | -40°C to +85°C; VDD = 3.0V, FOSC = 64 MHz (PRI_RUN, EC oscillator) | 356 | |
| Supply Current (IDD) PRI_RUN 16 MHz internal HS+PLL (D017A) | IDD | 4.2 | 5 | mA | -40°C to +125°C; VDD = 3.0V (PRI_RUN, HS+PLL, 16 MHz internal) | 356 | |
| Supply Current (IDD) PRI_RUN 64 MHz internal HS+PLL (D018) | IDD | 12.2 | 15 | mA | -40°C to +85°C; VDD = 3.0V, FOSC = 16 MHz, 64 MHz internal (PRI_RUN, HS+PLL) | 356 | |
| Supply Current (IDD) PRI_IDLE 1 MHz EC (D019A) | IDD | 0.09 | 0.15 | mA | -40°C to +125°C; VDD = 3.0V (PRI_IDLE, EC oscillator) | 356 | |
| Supply Current (IDD) PRI_IDLE 20 MHz EC (D020A) | IDD | 1.8 | 2.5 | mA | -40°C to +125°C; VDD = 3.0V (PRI_IDLE, EC oscillator) | 356 | |
| Supply Current (IDD) PRI_IDLE 64 MHz EC (D021) | IDD | 5.6 | 7 | mA | -40°C to +85°C; VDD = 3.0V, FOSC = 64 MHz (PRI_IDLE, EC oscillator) | 356 | |
| Secondary oscillator supply current SEC_RUN (D022A) | IDD | 10 | 15 | µA | -40°C; VDD = 3.0V (SEC_RUN, Timer1 as clock) | 357 | |
| Secondary oscillator supply current SEC_RUN (D022A) | IDD | 10 | 16 | µA | +25°C; VDD = 3.0V (SEC_RUN, Timer1 as clock) | 357 | |
| Secondary oscillator supply current SEC_RUN (D022A) | IDD | 11 | 20 | µA | +85°C; VDD = 3.0V (SEC_RUN, Timer1 as clock) | 357 | |
| RC_RUN supply current HF-INTOSC 31 kHz LFINTOSC (D008A) | IDD | 10 | 15 | µA | -40°C; VDD = 3.0V (RC_RUN, LFINTOSC) | 354 | |
| RC_RUN supply current HF-INTOSC 31 kHz LFINTOSC (D008A) | IDD | 10.5 | 16 | µA | +25°C; VDD = 3.0V (RC_RUN, LFINTOSC) | 354 | |
| RC_RUN supply current HF-INTOSC 31 kHz LFINTOSC (D008A) | IDD | 11 | 20 | µA | +85°C; VDD = 3.0V (RC_RUN, LFINTOSC) | 354 | |
| Supply Current (IDD) RC_RUN HF-INTOSC 1 MHz (D009A) | IDD | 0.6 | 0.8 | mA | -40°C to +125°C; VDD = 3.0V (RC_RUN, HF-INTOSC) | 354 | |
| Supply Current (IDD) RC_RUN HF-INTOSC 16 MHz (D010A) | IDD | 3.8 | 4.4 | mA | -40°C to +125°C; VDD = 3.0V (RC_RUN, HF-INTOSC) | 354 | |
| Supply Current (IDD) RC_RUN HF-INTOSC 1 MHz (D009) | IDD | 0.4 | 0.5 | mA | -40°C to +125°C; VDD = 1.8V, FOSC = 1 MHz (RC_RUN, HF-INTOSC) | 354 | |
| Supply Current (IDD) RC_RUN HF-INTOSC 16 MHz (D010) | IDD | 2.2 | 3 | mA | -40°C to +125°C; VDD = 1.8V, FOSC = 16 MHz (RC_RUN, HF-INTOSC) | 354 | |
| Output Low Voltage I/O ports (D080) | VOL | 0.6 | V | IOL = 8.5 mA, VDD = 3.0V, -40°C to +85°C | 361 | ||
| Capacitive loading OSC2 pin (D100) | COSC2 | 15 | pF | In XT, HS and LP modes when external clock is used to drive OSC1 | 361 | ||
| Capacitive loading all I/O pins and OSC2 in RC mode (D101) | CIO | 50 | pF | To meet the AC Timing Specifications | 361 | ||
| Capacitive loading SCL, SDA (D102) | CB | 400 | pF | I2C Specification | 361 |
CAD (KiCad official)
- Symbol:
PIC18F46K20-I - Footprint:
Package_QFP:TQFP-44_10x10mm_P0.8mm - 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
pic18f46k20-i-etched.step/pic18f46k20-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic18f46k20-i.step/pic18f46k20-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (440 pp, sha256
4e7e234c713a2325, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PIC18F46K20-I
**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)
PIC18F46K20-I from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC7/RX/DT | bidirectional | Digital I/O with Schmitt Trigger input; EUSART asynchronous receive input (RX) or synchronous data I/O (DT). |
| 2 | RD4/PSP4 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 4 (PSP4). |
| 3 | RD5/PSP5/P1B | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 5 or ECCP1 Enhanced PWM output channel B (P1B). |
| 4 | RD6/PSP6/P1C | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 6 or ECCP1 Enhanced PWM output channel C (P1C). |
| 5 | RD7/PSP7/P1D | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 7 or ECCP1 Enhanced PWM output channel D (P1D). |
| 6 | VSS | power_in | Ground reference for logic and I/O pins. |
| 7 | VDD | power_in | Positive supply for logic and I/O pins. |
| 8 | RB0/INT0/FLT0/AN12 | bidirectional | Digital I/O with programmable weak pull-up; external interrupt 0 (INT0), ECCP1 PWM Fault input (FLT0), or ADC analog input channel 12. |
| 9 | RB1/INT1/AN10/C12IN3- | bidirectional | Digital I/O with programmable weak pull-up; external interrupt 1 (INT1), ADC analog input channel 10, or comparator C1/C2 inverting input channel 3. |
| 10 | RB2/INT2/AN8 | bidirectional | Digital I/O with programmable weak pull-up; external interrupt 2 (INT2) or ADC analog input channel 8. |
| 11 | RB3/AN9/C12IN2-/CCP2 | bidirectional | Digital I/O with programmable weak pull-up; ADC analog input channel 9, comparator C1/C2 inverting input channel 2, or CCP2 capture/compare/PWM (alternate pin when CCP2MX is cleared). |
| 12 | NC | unconnected | No connect. |
| 13 | NC | unconnected | No connect. |
| 14 | RB4/KBI0/AN11 | bidirectional | Digital I/O with programmable weak pull-up; interrupt-on-pin-change KBI0 or ADC analog input channel 11. |
| 15 | RB5/KBI1/PGM | bidirectional | Digital I/O with programmable weak pull-up; interrupt-on-pin-change KBI1 or low-voltage ICSP programming enable (PGM). |
| 16 | RB6/KBI2/PGC | bidirectional | Digital I/O with programmable weak pull-up; interrupt-on-pin-change KBI2 or in-circuit debugger and ICSP programming clock (PGC). |
| 17 | RB7/KBI3/PGD | bidirectional | Digital I/O with programmable weak pull-up; interrupt-on-pin-change KBI3 or in-circuit debugger and ICSP programming data (PGD). |
| 18 | MCLR/VPP/RE3 | input | Active-low Master Clear (device Reset) input when MCLRE is enabled, programming voltage input (VPP), or digital input RE3 when MCLR is disabled. |
| 19 | RA0/AN0/C12IN0- | bidirectional | Digital I/O (TTL input); ADC analog input channel 0 or comparator C1/C2 inverting input channel 0. |
| 20 | RA1/AN1/C12IN0- | bidirectional | Digital I/O (TTL input); ADC analog input channel 1 or comparator C1/C2 inverting input (printed as C12IN0- in the 40/44-pin table). |
| 21 | RA2/AN2/VREF-/CVREF/C2IN+ | bidirectional | Digital I/O (TTL input); ADC analog input channel 2, A/D reference voltage (low) input VREF-, comparator reference voltage output CVREF, or comparator C2 non-inverting input. |
| 22 | RA3/AN3/VREF+/C1IN+ | bidirectional | Digital I/O (TTL input); ADC analog input channel 3, A/D reference voltage (high) input VREF+, or comparator C1 non-inverting input. |
| 23 | RA4/T0CKI/C1OUT | bidirectional | Digital I/O with Schmitt Trigger input; Timer0 external clock input (T0CKI) or comparator C1 output. |
| 24 | RA5/AN4/SS/HLVDIN/C2OUT | bidirectional | Digital I/O (TTL input); ADC analog input channel 4, SPI slave select input (SS), high/low-voltage detect input (HLVDIN), or comparator C2 output. |
| 25 | RE0/RD/AN5 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port read control (RD) or ADC analog input channel 5. |
| 26 | RE1/WR/AN6 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port write control (WR) or ADC analog input channel 6. |
| 27 | RE2/CS/AN7 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port chip select (CS) or ADC analog input channel 7. |
| 28 | VDD | power_in | Positive supply for logic and I/O pins. |
| 29 | VSS | power_in | Ground reference for logic and I/O pins. |
| 30 | OSC1/CLKIN/RA7 | bidirectional | Oscillator crystal or external clock input (OSC1/CLKIN) in oscillator modes; otherwise general purpose I/O RA7. |
| 31 | OSC2/CLKOUT/RA6 | bidirectional | Oscillator crystal output (OSC2) or CLKOUT at FOSC/4 in RC mode; otherwise general purpose I/O RA6. |
| 32 | RC0/T1OSO/T13CKI | bidirectional | Digital I/O with Schmitt Trigger input; Timer1 oscillator output (T1OSO) or Timer1/Timer3 external clock input (T13CKI). |
| 33 | NC | unconnected | No connect. |
| 34 | NC | unconnected | No connect. |
| 35 | RC1/T1OSI/CCP2 | bidirectional | Digital I/O with Schmitt Trigger input; Timer1 oscillator input (T1OSI) or CCP2 capture/compare/PWM (default CCP2 pin when CCP2MX is set). |
| 36 | RC2/CCP1/P1A | bidirectional | Digital I/O with Schmitt Trigger input; ECCP1 capture/compare input/output or Enhanced PWM output channel A (P1A). |
| 37 | RC3/SCK/SCL | bidirectional | Digital I/O with Schmitt Trigger input; MSSP synchronous serial clock input/output for SPI (SCK) or I2C (SCL) mode. |
| 38 | RD0/PSP0 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 0 (TTL input when PSP is enabled). |
| 39 | RD1/PSP1 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 1 (TTL input when PSP is enabled). |
| 40 | RD2/PSP2 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 2 (TTL input when PSP is enabled). |
| 41 | RD3/PSP3 | bidirectional | Digital I/O with Schmitt Trigger input; Parallel Slave Port data bit 3 (TTL input when PSP is enabled). |
| 42 | RC4/SDI/SDA | bidirectional | Digital I/O with Schmitt Trigger input; MSSP SPI data input (SDI) or I2C data I/O (SDA). |
| 43 | RC5/SDO | bidirectional | Digital I/O with Schmitt Trigger input; MSSP SPI data output (SDO). |
| 44 | RC6/TX/CK | bidirectional | Digital I/O with Schmitt Trigger input; EUSART asynchronous transmit output (TX) or synchronous clock I/O (CK). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias | | -40 | | 125 | °C | Under bias | 350 |
| Storage temperature | | -65 | | 150 | °C | | 350 |
| Voltage on pins with respect to VSS (except VDD and MCLR) | | -0.3 | | | V | Except VDD and MCLR; upper limit printed as (VDD + 0.3V) | 350 |
| Voltage on VDD pin with respect to VSS | VDD | -0.3 | | 4.5 | V | | 350 |
| Voltage on MCLR with respect to VSS | MCLR | 0 | | 11 | V | | 350 |
| Total power dissipation | | | | 1 | W | | 350 |
| Maximum current out of VSS pin | | | | 350 | mA | -40°C to +85°C for industrial | 350 |
| Maximum current into VDD pin (PIC18F4XK20) | | | | 350 | mA | -40°C to +85°C for industrial | 350 |
| Input clamp current | IIK | | | 20 | mA | VI < 0 or VI > VDD | 350 |
| Maximum output current sunk by any I/O pin | | | | 50 | mA | | 350 |
| Maximum output current sourced by any I/O pin | | | | 50 | mA | | 350 |
| VDDMIN (Fosc <= 16 MHz) | VDDMIN | 1.8 | | | V | Fosc <= 16 MHz | 351 |
| VDDMIN (Fosc <= 20 MHz) | VDDMIN | 2 | | | V | Fosc <= 20 MHz | 351 |
| VDDMIN (Fosc <= 64 MHz, Industrial Temperature) | VDDMIN | 3 | | | V | Fosc <= 64 MHz, industrial temperature | 351 |
| VDDMAX | VDDMAX | | | 3.6 | V | | 351 |
| TA_MIN operating ambient temperature (industrial) | TA_MIN | -40 | | | °C | Industrial temperature | 351 |
| TA_MAX operating ambient temperature (industrial) | TA_MAX | | | 85 | °C | Industrial temperature | 351 |
| Supply Voltage (D001) | VDD | 1.8 | | 3.6 | V | | 353 |
| RAM Data Retention Voltage (D002) | VDR | 1.5 | | | V | | 353 |
| VDD Start Voltage to ensure internal Power-on Reset signal (D003) | VPOR | | | 0.7 | V | See section on Power-on Reset for details | 353 |
| VDD Rise Rate to ensure internal Power-on Reset signal (D004) | SVDD | 0.05 | | | V/ms | See section on Power-on Reset for details | 353 |
| Brown-out Reset Voltage (D005) | VBOR | 1.72 | 1.82 | 1.95 | V | BORV<1:0> = 11 | 353 |
| Brown-out Reset Voltage (D005) | VBOR | 2.15 | 2.27 | 2.4 | V | BORV<1:0> = 10 | 353 |
| Brown-out Reset Voltage (D005) | VBOR | 2.65 | 2.75 | 2.9 | V | BORV<1:0> = 01 | 353 |
| Brown-out Reset Voltage (D005) | VBOR | 2.98 | 3.08 | 3.25 | V | BORV<1:0> = 00 | 353 |
| Power-down Current (IPD) D006 | IPD | | 0.05 | 1 | µA | -40°C; VDD = 1.8V, Sleep mode | 353 |
| Power-down Current (IPD) D006 | IPD | | 0.6 | 3 | µA | +85°C; VDD = 1.8V, Sleep mode | 353 |
| Power-down Current (IPD) D007 | IPD | | 0.1 | 1 | µA | -40°C; VDD = 3.0V, Sleep mode | 353 |
| Power-down Current (IPD) D007 | IPD | | 0.7 | 3 | µA | +85°C; VDD = 3.0V, Sleep mode | 353 |
| Supply Current (IDD) RC_IDLE, LFINTOSC 31 kHz (D011A) | IDD | | 3.5 | 8 | µA | -40°C; VDD = 3.0V, FOSC = 31 kHz (RC_IDLE, LFINTOSC) | 355 |
| Supply Current (IDD) RC_IDLE, LFINTOSC 31 kHz (D011A) | IDD | | 4 | 12 | µA | +85°C; VDD = 3.0V, FOSC = 31 kHz (RC_IDLE, LFINTOSC) | 355 |
| Supply Current (IDD) RC_IDLE, HF-INTOSC 1 MHz (D012) | IDD | | 0.3 | 0.4 | mA | -40°C to +125°C; VDD = 1.8V, FOSC = 1 MHz (RC_IDLE, HF-INTOSC) | 355 |
| Supply Current (IDD) RC_IDLE, HF-INTOSC 1 MHz (D012A) | IDD | | 0.4 | 0.6 | mA | -40°C to +125°C; VDD = 3.0V (RC_IDLE, HF-INTOSC) | 355 |
| Supply Current (IDD) RC_IDLE, HF-INTOSC 16 MHz (D013) | IDD | | 1 | 1.2 | mA | -40°C to +125°C; VDD = 1.8V, FOSC = 16 MHz (RC_IDLE, HF-INTOSC) | 355 |
| Supply Current (IDD) RC_IDLE, HF-INTOSC 16 MHz (D013A) | IDD | | 1.6 | 2 | mA | -40°C to +125°C; VDD = 3.0V (RC_IDLE, HF-INTOSC) | 355 |
| Supply Current (IDD) PRI_RUN 1 MHz EC (D014A) | IDD | | 0.5 | 0.75 | mA | -40°C to +125°C; VDD = 3.0V (PRI_RUN, EC oscillator) | 356 |
| Supply Current (IDD) PRI_RUN 20 MHz EC (D015A) | IDD | | 4.3 | 5 | mA | -40°C to +125°C; VDD = 3.0V (PRI_RUN, EC oscillator) | 356 |
| Supply Current (IDD) PRI_RUN 64 MHz EC (D016) | IDD | | 12.2 | 14 | mA | -40°C to +85°C; VDD = 3.0V, FOSC = 64 MHz (PRI_RUN, EC oscillator) | 356 |
| Supply Current (IDD) PRI_RUN 16 MHz internal HS+PLL (D017A) | IDD | | 4.2 | 5 | mA | -40°C to +125°C; VDD = 3.0V (PRI_RUN, HS+PLL, 16 MHz internal) | 356 |
| Supply Current (IDD) PRI_RUN 64 MHz internal HS+PLL (D018) | IDD | | 12.2 | 15 | mA | -40°C to +85°C; VDD = 3.0V, FOSC = 16 MHz, 64 MHz internal (PRI_RUN, HS+PLL) | 356 |
| Supply Current (IDD) PRI_IDLE 1 MHz EC (D019A) | IDD | | 0.09 | 0.15 | mA | -40°C to +125°C; VDD = 3.0V (PRI_IDLE, EC oscillator) | 356 |
| Supply Current (IDD) PRI_IDLE 20 MHz EC (D020A) | IDD | | 1.8 | 2.5 | mA | -40°C to +125°C; VDD = 3.0V (PRI_IDLE, EC oscillator) | 356 |
| Supply Current (IDD) PRI_IDLE 64 MHz EC (D021) | IDD | | 5.6 | 7 | mA | -40°C to +85°C; VDD = 3.0V, FOSC = 64 MHz (PRI_IDLE, EC oscillator) | 356 |
| Secondary oscillator supply current SEC_RUN (D022A) | IDD | | 10 | 15 | µA | -40°C; VDD = 3.0V (SEC_RUN, Timer1 as clock) | 357 |
| Secondary oscillator supply current SEC_RUN (D022A) | IDD | | 10 | 16 | µA | +25°C; VDD = 3.0V (SEC_RUN, Timer1 as clock) | 357 |
| Secondary oscillator supply current SEC_RUN (D022A) | IDD | | 11 | 20 | µA | +85°C; VDD = 3.0V (SEC_RUN, Timer1 as clock) | 357 |
| RC_RUN supply current HF-INTOSC 31 kHz LFINTOSC (D008A) | IDD | | 10 | 15 | µA | -40°C; VDD = 3.0V (RC_RUN, LFINTOSC) | 354 |
| RC_RUN supply current HF-INTOSC 31 kHz LFINTOSC (D008A) | IDD | | 10.5 | 16 | µA | +25°C; VDD = 3.0V (RC_RUN, LFINTOSC) | 354 |
| RC_RUN supply current HF-INTOSC 31 kHz LFINTOSC (D008A) | IDD | | 11 | 20 | µA | +85°C; VDD = 3.0V (RC_RUN, LFINTOSC) | 354 |
| Supply Current (IDD) RC_RUN HF-INTOSC 1 MHz (D009A) | IDD | | 0.6 | 0.8 | mA | -40°C to +125°C; VDD = 3.0V (RC_RUN, HF-INTOSC) | 354 |
| Supply Current (IDD) RC_RUN HF-INTOSC 16 MHz (D010A) | IDD | | 3.8 | 4.4 | mA | -40°C to +125°C; VDD = 3.0V (RC_RUN, HF-INTOSC) | 354 |
| Supply Current (IDD) RC_RUN HF-INTOSC 1 MHz (D009) | IDD | | 0.4 | 0.5 | mA | -40°C to +125°C; VDD = 1.8V, FOSC = 1 MHz (RC_RUN, HF-INTOSC) | 354 |
| Supply Current (IDD) RC_RUN HF-INTOSC 16 MHz (D010) | IDD | | 2.2 | 3 | mA | -40°C to +125°C; VDD = 1.8V, FOSC = 16 MHz (RC_RUN, HF-INTOSC) | 354 |
| Output Low Voltage I/O ports (D080) | VOL | | | 0.6 | V | IOL = 8.5 mA, VDD = 3.0V, -40°C to +85°C | 361 |
| Capacitive loading OSC2 pin (D100) | COSC2 | | | 15 | pF | In XT, HS and LP modes when external clock is used to drive OSC1 | 361 |
| Capacitive loading all I/O pins and OSC2 in RC mode (D101) | CIO | | | 50 | pF | To meet the AC Timing Specifications | 361 |
| Capacitive loading SCL, SDA (D102) | CB | | | 400 | pF | I2C Specification | 361 |
## CAD (KiCad official)
- Symbol: `PIC18F46K20-I`
- Footprint: `Package_QFP:TQFP-44_10x10mm_P0.8mm`
- 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files: `pic18f46k20-i-etched.step` / `pic18f46k20-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic18f46k20-i.step` / `pic18f46k20-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586182037783265280) (440 pp, sha256 `4e7e234c713a2325`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pic18f46k20-i-datasheet.pdf)