component
PIC18F4550-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PIC18F4550-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)
PIC18F4550-I from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC7/RX/DT/SDO | bidirectional | Digital I/O with Schmitt Trigger input; serves as EUSART asynchronous receive (RX), synchronous data (DT) or SPI data output (SDO). |
| 2 | RD4/SPP4 | bidirectional | Digital I/O or Streaming Parallel Port data bit 4 (SPP4), with TTL input buffer when the SPP is enabled. |
| 3 | RD5/SPP5/P1B | bidirectional | Digital I/O or Streaming Parallel Port data bit 5 (SPP5), or ECCP1 Enhanced PWM output channel B (P1B) that may be tri-stated during PWM shutdown events. |
| 4 | RD6/SPP6/P1C | bidirectional | Digital I/O or Streaming Parallel Port data bit 6 (SPP6), or ECCP1 Enhanced PWM output channel C (P1C) that may be tri-stated during PWM shutdown events. |
| 5 | RD7/SPP7/P1D | bidirectional | Digital I/O or Streaming Parallel Port data bit 7 (SPP7), or ECCP1 Enhanced PWM output channel D (P1D) that may be tri-stated during PWM shutdown events. |
| 6 | VSS | power_in | Ground reference for logic and I/O pins. |
| 7 | VDD | power_in | Positive supply for logic and I/O pins. |
| 8 | RB0/AN12/INT0/FLT0/SDI/SDA | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 12, external interrupt 0, Enhanced PWM Fault input (ECCP1), SPI data in, or I2C data I/O. |
| 9 | RB1/AN10/INT1/SCK/SCL | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 10, external interrupt 1, SPI clock I/O, or I2C clock I/O. |
| 10 | RB2/AN8/INT2/VMO | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 8, external interrupt 2, or external USB transceiver VMO output. |
| 11 | RB3/AN9/CCP2/VPO | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 9, CCP2 capture/compare/PWM (alternate CCP2 pin when CCP2MX is cleared), or external USB transceiver VPO output. |
| 12 | NC/ICCK/ICPGC | bidirectional | No Connect unless the ICPRT Configuration bit is set; then it is the dedicated ICD clock (ICCK) or ICSP programming clock (ICPGC). |
| 13 | NC/ICDT/ICPGD | bidirectional | No Connect unless the ICPRT Configuration bit is set; then it is the dedicated ICD data (ICDT) or ICSP programming data (ICPGD) pin. |
| 14 | RB4/AN11/KBI0/CSSPP | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 11, interrupt-on-pin-change KBI0, or SPP chip select control output CSSPP. |
| 15 | RB5/KBI1/PGM | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also interrupt-on-pin-change KBI1, or Low-Voltage ICSP programming enable pin PGM when the LVP Configuration bit is set. |
| 16 | RB6/KBI2/PGC | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also interrupt-on-pin-change KBI2, or In-Circuit Debugger and ICSP programming clock PGC. |
| 17 | RB7/KBI3/PGD | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also interrupt-on-pin-change KBI3, or In-Circuit Debugger and ICSP programming data PGD. |
| 18 | MCLR/VPP/RE3 | input | Active-low Master Clear (Reset) input when MCLRE is set; programming voltage input VPP; or digital input RE3 when MCLR is disabled. |
| 19 | RA0/AN0 | bidirectional | Digital I/O with TTL input buffer; analog input 0. |
| 20 | RA1/AN1 | bidirectional | Digital I/O with TTL input buffer; analog input 1. |
| 21 | RA2/AN2/VREF-/CVREF | bidirectional | Digital I/O with TTL input buffer; analog input 2, A/D reference voltage low input (VREF-), or analog comparator reference output (CVREF). |
| 22 | RA3/AN3/VREF+ | bidirectional | Digital I/O with TTL input buffer; analog input 3, or A/D reference voltage high input (VREF+). |
| 23 | RA4/T0CKI/C1OUT/RCV | bidirectional | Digital I/O with Schmitt Trigger input; Timer0 external clock input T0CKI, comparator 1 output C1OUT, or external USB transceiver RCV input. |
| 24 | RA5/AN4/SS/HLVDIN/C2OUT | bidirectional | Digital I/O with TTL input buffer; analog input 4, SPI slave select input SS, High/Low-Voltage Detect input HLVDIN, or comparator 2 output C2OUT. |
| 25 | RE0/AN5/CK1SPP | bidirectional | Digital I/O with Schmitt Trigger input; analog input 5 (reads '0' when analog is selected) or SPP clock 1 output CK1SPP. |
| 26 | RE1/AN6/CK2SPP | bidirectional | Digital I/O with Schmitt Trigger input; analog input 6 (reads '0' when analog is selected) or SPP clock 2 output CK2SPP. |
| 27 | RE2/AN7/OESPP | bidirectional | Digital I/O with Schmitt Trigger input; analog input 7 (reads '0' when analog is selected) or SPP output enable OESPP. |
| 28 | VDD | power_in | Positive supply for logic and I/O pins. |
| 29 | VSS | power_in | Ground reference for logic and I/O pins. |
| 30 | OSC1/CLKI | input | Oscillator crystal or external clock source input; always associated with the OSC2 pin in crystal modes. |
| 31 | OSC2/CLKO/RA6 | bidirectional | Oscillator crystal output in crystal modes; in RC mode outputs CLKO at 1/4 the OSC1 frequency; or general purpose I/O RA6 when the internal oscillator mode frees the pin. |
| 32 | RC0/T1OSO/T13CKI | bidirectional | Digital I/O with Schmitt Trigger input; Timer1 oscillator output T1OSO or Timer1/Timer3 external clock input T13CKI. |
| 33 | NC/ICRST/ICVPP | input | No Connect unless the ICPRT Configuration bit is set; then it is the dedicated ICD/ICSP Master Clear (ICRST) input or programming voltage input (ICVPP). |
| 34 | NC/ICPORTS | passive | No Connect; when ICPRT and DEBUG are configured for the dedicated port, connecting this pin to VSS enables 28-pin device emulation and connecting it to VDD gives the default configuration. |
| 35 | RC1/T1OSI/CCP2/UOE | bidirectional | Digital I/O with Schmitt Trigger input; Timer1 oscillator input T1OSI, CCP2 capture/compare/PWM (default CCP2 pin when CCP2MX is set), or external USB transceiver OE output. |
| 36 | RC2/CCP1/P1A | bidirectional | Digital I/O with Schmitt Trigger input; ECCP1 capture/compare/PWM output CCP1, or Enhanced PWM output channel A (P1A). |
| 37 | VUSB | power_out | Internal USB 3.3V voltage regulator output, providing the positive supply for the internal USB transceiver. |
| 38 | RD0/SPP0 | bidirectional | Digital I/O with Schmitt Trigger input; Streaming Parallel Port data bit 0 (SPP0) with TTL input buffer when the SPP is enabled. |
| 39 | RD1/SPP1 | bidirectional | Digital I/O with Schmitt Trigger input; Streaming Parallel Port data bit 1 (SPP1) with TTL input buffer when the SPP is enabled. |
| 40 | RD2/SPP2 | bidirectional | Digital I/O with Schmitt Trigger input; Streaming Parallel Port data bit 2 (SPP2) with TTL input buffer when the SPP is enabled. |
| 41 | RD3/SPP3 | bidirectional | Digital I/O with Schmitt Trigger input; Streaming Parallel Port data bit 3 (SPP3) with TTL input buffer when the SPP is enabled. |
| 42 | RC4/D-/VM | bidirectional | TTL digital input in port mode; USB differential minus line (D-) of the internal transceiver, or VM input from an external USB transceiver. |
| 43 | RC5/D+/VP | bidirectional | TTL digital input in port mode; USB differential plus line (D+) of the internal transceiver, or VP input from an external USB transceiver. |
| 44 | RC6/TX/CK | bidirectional | Digital I/O with Schmitt Trigger input; EUSART asynchronous transmit (TX) or synchronous clock (CK). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Standard (F) device operating VDD range | VDD | 4.2 | 5.5 | V | Standard F devices (PIC18F4550); from Section 1.3 overview text | 9 | |
| Internal oscillator (INTOSC) 8 MHz accuracy | -2 | 2 | % | 9 | |||
| Clock speed range via PLL / HS mode | 4 | 48 | MHz | PLL frequency multiplier, HSPLL/ECPLL modes; HS mode up to 48 MHz | 9 | ||
| MCLR pull-up resistor to VDD for POR | 1 | 10 | kΩ | MCLR tied to VDD through resistor | 49 | ||
| External POR circuit resistor R (slow VDD rise) | R | 40 | kΩ | Voltage drop across R must not violate electrical specification | 49 | ||
| MCLR series resistor R1 (ESD/EOS protection) | R1 | 1 | kΩ | Limits current into MCLR from external capacitor C | 49 | ||
| Maximum recommended analog source impedance | RS | 2.5 | kΩ | A/D acquisition; source impedance affects offset | 272 | ||
| A/D conversion clock TAD minimum | TAD | 0.8 | µs | Table 21-1 assumption (TAD Min = 0.8 µs) | 273 | ||
| Analog input pin leakage current | ILEAKAGE | -100 | 100 | nA | Analog input model (Figure 21-3), leakage due to various junctions | 271 | |
| HLVD internal reference voltage | 1.2 | V | Typical, HLVD block diagram (Figure 24-1) | 288 | |||
| Series resistor RS for ceramic resonator (HS mode) | RS | 330 | Ω | Recommended starting point, HS mode with ceramic resonator | 27 |
CAD (KiCad official)
- Symbol:
PIC18F4550-I - Footprint:
Package_QFP:TQFP-44_10x10mm_P0.8mm - 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
pic18f4550-i-etched.step/pic18f4550-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic18f4550-i.step/pic18f4550-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (438 pp, sha256
89dc5b86edd4804e, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PIC18F4550-I
**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)
PIC18F4550-I from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC7/RX/DT/SDO | bidirectional | Digital I/O with Schmitt Trigger input; serves as EUSART asynchronous receive (RX), synchronous data (DT) or SPI data output (SDO). |
| 2 | RD4/SPP4 | bidirectional | Digital I/O or Streaming Parallel Port data bit 4 (SPP4), with TTL input buffer when the SPP is enabled. |
| 3 | RD5/SPP5/P1B | bidirectional | Digital I/O or Streaming Parallel Port data bit 5 (SPP5), or ECCP1 Enhanced PWM output channel B (P1B) that may be tri-stated during PWM shutdown events. |
| 4 | RD6/SPP6/P1C | bidirectional | Digital I/O or Streaming Parallel Port data bit 6 (SPP6), or ECCP1 Enhanced PWM output channel C (P1C) that may be tri-stated during PWM shutdown events. |
| 5 | RD7/SPP7/P1D | bidirectional | Digital I/O or Streaming Parallel Port data bit 7 (SPP7), or ECCP1 Enhanced PWM output channel D (P1D) that may be tri-stated during PWM shutdown events. |
| 6 | VSS | power_in | Ground reference for logic and I/O pins. |
| 7 | VDD | power_in | Positive supply for logic and I/O pins. |
| 8 | RB0/AN12/INT0/FLT0/SDI/SDA | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 12, external interrupt 0, Enhanced PWM Fault input (ECCP1), SPI data in, or I2C data I/O. |
| 9 | RB1/AN10/INT1/SCK/SCL | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 10, external interrupt 1, SPI clock I/O, or I2C clock I/O. |
| 10 | RB2/AN8/INT2/VMO | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 8, external interrupt 2, or external USB transceiver VMO output. |
| 11 | RB3/AN9/CCP2/VPO | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 9, CCP2 capture/compare/PWM (alternate CCP2 pin when CCP2MX is cleared), or external USB transceiver VPO output. |
| 12 | NC/ICCK/ICPGC | bidirectional | No Connect unless the ICPRT Configuration bit is set; then it is the dedicated ICD clock (ICCK) or ICSP programming clock (ICPGC). |
| 13 | NC/ICDT/ICPGD | bidirectional | No Connect unless the ICPRT Configuration bit is set; then it is the dedicated ICD data (ICDT) or ICSP programming data (ICPGD) pin. |
| 14 | RB4/AN11/KBI0/CSSPP | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also analog input 11, interrupt-on-pin-change KBI0, or SPP chip select control output CSSPP. |
| 15 | RB5/KBI1/PGM | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also interrupt-on-pin-change KBI1, or Low-Voltage ICSP programming enable pin PGM when the LVP Configuration bit is set. |
| 16 | RB6/KBI2/PGC | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also interrupt-on-pin-change KBI2, or In-Circuit Debugger and ICSP programming clock PGC. |
| 17 | RB7/KBI3/PGD | bidirectional | Digital I/O with weak pull-up when RBPU is cleared; also interrupt-on-pin-change KBI3, or In-Circuit Debugger and ICSP programming data PGD. |
| 18 | MCLR/VPP/RE3 | input | Active-low Master Clear (Reset) input when MCLRE is set; programming voltage input VPP; or digital input RE3 when MCLR is disabled. |
| 19 | RA0/AN0 | bidirectional | Digital I/O with TTL input buffer; analog input 0. |
| 20 | RA1/AN1 | bidirectional | Digital I/O with TTL input buffer; analog input 1. |
| 21 | RA2/AN2/VREF-/CVREF | bidirectional | Digital I/O with TTL input buffer; analog input 2, A/D reference voltage low input (VREF-), or analog comparator reference output (CVREF). |
| 22 | RA3/AN3/VREF+ | bidirectional | Digital I/O with TTL input buffer; analog input 3, or A/D reference voltage high input (VREF+). |
| 23 | RA4/T0CKI/C1OUT/RCV | bidirectional | Digital I/O with Schmitt Trigger input; Timer0 external clock input T0CKI, comparator 1 output C1OUT, or external USB transceiver RCV input. |
| 24 | RA5/AN4/SS/HLVDIN/C2OUT | bidirectional | Digital I/O with TTL input buffer; analog input 4, SPI slave select input SS, High/Low-Voltage Detect input HLVDIN, or comparator 2 output C2OUT. |
| 25 | RE0/AN5/CK1SPP | bidirectional | Digital I/O with Schmitt Trigger input; analog input 5 (reads '0' when analog is selected) or SPP clock 1 output CK1SPP. |
| 26 | RE1/AN6/CK2SPP | bidirectional | Digital I/O with Schmitt Trigger input; analog input 6 (reads '0' when analog is selected) or SPP clock 2 output CK2SPP. |
| 27 | RE2/AN7/OESPP | bidirectional | Digital I/O with Schmitt Trigger input; analog input 7 (reads '0' when analog is selected) or SPP output enable OESPP. |
| 28 | VDD | power_in | Positive supply for logic and I/O pins. |
| 29 | VSS | power_in | Ground reference for logic and I/O pins. |
| 30 | OSC1/CLKI | input | Oscillator crystal or external clock source input; always associated with the OSC2 pin in crystal modes. |
| 31 | OSC2/CLKO/RA6 | bidirectional | Oscillator crystal output in crystal modes; in RC mode outputs CLKO at 1/4 the OSC1 frequency; or general purpose I/O RA6 when the internal oscillator mode frees the pin. |
| 32 | RC0/T1OSO/T13CKI | bidirectional | Digital I/O with Schmitt Trigger input; Timer1 oscillator output T1OSO or Timer1/Timer3 external clock input T13CKI. |
| 33 | NC/ICRST/ICVPP | input | No Connect unless the ICPRT Configuration bit is set; then it is the dedicated ICD/ICSP Master Clear (ICRST) input or programming voltage input (ICVPP). |
| 34 | NC/ICPORTS | passive | No Connect; when ICPRT and DEBUG are configured for the dedicated port, connecting this pin to VSS enables 28-pin device emulation and connecting it to VDD gives the default configuration. |
| 35 | RC1/T1OSI/CCP2/UOE | bidirectional | Digital I/O with Schmitt Trigger input; Timer1 oscillator input T1OSI, CCP2 capture/compare/PWM (default CCP2 pin when CCP2MX is set), or external USB transceiver OE output. |
| 36 | RC2/CCP1/P1A | bidirectional | Digital I/O with Schmitt Trigger input; ECCP1 capture/compare/PWM output CCP1, or Enhanced PWM output channel A (P1A). |
| 37 | VUSB | power_out | Internal USB 3.3V voltage regulator output, providing the positive supply for the internal USB transceiver. |
| 38 | RD0/SPP0 | bidirectional | Digital I/O with Schmitt Trigger input; Streaming Parallel Port data bit 0 (SPP0) with TTL input buffer when the SPP is enabled. |
| 39 | RD1/SPP1 | bidirectional | Digital I/O with Schmitt Trigger input; Streaming Parallel Port data bit 1 (SPP1) with TTL input buffer when the SPP is enabled. |
| 40 | RD2/SPP2 | bidirectional | Digital I/O with Schmitt Trigger input; Streaming Parallel Port data bit 2 (SPP2) with TTL input buffer when the SPP is enabled. |
| 41 | RD3/SPP3 | bidirectional | Digital I/O with Schmitt Trigger input; Streaming Parallel Port data bit 3 (SPP3) with TTL input buffer when the SPP is enabled. |
| 42 | RC4/D-/VM | bidirectional | TTL digital input in port mode; USB differential minus line (D-) of the internal transceiver, or VM input from an external USB transceiver. |
| 43 | RC5/D+/VP | bidirectional | TTL digital input in port mode; USB differential plus line (D+) of the internal transceiver, or VP input from an external USB transceiver. |
| 44 | RC6/TX/CK | bidirectional | Digital I/O with Schmitt Trigger input; EUSART asynchronous transmit (TX) or synchronous clock (CK). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Standard (F) device operating VDD range | VDD | 4.2 | | 5.5 | V | Standard F devices (PIC18F4550); from Section 1.3 overview text | 9 |
| Internal oscillator (INTOSC) 8 MHz accuracy | | -2 | | 2 | % | | 9 |
| Clock speed range via PLL / HS mode | | 4 | | 48 | MHz | PLL frequency multiplier, HSPLL/ECPLL modes; HS mode up to 48 MHz | 9 |
| MCLR pull-up resistor to VDD for POR | | 1 | | 10 | kΩ | MCLR tied to VDD through resistor | 49 |
| External POR circuit resistor R (slow VDD rise) | R | | | 40 | kΩ | Voltage drop across R must not violate electrical specification | 49 |
| MCLR series resistor R1 (ESD/EOS protection) | R1 | 1 | | | kΩ | Limits current into MCLR from external capacitor C | 49 |
| Maximum recommended analog source impedance | RS | | | 2.5 | kΩ | A/D acquisition; source impedance affects offset | 272 |
| A/D conversion clock TAD minimum | TAD | 0.8 | | | µs | Table 21-1 assumption (TAD Min = 0.8 µs) | 273 |
| Analog input pin leakage current | ILEAKAGE | -100 | | 100 | nA | Analog input model (Figure 21-3), leakage due to various junctions | 271 |
| HLVD internal reference voltage | | | 1.2 | | V | Typical, HLVD block diagram (Figure 24-1) | 288 |
| Series resistor RS for ceramic resonator (HS mode) | RS | | 330 | | Ω | Recommended starting point, HS mode with ceramic resonator | 27 |
## CAD (KiCad official)
- Symbol: `PIC18F4550-I`
- Footprint: `Package_QFP:TQFP-44_10x10mm_P0.8mm`
- 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files: `pic18f4550-i-etched.step` / `pic18f4550-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic18f4550-i.step` / `pic18f4550-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586171927140843520) (438 pp, sha256 `89dc5b86edd4804e`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pic18f4550-i-datasheet.pdf)