PIC18F24Q10-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SSOP-28-208mil

PIC18F24Q10-I from Microchip Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MCLR/VPP/RE3	input	Master Clear input that holds the device in Reset while low when MCLR is enabled, with an internal weak pull-up to VDD; it is input-only and RE3 is the read-only PORTE bit on this pin.
2	RA0	bidirectional	PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS.
3	RA1	bidirectional	PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS.
4	RA2	bidirectional	PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS.
5	RA3	bidirectional	PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS.
6	RA4	bidirectional	PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS.
7	RA5	bidirectional	PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS.
8	VSS	power_in	Ground reference; all VSS pins must be connected and each VDD/VSS pair requires a decoupling capacitor.
9	RA7	bidirectional	PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS.
10	RA6	bidirectional	PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS.
11	RC0	bidirectional	PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS.
12	RC1	bidirectional	PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS.
13	RC2	bidirectional	PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS.
14	RC3	bidirectional	PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS.
15	RC4	bidirectional	PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS.
16	RC5	bidirectional	PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS.
17	RC6	bidirectional	PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS.
18	RC7	bidirectional	PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS.
19	VSS	power_in	Ground reference; all VSS pins must be connected and each VDD/VSS pair requires a decoupling capacitor.
20	VDD	power_in	Positive supply; all VDD pins must be connected and decoupled with a low-ESR ceramic capacitor, 0.1 µF (100 nF), 10-20V recommended.
21	RB0	bidirectional	PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS.
22	RB1	bidirectional	PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS.
23	RB2	bidirectional	PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS.
24	RB3	bidirectional	PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS.
25	RB4	bidirectional	PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS.
26	RB5	bidirectional	PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS.
27	RB6/ICSPCLK	bidirectional	PORTB digital I/O pin that doubles as the ICSPCLK clock input for In-Circuit Serial Programming and debugging; keep the ICSP trace short and avoid pull-ups or series diodes on it.
28	RB7/ICSPDAT	bidirectional	PORTB digital I/O pin that doubles as the ICSPDAT bidirectional serial data pin for In-Circuit Serial Programming and debugging; avoid pull-ups, series diodes or capacitors on it.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	SSOP-28-208mil
Category	Embedded Processors & Controllers
Pins	28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Ambient temperature under bias		-40		125	°C		659
Storage temperature		-65		150	°C		659
Voltage on VDD pin with respect to VSS		-0.3		6.5	V		659
Voltage on MCLR pin with respect to VSS		-0.3		9	V		659
Voltage on all other pins with respect to VSS (max printed as VDD+0.3V)		-0.3			V		659
Maximum current on VSS pin				350	mA	-40°C ≤ TA ≤ +85°C	659
Maximum current on VSS pin				120	mA	85°C < TA ≤ +125°C	659
Maximum current on VDD pin				250	mA	-40°C ≤ TA ≤ +85°C	659
Maximum current on VDD pin				85	mA	85°C < TA ≤ +125°C	659
Maximum current on any standard I/O pin		-50		50	mA		659
Clamp current IK	IK	-20		20	mA	VPIN < 0 or VPIN > VDD	659
Total power dissipation				800	mW		659
Supply Voltage	VDD	1.8		5.5	V		660
Operating Ambient Temperature Range, Industrial	TA	-40		85	°C		660
RAM Data Retention voltage, device in SLEEP mode	VDR	1.7			V	Device in SLEEP mode	660
VDD Rise Rate to ensure internal Power-on Reset signal	SVDD	0.05			V/ms	BOR or LPBOR disabled	661
External clock, ECH oscillator clock frequency	FECH			64	MHz		667
LP oscillator clock frequency	FLP			100	kHz	Note 4	667
XT oscillator clock frequency	FXT			4	MHz	Note 4	667
HS oscillator clock frequency	FHS			20	MHz	Note 4	667
Secondary oscillator clock frequency	FSEC	32.4	32.768	33.1	kHz	Note 4	667
System clock frequency	FOSC			64	MHz	Note 2, Note 3	667
Instruction cycle period	TCY	62.5			ns		668
PLL input frequency range	FPLLIN	4		16	MHz		669
PLL output frequency range	FPLLOUT	16		64	MHz	Note 1	669
Supply current, XT = 4 MHz	IDDXT4		440	700	μA	3.0V	662
Supply current, HFINTOSC = 16 MHz	IDDHFO16		1.2	1.55	mA	3.0V	662
Supply current, HFINTOSC = 64 MHz (PLL)	IDDHFOPLL		4	5.3	mA	3.0V	662
Supply current, HS+PLL = 64 MHz	IDDHSPLL32		3.9	5.1	mA	3.0V	662
Power-down current IPD base (VREGPM b'10')	IPD		0.6	4	μA	Max at +85°C column; 3.0V; VREGPM b'10'	663
Power-down current, Low-Frequency Internal Oscillator/WDT	IPD_WDT		0.9	5	μA	Max at +85°C column; 3.0V; VREGPM b'10'	663
Power-down current, Low-Power Brown-out Reset (LPBOR)	IPD_LPBOR		0.9	6	μA	Max at +85°C column; 3.0V; VREGPM b'10'	663
Power-down current, FVR	IPD_FVR		63	125	μA	FVRCON = 0x81 or 0x84; 3.0V; VREGPM b'10'; max at +85°C column	663
Power-down current, Brown-out Reset (BOR)	IPD_BOR		30	60	μA	Max at +85°C column; 3.0V; VREGPM b'10'	663
Power-down current, Comparator	IPD_CMP		48	75	μA	Only one comparator active; 3.0V; VREGPM b'10'; max at +85°C column	663
Input Low Voltage VIL, I/O port with TTL buffer (printed value 0.8 V)	VIL			0.8	V	4.5V≤VDD≤5.5V	664
Input Low Voltage VIL, I/O port (printed 0.15 VDD; value is multiple of VDD)	VIL			0.15	×VDD	1.8V≤VDD≤4.5V	664
Input Low Voltage VIL, I/O port with Schmitt Trigger buffer (printed 0.2 VDD; value is multiple of VDD)	VIL			0.2	×VDD	2.0V≤VDD≤5.5V	664
Input Low Voltage VIL, I/O port with I2C levels (printed 0.3 VDD; value is multiple of VDD)	VIL			0.3	×VDD		664
Input Low Voltage VIL, I/O port with SMBus levels	VIL			0.8	V	2.7V≤VDD≤5.5V	664
Input Low Voltage VIL, MCLR (printed 0.2 VDD; value is multiple of VDD)	VIL			0.2	×VDD		664
Input High Voltage VIH, I/O port with TTL buffer	VIH	2			V	4.5V≤VDD≤5.5V	664
Input High Voltage VIH, I/O port with Schmitt Trigger buffer (printed 0.8VDD; value is multiple of VDD)	VIH	0.8			×VDD	2.0V≤VDD≤5.5V	664
Input High Voltage VIH, I/O port with I2C levels (printed 0.7 VDD; value is multiple of VDD)	VIH	0.7			×VDD		664
Input High Voltage VIH, I/O port with SMBus levels	VIH	2.1			V	2.7V≤VDD≤5.5V	664
Input High Voltage VIH, MCLR (printed 0.8 VDD; value is multiple of VDD)	VIH	0.8			×VDD		664
Input leakage current, I/O ports (±125 nA printed, 85°C)	IIL	-125	5	125	nA	VSS≤VPIN≤VDD, pin at high-impedance, 85°C	664
Input leakage current, MCLR (±200 nA printed, 85°C)	IIL	-200	50	200	nA	VSS≤VPIN≤VDD, pin at high-impedance, 85°C	664
Weak pull-up current	IPUR	80	140	200	μA	VDD=3.0V, VPIN=VSS	664
Output low voltage, I/O ports	VOL			0.6	V	IOL=10.0 mA, VDD=3.0V	664
All I/O pins capacitance	CIO		5	50	pF		664
BOR Reset voltage, BORV=00	VBOR	2.7	2.85	3	V	BORV=00	672
BOR Reset voltage, BORV=01	VBOR	2.55	2.7	2.85	V	BORV=01	672
BOR Reset voltage, BORV=10	VBOR	2.3	2.45	2.6	V	BORV=10	672
BOR Reset voltage, BORV=11	VBOR	1.8	1.9	2.1	V	BORV=11	672
MCLR pulse width low to ensure Reset	TMCLR	2			μs		672
Absolute accuracy, ADC integral error (EIL)	EIL	-1	0.1	1	LSb	VDD=3.0V, TA=25°C, TAD=1μs; ADCREF+=3.0V, ADCREF-=0V	673
ADC differential error (EDL)	EDL	-1	0.1	1	LSb	VDD=3.0V, TA=25°C, TAD=1μs; ADCREF+=3.0V, ADCREF-=0V	673
Thermal resistance junction to ambient, 28-pin SSOP package	θJA		90		°C/W	28-pin SSOP package	666
Maximum junction temperature	TJMAX			150	°C		666

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PPS		body RxyPPS	277

CAD (KiCad official)

Symbol: PIC18F24Q10-I
Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
3D model: SSOP-28-208mil (KiCad packages3D, STEP)
3D model files: pic18f24q10-i-etched.step / pic18f24q10-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic18f24q10-i.step / pic18f24q10-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (725 pp, sha256 e22ca20a7af480e3, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# PIC18F24Q10-I

**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · SSOP-28-208mil

PIC18F24Q10-I from Microchip Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MCLR/VPP/RE3 | input | Master Clear input that holds the device in Reset while low when MCLR is enabled, with an internal weak pull-up to VDD; it is input-only and RE3 is the read-only PORTE bit on this pin. |
| 2 | RA0 | bidirectional | PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS. |
| 3 | RA1 | bidirectional | PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS. |
| 4 | RA2 | bidirectional | PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS. |
| 5 | RA3 | bidirectional | PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS. |
| 6 | RA4 | bidirectional | PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS. |
| 7 | RA5 | bidirectional | PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS. |
| 8 | VSS | power_in | Ground reference; all VSS pins must be connected and each VDD/VSS pair requires a decoupling capacitor. |
| 9 | RA7 | bidirectional | PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS. |
| 10 | RA6 | bidirectional | PORTA digital I/O pin whose direction is set by TRISA and whose analog input mode is selected by ANSELA; peripheral functions are routed through PPS. |
| 11 | RC0 | bidirectional | PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS. |
| 12 | RC1 | bidirectional | PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS. |
| 13 | RC2 | bidirectional | PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS. |
| 14 | RC3 | bidirectional | PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS. |
| 15 | RC4 | bidirectional | PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS. |
| 16 | RC5 | bidirectional | PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS. |
| 17 | RC6 | bidirectional | PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS. |
| 18 | RC7 | bidirectional | PORTC digital I/O pin whose direction is set by TRISC and whose analog input mode is selected by ANSELC; peripheral functions are routed through PPS. |
| 19 | VSS | power_in | Ground reference; all VSS pins must be connected and each VDD/VSS pair requires a decoupling capacitor. |
| 20 | VDD | power_in | Positive supply; all VDD pins must be connected and decoupled with a low-ESR ceramic capacitor, 0.1 µF (100 nF), 10-20V recommended. |
| 21 | RB0 | bidirectional | PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS. |
| 22 | RB1 | bidirectional | PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS. |
| 23 | RB2 | bidirectional | PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS. |
| 24 | RB3 | bidirectional | PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS. |
| 25 | RB4 | bidirectional | PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS. |
| 26 | RB5 | bidirectional | PORTB digital I/O pin whose direction is set by TRISB and whose analog input mode is selected by ANSELB; peripheral functions are routed through PPS. |
| 27 | RB6/ICSPCLK | bidirectional | PORTB digital I/O pin that doubles as the ICSPCLK clock input for In-Circuit Serial Programming and debugging; keep the ICSP trace short and avoid pull-ups or series diodes on it. |
| 28 | RB7/ICSPDAT | bidirectional | PORTB digital I/O pin that doubles as the ICSPDAT bidirectional serial data pin for In-Circuit Serial Programming and debugging; avoid pull-ups, series diodes or capacitors on it. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SSOP-28-208mil |
| Category | Embedded Processors & Controllers |
| Pins | 28 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias |  | -40 |  | 125 | °C |  | 659 |
| Storage temperature |  | -65 |  | 150 | °C |  | 659 |
| Voltage on VDD pin with respect to VSS |  | -0.3 |  | 6.5 | V |  | 659 |
| Voltage on MCLR pin with respect to VSS |  | -0.3 |  | 9 | V |  | 659 |
| Voltage on all other pins with respect to VSS (max printed as VDD+0.3V) |  | -0.3 |  |  | V |  | 659 |
| Maximum current on VSS pin |  |  |  | 350 | mA | -40°C ≤ TA ≤ +85°C | 659 |
| Maximum current on VSS pin |  |  |  | 120 | mA | 85°C < TA ≤ +125°C | 659 |
| Maximum current on VDD pin |  |  |  | 250 | mA | -40°C ≤ TA ≤ +85°C | 659 |
| Maximum current on VDD pin |  |  |  | 85 | mA | 85°C < TA ≤ +125°C | 659 |
| Maximum current on any standard I/O pin |  | -50 |  | 50 | mA |  | 659 |
| Clamp current IK | IK | -20 |  | 20 | mA | VPIN < 0 or VPIN > VDD | 659 |
| Total power dissipation |  |  |  | 800 | mW |  | 659 |
| Supply Voltage | VDD | 1.8 |  | 5.5 | V |  | 660 |
| Operating Ambient Temperature Range, Industrial | TA | -40 |  | 85 | °C |  | 660 |
| RAM Data Retention voltage, device in SLEEP mode | VDR | 1.7 |  |  | V | Device in SLEEP mode | 660 |
| VDD Rise Rate to ensure internal Power-on Reset signal | SVDD | 0.05 |  |  | V/ms | BOR or LPBOR disabled | 661 |
| External clock, ECH oscillator clock frequency | FECH |  |  | 64 | MHz |  | 667 |
| LP oscillator clock frequency | FLP |  |  | 100 | kHz | Note 4 | 667 |
| XT oscillator clock frequency | FXT |  |  | 4 | MHz | Note 4 | 667 |
| HS oscillator clock frequency | FHS |  |  | 20 | MHz | Note 4 | 667 |
| Secondary oscillator clock frequency | FSEC | 32.4 | 32.768 | 33.1 | kHz | Note 4 | 667 |
| System clock frequency | FOSC |  |  | 64 | MHz | Note 2, Note 3 | 667 |
| Instruction cycle period | TCY | 62.5 |  |  | ns |  | 668 |
| PLL input frequency range | FPLLIN | 4 |  | 16 | MHz |  | 669 |
| PLL output frequency range | FPLLOUT | 16 |  | 64 | MHz | Note 1 | 669 |
| Supply current, XT = 4 MHz | IDDXT4 |  | 440 | 700 | μA | 3.0V | 662 |
| Supply current, HFINTOSC = 16 MHz | IDDHFO16 |  | 1.2 | 1.55 | mA | 3.0V | 662 |
| Supply current, HFINTOSC = 64 MHz (PLL) | IDDHFOPLL |  | 4 | 5.3 | mA | 3.0V | 662 |
| Supply current, HS+PLL = 64 MHz | IDDHSPLL32 |  | 3.9 | 5.1 | mA | 3.0V | 662 |
| Power-down current IPD base (VREGPM b'10') | IPD |  | 0.6 | 4 | μA | Max at +85°C column; 3.0V; VREGPM b'10' | 663 |
| Power-down current, Low-Frequency Internal Oscillator/WDT | IPD_WDT |  | 0.9 | 5 | μA | Max at +85°C column; 3.0V; VREGPM b'10' | 663 |
| Power-down current, Low-Power Brown-out Reset (LPBOR) | IPD_LPBOR |  | 0.9 | 6 | μA | Max at +85°C column; 3.0V; VREGPM b'10' | 663 |
| Power-down current, FVR | IPD_FVR |  | 63 | 125 | μA | FVRCON = 0x81 or 0x84; 3.0V; VREGPM b'10'; max at +85°C column | 663 |
| Power-down current, Brown-out Reset (BOR) | IPD_BOR |  | 30 | 60 | μA | Max at +85°C column; 3.0V; VREGPM b'10' | 663 |
| Power-down current, Comparator | IPD_CMP |  | 48 | 75 | μA | Only one comparator active; 3.0V; VREGPM b'10'; max at +85°C column | 663 |
| Input Low Voltage VIL, I/O port with TTL buffer (printed value 0.8 V) | VIL |  |  | 0.8 | V | 4.5V≤VDD≤5.5V | 664 |
| Input Low Voltage VIL, I/O port (printed 0.15 VDD; value is multiple of VDD) | VIL |  |  | 0.15 | ×VDD | 1.8V≤VDD≤4.5V | 664 |
| Input Low Voltage VIL, I/O port with Schmitt Trigger buffer (printed 0.2 VDD; value is multiple of VDD) | VIL |  |  | 0.2 | ×VDD | 2.0V≤VDD≤5.5V | 664 |
| Input Low Voltage VIL, I/O port with I2C levels (printed 0.3 VDD; value is multiple of VDD) | VIL |  |  | 0.3 | ×VDD |  | 664 |
| Input Low Voltage VIL, I/O port with SMBus levels | VIL |  |  | 0.8 | V | 2.7V≤VDD≤5.5V | 664 |
| Input Low Voltage VIL, MCLR (printed 0.2 VDD; value is multiple of VDD) | VIL |  |  | 0.2 | ×VDD |  | 664 |
| Input High Voltage VIH, I/O port with TTL buffer | VIH | 2 |  |  | V | 4.5V≤VDD≤5.5V | 664 |
| Input High Voltage VIH, I/O port with Schmitt Trigger buffer (printed 0.8VDD; value is multiple of VDD) | VIH | 0.8 |  |  | ×VDD | 2.0V≤VDD≤5.5V | 664 |
| Input High Voltage VIH, I/O port with I2C levels (printed 0.7 VDD; value is multiple of VDD) | VIH | 0.7 |  |  | ×VDD |  | 664 |
| Input High Voltage VIH, I/O port with SMBus levels | VIH | 2.1 |  |  | V | 2.7V≤VDD≤5.5V | 664 |
| Input High Voltage VIH, MCLR (printed 0.8 VDD; value is multiple of VDD) | VIH | 0.8 |  |  | ×VDD |  | 664 |
| Input leakage current, I/O ports (±125 nA printed, 85°C) | IIL | -125 | 5 | 125 | nA | VSS≤VPIN≤VDD, pin at high-impedance, 85°C | 664 |
| Input leakage current, MCLR (±200 nA printed, 85°C) | IIL | -200 | 50 | 200 | nA | VSS≤VPIN≤VDD, pin at high-impedance, 85°C | 664 |
| Weak pull-up current | IPUR | 80 | 140 | 200 | μA | VDD=3.0V, VPIN=VSS | 664 |
| Output low voltage, I/O ports | VOL |  |  | 0.6 | V | IOL=10.0 mA, VDD=3.0V | 664 |
| All I/O pins capacitance | CIO |  | 5 | 50 | pF |  | 664 |
| BOR Reset voltage, BORV=00 | VBOR | 2.7 | 2.85 | 3 | V | BORV=00 | 672 |
| BOR Reset voltage, BORV=01 | VBOR | 2.55 | 2.7 | 2.85 | V | BORV=01 | 672 |
| BOR Reset voltage, BORV=10 | VBOR | 2.3 | 2.45 | 2.6 | V | BORV=10 | 672 |
| BOR Reset voltage, BORV=11 | VBOR | 1.8 | 1.9 | 2.1 | V | BORV=11 | 672 |
| MCLR pulse width low to ensure Reset | TMCLR | 2 |  |  | μs |  | 672 |
| Absolute accuracy, ADC integral error (EIL) | EIL | -1 | 0.1 | 1 | LSb | VDD=3.0V, TA=25°C, TAD=1μs; ADCREF+=3.0V, ADCREF-=0V | 673 |
| ADC differential error (EDL) | EDL | -1 | 0.1 | 1 | LSb | VDD=3.0V, TA=25°C, TAD=1μs; ADCREF+=3.0V, ADCREF-=0V | 673 |
| Thermal resistance junction to ambient, 28-pin SSOP package | θJA |  | 90 |  | °C/W | 28-pin SSOP package | 666 |
| Maximum junction temperature | TJMAX |  |  | 150 | °C |  | 666 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PPS |  | body RxyPPS | 277 |

## CAD (KiCad official)

- Symbol: `PIC18F24Q10-I`
- Footprint: `Package_SO:SSOP-28_5.3x10.2mm_P0.65mm`
- 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files: `pic18f24q10-i-etched.step` / `pic18f24q10-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic18f24q10-i.step` / `pic18f24q10-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590209561924558848) (725 pp, sha256 `e22ca20a7af480e3`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pic18f24q10-i-datasheet.pdf)