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PIC18F24J11-I
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Microchip Tech MICROCHIP, QFN-28-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+89docs/hero.pngdocs/pic18f24j11-i-datasheet.pdfpackage.json+318page.json+324pic18f24j11-i-etched.glbpic18f24j11-i-hero.glbpic18f24j11-i-hero.overlay.json+713pic18f24j11-i.glbpic18f24j11-i.kicad_mod+397pic18f24j11-i.kicad_sym+129pic18f24j11-i.lbr+195pic18f24j11-i.step+7342viewers/footprint.html+1viewers/symbol.html+1README.mdadded+89@@ -0,0 +1,89 @@+# PIC18F24J11-I++**Microchip Tech** · MICROCHIP · QFN-28-EP(6x6)++PIC18F24J11-I from Microchip Tech, in a QFN-28-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RA2/AN2/VREF-/CVREF/C2INB | bidirectional | PORTA digital I/O with analog input 2, A/D reference voltage (low) input, comparator reference voltage output and comparator 2 input B. |+| 2 | RA3/AN3/VREF+/C1INB | bidirectional | PORTA digital I/O with analog input 3, A/D reference voltage (high) input and comparator 1 input B. |+| 3 | VDDCORE/VCAP | power_in | Core logic supply (VDDCORE, regulator disabled on LF parts) or external filter capacitor connection (VCAP, regulator enabled on F parts). |+| 4 | RA5/AN4/SS1/HLVDIN/RP2 | bidirectional | PORTA digital I/O with analog input 4, SPI slave select input, high/low-voltage detect input and remappable peripheral pin 2. |+| 5 | VSS1 | power_in | Ground reference for logic and I/O pins. |+| 6 | OSC1/CLKI/RA7 | bidirectional | Oscillator crystal input or external clock source input (ST in RC mode, CMOS otherwise); also digital I/O RA7, which is disabled when OSC1 is used for the clock function. |+| 7 | OSC2/CLKO/RA6 | bidirectional | Oscillator crystal output or CLKO (1/4 the OSC1 frequency in RC mode); also digital I/O RA6, which is disabled when OSC2 is used for the clock function. |+| 8 | RC0/T1OSO/T1CKI/RP11 | bidirectional | PORTC digital I/O with Timer1 oscillator output, Timer1/Timer3 external clock input and remappable peripheral pin 11. |+| 9 | RC1/T1OSI/RP12 | bidirectional | PORTC digital I/O with Timer1 oscillator input and remappable peripheral pin 12. |+| 10 | RC2/AN11/CTPLS/RP13 | bidirectional | PORTC digital I/O with analog input 11, CTMU pulse generator output and remappable peripheral pin 13. |+| 11 | RC3/SCK1/SCL1/RP14 | bidirectional | PORTC digital I/O with SPI/I2C synchronous serial clock input/output (MSSP1) and remappable peripheral pin 14. |+| 12 | RC4/SDI1/SDA1/RP15 | bidirectional | PORTC digital I/O with SPI data input, I2C data I/O (MSSP1) and remappable peripheral pin 15. |+| 13 | RC5/SDO1/RP16 | bidirectional | PORTC digital I/O with SPI data output (MSSP1) and remappable peripheral pin 16. |+| 14 | RC6/TX1/CK1/RP17 | bidirectional | PORTC digital I/O with EUSART1 asynchronous transmit, EUSART1 synchronous clock and remappable peripheral pin 17. |+| 15 | RC7/RX1/DT1/RP18 | bidirectional | PORTC digital I/O with EUSART1 asynchronous receive data input, synchronous data I/O and remappable peripheral pin 18. |+| 16 | VSS2 | power_in | Ground reference for logic and I/O pins. |+| 17 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins. |+| 18 | RB0/AN12/INT0/RP3 | bidirectional | PORTB digital I/O (software-programmable weak pull-up) with analog input 12, external interrupt 0 and remappable peripheral pin 3. |+| 19 | RB1/AN10/RTCC/RP4 | bidirectional | PORTB digital I/O with analog input 10, real-time clock calendar output and remappable peripheral pin 4. |+| 20 | RB2/AN8/CTED1/REFO/RP5 | bidirectional | PORTB digital I/O with analog input 8, CTMU edge 1 input, reference output clock and remappable peripheral pin 5. |+| 21 | RB3/AN9/CTED2/RP6 | bidirectional | PORTB digital I/O with analog input 9, CTMU edge 2 input and remappable peripheral pin 6. |+| 22 | RB4/KBI0/RP7 | bidirectional | PORTB digital I/O with interrupt-on-change and remappable peripheral pin 7. |+| 23 | RB5/KBI1/RP8 | bidirectional | PORTB digital I/O with interrupt-on-change and remappable peripheral pin 8. |+| 24 | RB6/KBI2/PGC/RP9 | bidirectional | PORTB digital I/O with interrupt-on-change, ICSP clock input and remappable peripheral pin 9. |+| 25 | RB7/KBI3/PGD/RP10 | bidirectional | PORTB digital I/O with interrupt-on-change, In-Circuit Debugger/ICSP programming data pin and remappable peripheral pin 10. |+| 26 | MCLR | input | Master Clear input; active-low Reset to the device (Schmitt Trigger input). |+| 27 | RA0/AN0/C1INA/ULPWU/RP0 | bidirectional | PORTA digital I/O with analog input 0, comparator 1 input A, ultra low-power wake-up input and remappable peripheral pin 0. |+| 28 | RA1/AN1/C2INA/RP1 | bidirectional | PORTA digital I/O with analog input 1, comparator 2 input A and remappable peripheral pin 1. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Microchip Tech |+| Package | QFN-28-EP(6x6) |+| Category | Embedded Processors & Controllers |+| Pins | 29 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Operating supply voltage (F device, regulator enabled) | VDD | 2.15 | | 3.6 | V | F part numbers; VDDCORE/VCAP connected to VSS through a low-ESR capacitor | 12 |+| Operating frequency | | 0 | | 48 | MHz | DC, 48 MHz | 13 |+| Input voltage tolerance, digital-only pins | | | | 5.5 | V | Pins used as digital-only inputs | 131 |+| VCAP/VDDCORE capacitor ESR | ESR | | | 5 | Ω | Regulator enabled (F devices); '< 5Ω' | 33 |+| VCAP/VDDCORE capacitor value | | | 10 | | µF | Connected to ground, ceramic or tantalum | 33 |+| Flash program memory endurance | | 10000 | | | cycles | Erase/write cycles minimum | 3 |+| Flash data retention | | 20 | | | years | Flash program memory | 3 |+| Internal oscillator accuracy (tunable) | | -1 | 0.15 | 1 | % | 31 kHz to 8 MHz; ±0.15% typical, ±1% max | 3 |+| Sleep mode current | | | 105 | | nA | Sleep mode, typical, 'currents down to' | 3 |++## Materials and finish++As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).++| Part | Material | Colour / plating | Datasheet says | Page |+|---|---|---|---|---|+| housing | ppa | | create the 10-bit time base. 2: These pins are remappable. | 255 |++## CAD (KiCad official)++- Symbol: `PIC18F24J11-I`+- Footprint: `Package_DFN_QFN:QFN-28-1EP_6x6mm_P0.65mm_EP4.8x4.8mm`+- 3D model: QFN-28-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `pic18f24j11-i-etched.step` / `pic18f24j11-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic18f24j11-i.step` / `pic18f24j11-i.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Microchip Tech datasheet](https://ww1.microchip.com/downloads/en/DeviceDoc/39932D.pdf) (536 pp, sha256 `692546e94e6fefb6`, retrieved 2026-10-27, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/pic18f24j11-i-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "pic18f24j11-i",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "pic18f24j11-i.kicad_sym",+ "pic18f24j11-i.kicad_mod",+ "pic18f24j11-i.glb",+ "pic18f24j11-i.step",+ "pic18f24j11-i.lbr",+ "docs/hero.png",+ "docs/pic18f24j11-i-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "pic18f24j11-i-hero.glb",+ "pic18f24j11-i-hero.overlay.json",+ "pic18f24j11-i-etched.glb"+ ],+ "component": {+ "mpn": "PIC18F24J11-I",+ "manufacturer": "Microchip Tech",+ "package": "QFN-28-EP(6x6)",+ "pin_count": 29,+ "category": "Embedded Processors & Controllers",+ "subcategory": "MICROCHIP",+ "datasheet": "https://ww1.microchip.com/downloads/en/DeviceDoc/39932D.pdf",+ "parts": {+ "symbol": "pic18f24j11-i.kicad_sym",+ "footprint": "pic18f24j11-i.kicad_mod",+ "model_3d": "pic18f24j11-i-hero.glb",+ "model_3d_plain": "pic18f24j11-i-etched.glb",+ "model_3d_step": "pic18f24j11-i-etched.step",+ "model_3d_step_plain": "pic18f24j11-i.step",+ "lbr": "pic18f24j11-i.lbr"+ },+ "distributor_links": {+ "lcsc": "C220750"+ },+ "distributor_check": {+ "checked_at": "2026-10-27T00:48:11Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "RA2/AN2/VREF-/CVREF/C2INB",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 2, A/D reference voltage (low) input, comparator reference voltage output and comparator 2 input B."+ },+ {+ "number": "2",+ "name": "RA3/AN3/VREF+/C1INB",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 3, A/D reference voltage (high) input and comparator 1 input B."+ },+ {+ "number": "3",+ "name": "VDDCORE/VCAP",+ "type": "power_in",+ "description": "Core logic supply (VDDCORE, regulator disabled on LF parts) or external filter capacitor connection (VCAP, regulator enabled on F parts)."+ },+ {+ "number": "4",+ "name": "RA5/AN4/SS1/HLVDIN/RP2",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 4, SPI slave select input, high/low-voltage detect input and remappable peripheral pin 2."+ },+ {+ "number": "5",+ "name": "VSS1",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "6",+ "name": "OSC1/CLKI/RA7",+ "type": "bidirectional",+ "description": "Oscillator crystal input or external clock source input (ST in RC mode, CMOS otherwise); also digital I/O RA7, which is disabled when OSC1 is used for the clock function."+ },+ {+ "number": "7",+ "name": "OSC2/CLKO/RA6",+ "type": "bidirectional",+ "description": "Oscillator crystal output or CLKO (1/4 the OSC1 frequency in RC mode); also digital I/O RA6, which is disabled when OSC2 is used for the clock function."+ },+ {+ "number": "8",+ "name": "RC0/T1OSO/T1CKI/RP11",+ "type": "bidirectional",+ "description": "PORTC digital I/O with Timer1 oscillator output, Timer1/Timer3 external clock input and remappable peripheral pin 11."+ },+ {+ "number": "9",+ "name": "RC1/T1OSI/RP12",+ "type": "bidirectional",+ "description": "PORTC digital I/O with Timer1 oscillator input and remappable peripheral pin 12."+ },+ {+ "number": "10",+ "name": "RC2/AN11/CTPLS/RP13",+ "type": "bidirectional",+ "description": "PORTC digital I/O with analog input 11, CTMU pulse generator output and remappable peripheral pin 13."+ },+ {+ "number": "11",+ "name": "RC3/SCK1/SCL1/RP14",+ "type": "bidirectional",+ "description": "PORTC digital I/O with SPI/I2C synchronous serial clock input/output (MSSP1) and remappable peripheral pin 14."+ },+ {+ "number": "12",+ "name": "RC4/SDI1/SDA1/RP15",+ "type": "bidirectional",+ "description": "PORTC digital I/O with SPI data input, I2C data I/O (MSSP1) and remappable peripheral pin 15."+ },+ {+ "number": "13",+ "name": "RC5/SDO1/RP16",+ "type": "bidirectional",+ "description": "PORTC digital I/O with SPI data output (MSSP1) and remappable peripheral pin 16."+ },+ {+ "number": "14",+ "name": "RC6/TX1/CK1/RP17",+ "type": "bidirectional",+ "description": "PORTC digital I/O with EUSART1 asynchronous transmit, EUSART1 synchronous clock and remappable peripheral pin 17."+ },+ {+ "number": "15",+ "name": "RC7/RX1/DT1/RP18",+ "type": "bidirectional",+ "description": "PORTC digital I/O with EUSART1 asynchronous receive data input, synchronous data I/O and remappable peripheral pin 18."+ },+ {+ "number": "16",+ "name": "VSS2",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "17",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral digital logic and I/O pins."+ },+ {+ "number": "18",+ "name": "RB0/AN12/INT0/RP3",+ "type": "bidirectional",+ "description": "PORTB digital I/O (software-programmable weak pull-up) with analog input 12, external interrupt 0 and remappable peripheral pin 3."+ },+ {+ "number": "19",+ "name": "RB1/AN10/RTCC/RP4",+ "type": "bidirectional",+ "description": "PORTB digital I/O with analog input 10, real-time clock calendar output and remappable peripheral pin 4."+ },+ {+ "number": "20",+ "name": "RB2/AN8/CTED1/REFO/RP5",+ "type": "bidirectional",+ "description": "PORTB digital I/O with analog input 8, CTMU edge 1 input, reference output clock and remappable peripheral pin 5."+ },+ {+ "number": "21",+ "name": "RB3/AN9/CTED2/RP6",+ "type": "bidirectional",+ "description": "PORTB digital I/O with analog input 9, CTMU edge 2 input and remappable peripheral pin 6."+ },+ {+ "number": "22",+ "name": "RB4/KBI0/RP7",+ "type": "bidirectional",+ "description": "PORTB digital I/O with interrupt-on-change and remappable peripheral pin 7."+ },+ {+ "number": "23",+ "name": "RB5/KBI1/RP8",+ "type": "bidirectional",+ "description": "PORTB digital I/O with interrupt-on-change and remappable peripheral pin 8."+ },+ {+ "number": "24",+ "name": "RB6/KBI2/PGC/RP9",+ "type": "bidirectional",+ "description": "PORTB digital I/O with interrupt-on-change, ICSP clock input and remappable peripheral pin 9."+ },+ {+ "number": "25",+ "name": "RB7/KBI3/PGD/RP10",+ "type": "bidirectional",+ "description": "PORTB digital I/O with interrupt-on-change, In-Circuit Debugger/ICSP programming data pin and remappable peripheral pin 10."+ },+ {+ "number": "26",+ "name": "MCLR",+ "type": "input",+ "description": "Master Clear input; active-low Reset to the device (Schmitt Trigger input)."+ },+ {+ "number": "27",+ "name": "RA0/AN0/C1INA/ULPWU/RP0",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 0, comparator 1 input A, ultra low-power wake-up input and remappable peripheral pin 0."+ },+ {+ "number": "28",+ "name": "RA1/AN1/C2INA/RP1",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 1, comparator 2 input A and remappable peripheral pin 1."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet's 28-lead QFN drawing (page 512) shows an exposed pad, but the pinout table gives it n; The MPN 'PIC18F24J11-I' has no package suffix. The datasheet marking examples (page 507) show '/ML' ; Some pin numbers in the extracted table text were run together (for example '96', '41', '52', '74')."+ ],+ "pages_sent": 91,+ "cost_usd": 0.7882,+ "at": "2026-10-27T00:47:38"+ },+ "datasheet": {+ "url": "https://ww1.microchip.com/downloads/en/DeviceDoc/39932D.pdf",+ "pages": 536,+ "sha256": "692546e94e6fefb6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "pic18f24j11-i.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 0.93+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "64a3dae9c9f9a8105c3bb3049fb2c326b3235bef9a1fff0bf5e22c753fbc9b55",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "pic18f24j11-i-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 0.93+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "70e8d68e869f075a49e9e21e20dea43d9f2c66aa263f428ae35467893476a771",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ }+}
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "pic18f24j11-i",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "pic18f24j11-i.kicad_sym",+ "pic18f24j11-i.kicad_mod",+ "pic18f24j11-i.glb",+ "pic18f24j11-i.step",+ "pic18f24j11-i.lbr",+ "docs/hero.png",+ "docs/pic18f24j11-i-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "pic18f24j11-i-hero.glb",+ "pic18f24j11-i-hero.overlay.json",+ "pic18f24j11-i-etched.glb"+ ],+ "component": {+ "mpn": "PIC18F24J11-I",+ "manufacturer": "Microchip Tech",+ "package": "QFN-28-EP(6x6)",+ "pin_count": 29,+ "category": "Embedded Processors & Controllers",+ "subcategory": "MICROCHIP",+ "datasheet": "https://ww1.microchip.com/downloads/en/DeviceDoc/39932D.pdf",+ "parts": {+ "symbol": "pic18f24j11-i.kicad_sym",+ "footprint": "pic18f24j11-i.kicad_mod",+ "model_3d": "pic18f24j11-i-hero.glb",+ "model_3d_plain": "pic18f24j11-i-etched.glb",+ "model_3d_step": "pic18f24j11-i-etched.step",+ "model_3d_step_plain": "pic18f24j11-i.step",+ "lbr": "pic18f24j11-i.lbr"+ },+ "distributor_links": {+ "lcsc": "C220750"+ },+ "distributor_check": {+ "checked_at": "2026-10-27T00:48:11Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "RA2/AN2/VREF-/CVREF/C2INB",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 2, A/D reference voltage (low) input, comparator reference voltage output and comparator 2 input B."+ },+ {+ "number": "2",+ "name": "RA3/AN3/VREF+/C1INB",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 3, A/D reference voltage (high) input and comparator 1 input B."+ },+ {+ "number": "3",+ "name": "VDDCORE/VCAP",+ "type": "power_in",+ "description": "Core logic supply (VDDCORE, regulator disabled on LF parts) or external filter capacitor connection (VCAP, regulator enabled on F parts)."+ },+ {+ "number": "4",+ "name": "RA5/AN4/SS1/HLVDIN/RP2",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 4, SPI slave select input, high/low-voltage detect input and remappable peripheral pin 2."+ },+ {+ "number": "5",+ "name": "VSS1",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "6",+ "name": "OSC1/CLKI/RA7",+ "type": "bidirectional",+ "description": "Oscillator crystal input or external clock source input (ST in RC mode, CMOS otherwise); also digital I/O RA7, which is disabled when OSC1 is used for the clock function."+ },+ {+ "number": "7",+ "name": "OSC2/CLKO/RA6",+ "type": "bidirectional",+ "description": "Oscillator crystal output or CLKO (1/4 the OSC1 frequency in RC mode); also digital I/O RA6, which is disabled when OSC2 is used for the clock function."+ },+ {+ "number": "8",+ "name": "RC0/T1OSO/T1CKI/RP11",+ "type": "bidirectional",+ "description": "PORTC digital I/O with Timer1 oscillator output, Timer1/Timer3 external clock input and remappable peripheral pin 11."+ },+ {+ "number": "9",+ "name": "RC1/T1OSI/RP12",+ "type": "bidirectional",+ "description": "PORTC digital I/O with Timer1 oscillator input and remappable peripheral pin 12."+ },+ {+ "number": "10",+ "name": "RC2/AN11/CTPLS/RP13",+ "type": "bidirectional",+ "description": "PORTC digital I/O with analog input 11, CTMU pulse generator output and remappable peripheral pin 13."+ },+ {+ "number": "11",+ "name": "RC3/SCK1/SCL1/RP14",+ "type": "bidirectional",+ "description": "PORTC digital I/O with SPI/I2C synchronous serial clock input/output (MSSP1) and remappable peripheral pin 14."+ },+ {+ "number": "12",+ "name": "RC4/SDI1/SDA1/RP15",+ "type": "bidirectional",+ "description": "PORTC digital I/O with SPI data input, I2C data I/O (MSSP1) and remappable peripheral pin 15."+ },+ {+ "number": "13",+ "name": "RC5/SDO1/RP16",+ "type": "bidirectional",+ "description": "PORTC digital I/O with SPI data output (MSSP1) and remappable peripheral pin 16."+ },+ {+ "number": "14",+ "name": "RC6/TX1/CK1/RP17",+ "type": "bidirectional",+ "description": "PORTC digital I/O with EUSART1 asynchronous transmit, EUSART1 synchronous clock and remappable peripheral pin 17."+ },+ {+ "number": "15",+ "name": "RC7/RX1/DT1/RP18",+ "type": "bidirectional",+ "description": "PORTC digital I/O with EUSART1 asynchronous receive data input, synchronous data I/O and remappable peripheral pin 18."+ },+ {+ "number": "16",+ "name": "VSS2",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "17",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for peripheral digital logic and I/O pins."+ },+ {+ "number": "18",+ "name": "RB0/AN12/INT0/RP3",+ "type": "bidirectional",+ "description": "PORTB digital I/O (software-programmable weak pull-up) with analog input 12, external interrupt 0 and remappable peripheral pin 3."+ },+ {+ "number": "19",+ "name": "RB1/AN10/RTCC/RP4",+ "type": "bidirectional",+ "description": "PORTB digital I/O with analog input 10, real-time clock calendar output and remappable peripheral pin 4."+ },+ {+ "number": "20",+ "name": "RB2/AN8/CTED1/REFO/RP5",+ "type": "bidirectional",+ "description": "PORTB digital I/O with analog input 8, CTMU edge 1 input, reference output clock and remappable peripheral pin 5."+ },+ {+ "number": "21",+ "name": "RB3/AN9/CTED2/RP6",+ "type": "bidirectional",+ "description": "PORTB digital I/O with analog input 9, CTMU edge 2 input and remappable peripheral pin 6."+ },+ {+ "number": "22",+ "name": "RB4/KBI0/RP7",+ "type": "bidirectional",+ "description": "PORTB digital I/O with interrupt-on-change and remappable peripheral pin 7."+ },+ {+ "number": "23",+ "name": "RB5/KBI1/RP8",+ "type": "bidirectional",+ "description": "PORTB digital I/O with interrupt-on-change and remappable peripheral pin 8."+ },+ {+ "number": "24",+ "name": "RB6/KBI2/PGC/RP9",+ "type": "bidirectional",+ "description": "PORTB digital I/O with interrupt-on-change, ICSP clock input and remappable peripheral pin 9."+ },+ {+ "number": "25",+ "name": "RB7/KBI3/PGD/RP10",+ "type": "bidirectional",+ "description": "PORTB digital I/O with interrupt-on-change, In-Circuit Debugger/ICSP programming data pin and remappable peripheral pin 10."+ },+ {+ "number": "26",+ "name": "MCLR",+ "type": "input",+ "description": "Master Clear input; active-low Reset to the device (Schmitt Trigger input)."+ },+ {+ "number": "27",+ "name": "RA0/AN0/C1INA/ULPWU/RP0",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 0, comparator 1 input A, ultra low-power wake-up input and remappable peripheral pin 0."+ },+ {+ "number": "28",+ "name": "RA1/AN1/C2INA/RP1",+ "type": "bidirectional",+ "description": "PORTA digital I/O with analog input 1, comparator 2 input A and remappable peripheral pin 1."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet's 28-lead QFN drawing (page 512) shows an exposed pad, but the pinout table gives it n; The MPN 'PIC18F24J11-I' has no package suffix. The datasheet marking examples (page 507) show '/ML' ; Some pin numbers in the extracted table text were run together (for example '96', '41', '52', '74')."+ ],+ "pages_sent": 91,+ "cost_usd": 0.7882,+ "at": "2026-10-27T00:47:38"+ },+ "datasheet": {+ "url": "https://ww1.microchip.com/downloads/en/DeviceDoc/39932D.pdf",+ "pages": 536,+ "sha256": "692546e94e6fefb6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "pic18f24j11-i.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 0.93+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "64a3dae9c9f9a8105c3bb3049fb2c326b3235bef9a1fff0bf5e22c753fbc9b55",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "pic18f24j11-i-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 0.93+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "70e8d68e869f075a49e9e21e20dea43d9f2c66aa263f428ae35467893476a771",+ "checked": "2026-10-27",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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SURFACE_STYLE_FILL_AREA(#7217);+#7217 = FILL_AREA_STYLE('',(#7218));+#7218 = FILL_AREA_STYLE_COLOUR('',#5999);+#7219 = STYLED_ITEM('color',(#7220),#5881);+#7220 = PRESENTATION_STYLE_ASSIGNMENT((#7221));+#7221 = SURFACE_STYLE_USAGE(.BOTH.,#7222);+#7222 = SURFACE_SIDE_STYLE('',(#7223));+#7223 = SURFACE_STYLE_FILL_AREA(#7224);+#7224 = FILL_AREA_STYLE('',(#7225));+#7225 = FILL_AREA_STYLE_COLOUR('',#5999);+#7226 = STYLED_ITEM('color',(#7227),#5893);+#7227 = PRESENTATION_STYLE_ASSIGNMENT((#7228));+#7228 = SURFACE_STYLE_USAGE(.BOTH.,#7229);+#7229 = SURFACE_SIDE_STYLE('',(#7230));+#7230 = SURFACE_STYLE_FILL_AREA(#7231);+#7231 = FILL_AREA_STYLE('',(#7232));+#7232 = FILL_AREA_STYLE_COLOUR('',#5999);+#7233 = STYLED_ITEM('color',(#7234),#5910);+#7234 = PRESENTATION_STYLE_ASSIGNMENT((#7235));+#7235 = SURFACE_STYLE_USAGE(.BOTH.,#7236);+#7236 = SURFACE_SIDE_STYLE('',(#7237));+#7237 = SURFACE_STYLE_FILL_AREA(#7238);+#7238 = FILL_AREA_STYLE('',(#7239));+#7239 = FILL_AREA_STYLE_COLOUR('',#5999);+#7240 = STYLED_ITEM('color',(#7241),#5922);+#7241 = PRESENTATION_STYLE_ASSIGNMENT((#7242));+#7242 = SURFACE_STYLE_USAGE(.BOTH.,#7243);+#7243 = SURFACE_SIDE_STYLE('',(#7244));+#7244 = SURFACE_STYLE_FILL_AREA(#7245);+#7245 = FILL_AREA_STYLE('',(#7246));+#7246 = FILL_AREA_STYLE_COLOUR('',#5999);+#7247 = STYLED_ITEM('color',(#7248),#5939);+#7248 = PRESENTATION_STYLE_ASSIGNMENT((#7249));+#7249 = SURFACE_STYLE_USAGE(.BOTH.,#7250);+#7250 = SURFACE_SIDE_STYLE('',(#7251));+#7251 = SURFACE_STYLE_FILL_AREA(#7252);+#7252 = FILL_AREA_STYLE('',(#7253));+#7253 = FILL_AREA_STYLE_COLOUR('',#5999);+#7254 = STYLED_ITEM('color',(#7255),#5951);+#7255 = PRESENTATION_STYLE_ASSIGNMENT((#7256));+#7256 = SURFACE_STYLE_USAGE(.BOTH.,#7257);+#7257 = SURFACE_SIDE_STYLE('',(#7258));+#7258 = SURFACE_STYLE_FILL_AREA(#7259);+#7259 = FILL_AREA_STYLE('',(#7260));+#7260 = FILL_AREA_STYLE_COLOUR('',#7261);+#7261 = COLOUR_RGB('',0.690999984741,0.663999974728,0.597999989986);+#7262 = STYLED_ITEM('color',(#7263),#5976);+#7263 = PRESENTATION_STYLE_ASSIGNMENT((#7264));+#7264 = SURFACE_STYLE_USAGE(.BOTH.,#7265);+#7265 = SURFACE_SIDE_STYLE('',(#7266));+#7266 = SURFACE_STYLE_FILL_AREA(#7267);+#7267 = FILL_AREA_STYLE('',(#7268));+#7268 = FILL_AREA_STYLE_COLOUR('',#7261);+ENDSEC;+END-ISO-10303-21;
viewers/footprint.htmladded+1@@ -0,0 +1 @@+<!doctype html><title>pic18f24j11-i</title>
viewers/symbol.htmladded+1@@ -0,0 +1 @@+<!doctype html><title>pic18f24j11-i</title>