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PIC18F24J11-I
Public Made by Adomby adom
Microchip Tech MICROCHIP, QFN-28-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownPIC18F24J11-I
Microchip Tech · MICROCHIP · QFN-28-EP(6x6)
PIC18F24J11-I from Microchip Tech, in a QFN-28-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RA2/AN2/VREF-/CVREF/C2INB | bidirectional | PORTA digital I/O with analog input 2, A/D reference voltage (low) input, comparator reference voltage output and comparator 2 input B. |
| 2 | RA3/AN3/VREF+/C1INB | bidirectional | PORTA digital I/O with analog input 3, A/D reference voltage (high) input and comparator 1 input B. |
| 3 | VDDCORE/VCAP | power_in | Core logic supply (VDDCORE, regulator disabled on LF parts) or external filter capacitor connection (VCAP, regulator enabled on F parts). |
| 4 | RA5/AN4/SS1/HLVDIN/RP2 | bidirectional | PORTA digital I/O with analog input 4, SPI slave select input, high/low-voltage detect input and remappable peripheral pin 2. |
| 5 | VSS1 | power_in | Ground reference for logic and I/O pins. |
| 6 | OSC1/CLKI/RA7 | bidirectional | Oscillator crystal input or external clock source input (ST in RC mode, CMOS otherwise); also digital I/O RA7, which is disabled when OSC1 is used for the clock function. |
| 7 | OSC2/CLKO/RA6 | bidirectional | Oscillator crystal output or CLKO (1/4 the OSC1 frequency in RC mode); also digital I/O RA6, which is disabled when OSC2 is used for the clock function. |
| 8 | RC0/T1OSO/T1CKI/RP11 | bidirectional | PORTC digital I/O with Timer1 oscillator output, Timer1/Timer3 external clock input and remappable peripheral pin 11. |
| 9 | RC1/T1OSI/RP12 | bidirectional | PORTC digital I/O with Timer1 oscillator input and remappable peripheral pin 12. |
| 10 | RC2/AN11/CTPLS/RP13 | bidirectional | PORTC digital I/O with analog input 11, CTMU pulse generator output and remappable peripheral pin 13. |
| 11 | RC3/SCK1/SCL1/RP14 | bidirectional | PORTC digital I/O with SPI/I2C synchronous serial clock input/output (MSSP1) and remappable peripheral pin 14. |
| 12 | RC4/SDI1/SDA1/RP15 | bidirectional | PORTC digital I/O with SPI data input, I2C data I/O (MSSP1) and remappable peripheral pin 15. |
| 13 | RC5/SDO1/RP16 | bidirectional | PORTC digital I/O with SPI data output (MSSP1) and remappable peripheral pin 16. |
| 14 | RC6/TX1/CK1/RP17 | bidirectional | PORTC digital I/O with EUSART1 asynchronous transmit, EUSART1 synchronous clock and remappable peripheral pin 17. |
| 15 | RC7/RX1/DT1/RP18 | bidirectional | PORTC digital I/O with EUSART1 asynchronous receive data input, synchronous data I/O and remappable peripheral pin 18. |
| 16 | VSS2 | power_in | Ground reference for logic and I/O pins. |
| 17 | VDD | power_in | Positive supply for peripheral digital logic and I/O pins. |
| 18 | RB0/AN12/INT0/RP3 | bidirectional | PORTB digital I/O (software-programmable weak pull-up) with analog input 12, external interrupt 0 and remappable peripheral pin 3. |
| 19 | RB1/AN10/RTCC/RP4 | bidirectional | PORTB digital I/O with analog input 10, real-time clock calendar output and remappable peripheral pin 4. |
| 20 | RB2/AN8/CTED1/REFO/RP5 | bidirectional | PORTB digital I/O with analog input 8, CTMU edge 1 input, reference output clock and remappable peripheral pin 5. |
| 21 | RB3/AN9/CTED2/RP6 | bidirectional | PORTB digital I/O with analog input 9, CTMU edge 2 input and remappable peripheral pin 6. |
| 22 | RB4/KBI0/RP7 | bidirectional | PORTB digital I/O with interrupt-on-change and remappable peripheral pin 7. |
| 23 | RB5/KBI1/RP8 | bidirectional | PORTB digital I/O with interrupt-on-change and remappable peripheral pin 8. |
| 24 | RB6/KBI2/PGC/RP9 | bidirectional | PORTB digital I/O with interrupt-on-change, ICSP clock input and remappable peripheral pin 9. |
| 25 | RB7/KBI3/PGD/RP10 | bidirectional | PORTB digital I/O with interrupt-on-change, In-Circuit Debugger/ICSP programming data pin and remappable peripheral pin 10. |
| 26 | MCLR | input | Master Clear input; active-low Reset to the device (Schmitt Trigger input). |
| 27 | RA0/AN0/C1INA/ULPWU/RP0 | bidirectional | PORTA digital I/O with analog input 0, comparator 1 input A, ultra low-power wake-up input and remappable peripheral pin 0. |
| 28 | RA1/AN1/C2INA/RP1 | bidirectional | PORTA digital I/O with analog input 1, comparator 2 input A and remappable peripheral pin 1. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-28-EP(6x6) |
| Category | Embedded Processors & Controllers |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage (F device, regulator enabled) | VDD | 2.15 | 3.6 | V | F part numbers; VDDCORE/VCAP connected to VSS through a low-ESR capacitor | 12 | |
| Operating frequency | 0 | 48 | MHz | DC, 48 MHz | 13 | ||
| Input voltage tolerance, digital-only pins | 5.5 | V | Pins used as digital-only inputs | 131 | |||
| VCAP/VDDCORE capacitor ESR | ESR | 5 | Ω | Regulator enabled (F devices); '< 5Ω' | 33 | ||
| VCAP/VDDCORE capacitor value | 10 | µF | Connected to ground, ceramic or tantalum | 33 | |||
| Flash program memory endurance | 10000 | cycles | Erase/write cycles minimum | 3 | |||
| Flash data retention | 20 | years | Flash program memory | 3 | |||
| Internal oscillator accuracy (tunable) | -1 | 0.15 | 1 | % | 31 kHz to 8 MHz; ±0.15% typical, ±1% max | 3 | |
| Sleep mode current | 105 | nA | Sleep mode, typical, 'currents down to' | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | ppa | create the 10-bit time base. 2: These pins are remappable. | 255 |
CAD (KiCad official)
- Symbol:
PIC18F24J11-I - Footprint:
Package_DFN_QFN:QFN-28-1EP_6x6mm_P0.65mm_EP4.8x4.8mm - 3D model: QFN-28-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
pic18f24j11-i-etched.step/pic18f24j11-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic18f24j11-i.step/pic18f24j11-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (536 pp, sha256
692546e94e6fefb6, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).