component
PIC18F14K22-E
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PIC18F14K22-E
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · QFN-20-EP(4x4)
PIC18F14K22-E from Microchip Tech, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RA3/MCLR/VPP | input | PORTA<3> digital input (only when MCLR functionality is disabled); active-low Master Clear with internal pull-up, or high-voltage programming input (VPP). |
| 2 | RC5/CCP1/P1A | bidirectional | Digital I/O; ECCP1 capture input or compare/PWM output (CCP1), or Enhanced CCP1 PWM output channel A (P1A). |
| 3 | RC4/C2OUT/P1B/SRNQ | bidirectional | Digital I/O; Comparator C2 output, Enhanced CCP1 PWM output channel B (P1B), or SR latch inverted output (SRNQ). |
| 4 | RC3/AN7/C12IN3-/P1C/PGM | bidirectional | Digital I/O; ADC channel 7, Comparator C1/C2 inverting input 3, Enhanced CCP1 PWM output channel C (P1C), or Low-Voltage ICSP programming enable (PGM) when LVP is enabled. |
| 5 | RC6/AN8/SS | bidirectional | Digital I/O; ADC channel 8, or SPI slave select input for the MSSP module (TTL input). |
| 6 | RC7/AN9/SDO | bidirectional | Digital I/O; ADC channel 9, or SPI data output from the MSSP module. |
| 7 | RB7/TX/CK | bidirectional | Digital I/O; EUSART asynchronous transmit output (TX) or EUSART synchronous clock input/output (CK). |
| 8 | RB6/SCK/SCL | bidirectional | Digital I/O; SPI clock input/output (SCK) or I2C clock input/output (SCL) for the MSSP module. |
| 9 | RB5/AN11/RX/DT | bidirectional | Digital I/O; ADC channel 11, EUSART asynchronous receive (RX), or EUSART synchronous data (DT). |
| 10 | RB4/AN10/SDI/SDA | bidirectional | Digital I/O; ADC channel 10, SPI data input (SDI), or I2C data I/O (SDA) for the MSSP module. |
| 11 | RC2/AN6/C12IN2-/P1D | bidirectional | Digital I/O; ADC channel 6, Comparator C1/C2 inverting input 2, or Enhanced CCP1 PWM output channel D (P1D). |
| 12 | RC1/AN5/C12IN1- | bidirectional | Digital I/O; ADC channel 5 or Comparator C1/C2 inverting input 1. |
| 13 | RC0/AN4/C2IN+ | bidirectional | Digital I/O; ADC channel 4 or Comparator C2 noninverting input. |
| 14 | RA2/AN2/C1OUT/T0CKI/INT2/SRQ | bidirectional | Digital I/O; ADC channel 2, Comparator C1 output, Timer0 external clock input (T0CKI), external interrupt 2 (INT2), or SR latch output (SRQ). |
| 15 | RA1/AN1/C12IN0-/VREF+/INT1/PGC | bidirectional | Digital I/O; ADC channel 1, Comparator C1/C2 inverting input 0, ADC and DAC reference voltage (high) input (VREF+), external interrupt 1 (INT1), or ICSP programming clock (PGC). |
| 16 | RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD | bidirectional | Digital I/O; ADC channel 0, DAC reference voltage output (CVREF/DAC1OUT), ADC and DAC reference voltage (low) input (VREF-), Comparator C1 noninverting input, external interrupt 0 (INT0), or ICSP programming data (PGD). |
| 17 | VSS | power_in | Ground reference for logic and I/O pins. |
| 18 | VDD | power_in | Positive supply for logic and I/O pins. |
| 19 | RA5/OSC1/CLKIN/T13CKI | bidirectional | Digital I/O; oscillator crystal input or external clock input (OSC1/CLKIN, ST buffer in RC mode), and Timer1/Timer3 external clock input (T13CKI). |
| 20 | RA4/AN3/OSC2/CLKOUT | bidirectional | Digital I/O; ADC channel 3, oscillator crystal output (OSC2) in crystal modes, or CLKOUT (instruction cycle clock, 1/4 of OSC1 frequency) in RC mode. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-20-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage on VDD pin with respect to VSS (PIC18F1XK22) | -0.3 | 6.5 | V | PIC18F1XK22 | 319 | ||
| Voltage on MCLR pin with respect to VSS | -0.3 | 9 | V | 319 | |||
| Voltage on all other pins with respect to VSS | -0.3 | V | Maximum is VDD + 0.3V | 319 | |||
| Ambient temperature under bias | -40 | 125 | °C | 319 | |||
| Storage temperature | -65 | 150 | °C | 319 | |||
| Maximum current on VSS pin | 85 | mA | -40°C ≤ TA ≤ +125°C, Extended | 319 | |||
| Maximum current on VDD pin | 85 | mA | -40°C ≤ TA ≤ +125°C, Extended | 319 | |||
| Maximum current sunk by all ports | 250 | mA | 319 | ||||
| Maximum current sourced by all ports | 250 | mA | 319 | ||||
| Maximum output current sunk by any I/O pin | 50 | mA | 319 | ||||
| Maximum output current sourced by any I/O pin | 50 | mA | 319 | ||||
| Clamp current, IK | IK | 20 | mA | VPIN < 0 or VPIN > VDD | 319 | ||
| Operating supply voltage VDD | VDD | 2.3 | 5.5 | V | FOSC ≤ 20 MHz | 324 | |
| Operating supply voltage VDD | VDD | 3 | 5.5 | V | FOSC ≤ 64 MHz, 85°C | 324 | |
| Operating ambient temperature range TA (extended) | TA | -40 | 125 | °C | Extended temperature | 320 | |
| RAM data retention voltage | VDR | 1.7 | V | Device in Sleep mode | 324 | ||
| VDD rise rate to ensure internal Power-on Reset signal | SVDD | 0.05 | V/ms | 324 | |||
| Power-down base current (IPD) | IPD | 17 | 55 | µA | VDD = 2.3V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive; +125°C | 332 | |
| Power-down base current (IPD) | IPD | 18 | 65 | µA | VDD = 3.0V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive; +125°C | 332 | |
| Power-down base current (IPD) | IPD | 20 | 80 | µA | VDD = 5.0V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive; +125°C | 332 | |
| Supply current IDD, RC_RUN (LFINTOSC) | IDD | 28 | 55 | µA | VDD = 2.3V, FOSC = 31 kHz (RC_RUN mode, LFINTOSC source); +125°C | 326 | |
| Supply current IDD, RC_RUN (LFINTOSC) | IDD | 32 | 75 | µA | VDD = 3.0V, FOSC = 31 kHz (RC_RUN mode, LFINTOSC source); +125°C | 326 | |
| Supply current IDD, RC_RUN (LFINTOSC) | IDD | 40 | 80 | µA | VDD = 5.0V, FOSC = 31 kHz (RC_RUN mode, LFINTOSC source); +125°C | 326 | |
| Supply current IDD, RC_RUN (HFINTOSC 1 MHz) | IDD | 0.45 | 0.55 | mA | -40°C to +125°C, VDD = 2.3V, FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) | 326 | |
| Supply current IDD, RC_RUN (HFINTOSC 1 MHz) | IDD | 0.6 | 0.82 | mA | -40°C to +125°C, VDD = 3.0V, FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) | 326 | |
| Supply current IDD, RC_RUN (HFINTOSC 1 MHz) | IDD | 0.8 | 1 | mA | -40°C to +125°C, VDD = 5.0V, FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) | 326 | |
| Supply current IDD, RC_RUN (HF-INTOSC 16 MHz) | IDD | 2.4 | 3.5 | mA | -40°C to +125°C, VDD = 2.3V, FOSC = 16 MHz (RC_RUN mode, HF-INTOSC source) | 326 | |
| Supply current IDD, RC_RUN (HF-INTOSC 16 MHz) | IDD | 3.5 | 4.6 | mA | -40°C to +125°C, VDD = 3.0V (RC_RUN mode, HF-INTOSC source) | 326 | |
| Supply current IDD, RC_RUN (HF-INTOSC 16 MHz) | IDD | 3.7 | 4.7 | mA | -40°C to +125°C, VDD = 5.0V (RC_RUN mode, HF-INTOSC source) | 326 | |
| External CLKIN frequency (EC, extended range devices) | FOSC | 48 | MHz | EC, ECIO Oscillator mode (Extended Range Devices); min printed as DC | 341 | ||
| Oscillator frequency, RC mode | FOSC | 4 | MHz | RC Oscillator mode; min printed as DC | 341 | ||
| Oscillator frequency, XT mode | FOSC | 0.1 | 4 | MHz | XT Oscillator mode | 341 | |
| Oscillator frequency, HS mode | FOSC | 4 | 25 | MHz | HS Oscillator mode | 341 | |
| Oscillator frequency, HS + PLL mode (extended range) | FOSC | 4 | 12 | MHz | HS + PLL Oscillator mode (Extended Range Devices) | 341 | |
| Oscillator frequency, LP mode | FOSC | 5 | 33 | kHz | LP Oscillator mode | 341 | |
| External CLKIN period (EC, extended range devices) | TOSC | 20.8 | ns | EC, ECIO Oscillator mode (Extended Range Devices) | 341 | ||
| HFINTOSC calibrated frequency tolerance | HFOSC | -2 | 2 | % | 0°C ≤ TA ≤ 60°C | 342 | |
| HFINTOSC calibrated frequency tolerance | HFOSC | -3 | 3 | % | 60°C ≤ TA ≤ +85°C | 342 | |
| HFINTOSC calibrated frequency tolerance | HFOSC | -5 | 5 | % | 342 | ||
| PLL oscillator frequency range (F10) | FOSC | 4 | 16 | MHz | VDD = 3.0-5.0V, -40°C to +85°C | 342 | |
| PLL oscillator frequency range (F10) | FOSC | 4 | 12 | MHz | VDD = 3.0-5.0V, 125°C | 342 | |
| PLL on-chip VCO system frequency (F11) | FSYS | 16 | 64 | MHz | VDD = 3.0-5.0V, -40°C to +85°C | 342 | |
| PLL on-chip VCO system frequency (F11) | FSYS | 16 | 48 | MHz | VDD = 3.0-5.0V, 125°C | 342 | |
| PLL start-up time (lock time) | trc | 2 | ms | 342 | |||
| CLKOUT stability (jitter) | CLK | -0.25 | 0.25 | % | 342 | ||
| Integral error | EIL | -2 | 2 | LSb | VREF = 3.0V | 347 | |
| Differential error | EDL | -1.5 | 1.5 | LSb | No missing codes, VREF = 3.0V | 347 | |
| Offset error | EOFF | -3 | 3 | LSb | VREF = 3.0V | 347 | |
| Gain error | EGN | -3 | 3 | LSb | VREF = 3.0V | 347 | |
| Recommended impedance of analog voltage source | ZAIN | 10 | kΩ | Can go higher if external 0.01 µF capacitor is present on input pin. | 347 | ||
| Thermal resistance junction to ambient, 20-pin QFN 4x4mm | JA | 43 | C/W | 20-pin QFN 4x4mm package | 338 | ||
| Thermal resistance junction to case, 20-pin QFN 4x4mm | JC | 5.3 | C/W | 20-pin QFN 4x4mm package | 338 | ||
| Maximum junction temperature | TJMAX | 150 | C | 338 |
CAD (KiCad official)
- Symbol:
PIC18F14K22-E - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
pic18f14k22-e-etched.step/pic18f14k22-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic18f14k22-e.step/pic18f14k22-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (387 pp, sha256
21f69d409798287f, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PIC18F14K22-E
**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · QFN-20-EP(4x4)
PIC18F14K22-E from Microchip Tech, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RA3/MCLR/VPP | input | PORTA<3> digital input (only when MCLR functionality is disabled); active-low Master Clear with internal pull-up, or high-voltage programming input (VPP). |
| 2 | RC5/CCP1/P1A | bidirectional | Digital I/O; ECCP1 capture input or compare/PWM output (CCP1), or Enhanced CCP1 PWM output channel A (P1A). |
| 3 | RC4/C2OUT/P1B/SRNQ | bidirectional | Digital I/O; Comparator C2 output, Enhanced CCP1 PWM output channel B (P1B), or SR latch inverted output (SRNQ). |
| 4 | RC3/AN7/C12IN3-/P1C/PGM | bidirectional | Digital I/O; ADC channel 7, Comparator C1/C2 inverting input 3, Enhanced CCP1 PWM output channel C (P1C), or Low-Voltage ICSP programming enable (PGM) when LVP is enabled. |
| 5 | RC6/AN8/SS | bidirectional | Digital I/O; ADC channel 8, or SPI slave select input for the MSSP module (TTL input). |
| 6 | RC7/AN9/SDO | bidirectional | Digital I/O; ADC channel 9, or SPI data output from the MSSP module. |
| 7 | RB7/TX/CK | bidirectional | Digital I/O; EUSART asynchronous transmit output (TX) or EUSART synchronous clock input/output (CK). |
| 8 | RB6/SCK/SCL | bidirectional | Digital I/O; SPI clock input/output (SCK) or I2C clock input/output (SCL) for the MSSP module. |
| 9 | RB5/AN11/RX/DT | bidirectional | Digital I/O; ADC channel 11, EUSART asynchronous receive (RX), or EUSART synchronous data (DT). |
| 10 | RB4/AN10/SDI/SDA | bidirectional | Digital I/O; ADC channel 10, SPI data input (SDI), or I2C data I/O (SDA) for the MSSP module. |
| 11 | RC2/AN6/C12IN2-/P1D | bidirectional | Digital I/O; ADC channel 6, Comparator C1/C2 inverting input 2, or Enhanced CCP1 PWM output channel D (P1D). |
| 12 | RC1/AN5/C12IN1- | bidirectional | Digital I/O; ADC channel 5 or Comparator C1/C2 inverting input 1. |
| 13 | RC0/AN4/C2IN+ | bidirectional | Digital I/O; ADC channel 4 or Comparator C2 noninverting input. |
| 14 | RA2/AN2/C1OUT/T0CKI/INT2/SRQ | bidirectional | Digital I/O; ADC channel 2, Comparator C1 output, Timer0 external clock input (T0CKI), external interrupt 2 (INT2), or SR latch output (SRQ). |
| 15 | RA1/AN1/C12IN0-/VREF+/INT1/PGC | bidirectional | Digital I/O; ADC channel 1, Comparator C1/C2 inverting input 0, ADC and DAC reference voltage (high) input (VREF+), external interrupt 1 (INT1), or ICSP programming clock (PGC). |
| 16 | RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD | bidirectional | Digital I/O; ADC channel 0, DAC reference voltage output (CVREF/DAC1OUT), ADC and DAC reference voltage (low) input (VREF-), Comparator C1 noninverting input, external interrupt 0 (INT0), or ICSP programming data (PGD). |
| 17 | VSS | power_in | Ground reference for logic and I/O pins. |
| 18 | VDD | power_in | Positive supply for logic and I/O pins. |
| 19 | RA5/OSC1/CLKIN/T13CKI | bidirectional | Digital I/O; oscillator crystal input or external clock input (OSC1/CLKIN, ST buffer in RC mode), and Timer1/Timer3 external clock input (T13CKI). |
| 20 | RA4/AN3/OSC2/CLKOUT | bidirectional | Digital I/O; ADC channel 3, oscillator crystal output (OSC2) in crystal modes, or CLKOUT (instruction cycle clock, 1/4 of OSC1 frequency) in RC mode. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-20-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage on VDD pin with respect to VSS (PIC18F1XK22) | | -0.3 | | 6.5 | V | PIC18F1XK22 | 319 |
| Voltage on MCLR pin with respect to VSS | | -0.3 | | 9 | V | | 319 |
| Voltage on all other pins with respect to VSS | | -0.3 | | | V | Maximum is VDD + 0.3V | 319 |
| Ambient temperature under bias | | -40 | | 125 | °C | | 319 |
| Storage temperature | | -65 | | 150 | °C | | 319 |
| Maximum current on VSS pin | | | | 85 | mA | -40°C ≤ TA ≤ +125°C, Extended | 319 |
| Maximum current on VDD pin | | | | 85 | mA | -40°C ≤ TA ≤ +125°C, Extended | 319 |
| Maximum current sunk by all ports | | | | 250 | mA | | 319 |
| Maximum current sourced by all ports | | | | 250 | mA | | 319 |
| Maximum output current sunk by any I/O pin | | | | 50 | mA | | 319 |
| Maximum output current sourced by any I/O pin | | | | 50 | mA | | 319 |
| Clamp current, IK | IK | | | 20 | mA | VPIN < 0 or VPIN > VDD | 319 |
| Operating supply voltage VDD | VDD | 2.3 | | 5.5 | V | FOSC ≤ 20 MHz | 324 |
| Operating supply voltage VDD | VDD | 3 | | 5.5 | V | FOSC ≤ 64 MHz, 85°C | 324 |
| Operating ambient temperature range TA (extended) | TA | -40 | | 125 | °C | Extended temperature | 320 |
| RAM data retention voltage | VDR | 1.7 | | | V | Device in Sleep mode | 324 |
| VDD rise rate to ensure internal Power-on Reset signal | SVDD | 0.05 | | | V/ms | | 324 |
| Power-down base current (IPD) | IPD | | 17 | 55 | µA | VDD = 2.3V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive; +125°C | 332 |
| Power-down base current (IPD) | IPD | | 18 | 65 | µA | VDD = 3.0V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive; +125°C | 332 |
| Power-down base current (IPD) | IPD | | 20 | 80 | µA | VDD = 5.0V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive; +125°C | 332 |
| Supply current IDD, RC_RUN (LFINTOSC) | IDD | | 28 | 55 | µA | VDD = 2.3V, FOSC = 31 kHz (RC_RUN mode, LFINTOSC source); +125°C | 326 |
| Supply current IDD, RC_RUN (LFINTOSC) | IDD | | 32 | 75 | µA | VDD = 3.0V, FOSC = 31 kHz (RC_RUN mode, LFINTOSC source); +125°C | 326 |
| Supply current IDD, RC_RUN (LFINTOSC) | IDD | | 40 | 80 | µA | VDD = 5.0V, FOSC = 31 kHz (RC_RUN mode, LFINTOSC source); +125°C | 326 |
| Supply current IDD, RC_RUN (HFINTOSC 1 MHz) | IDD | | 0.45 | 0.55 | mA | -40°C to +125°C, VDD = 2.3V, FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) | 326 |
| Supply current IDD, RC_RUN (HFINTOSC 1 MHz) | IDD | | 0.6 | 0.82 | mA | -40°C to +125°C, VDD = 3.0V, FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) | 326 |
| Supply current IDD, RC_RUN (HFINTOSC 1 MHz) | IDD | | 0.8 | 1 | mA | -40°C to +125°C, VDD = 5.0V, FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) | 326 |
| Supply current IDD, RC_RUN (HF-INTOSC 16 MHz) | IDD | | 2.4 | 3.5 | mA | -40°C to +125°C, VDD = 2.3V, FOSC = 16 MHz (RC_RUN mode, HF-INTOSC source) | 326 |
| Supply current IDD, RC_RUN (HF-INTOSC 16 MHz) | IDD | | 3.5 | 4.6 | mA | -40°C to +125°C, VDD = 3.0V (RC_RUN mode, HF-INTOSC source) | 326 |
| Supply current IDD, RC_RUN (HF-INTOSC 16 MHz) | IDD | | 3.7 | 4.7 | mA | -40°C to +125°C, VDD = 5.0V (RC_RUN mode, HF-INTOSC source) | 326 |
| External CLKIN frequency (EC, extended range devices) | FOSC | | | 48 | MHz | EC, ECIO Oscillator mode (Extended Range Devices); min printed as DC | 341 |
| Oscillator frequency, RC mode | FOSC | | | 4 | MHz | RC Oscillator mode; min printed as DC | 341 |
| Oscillator frequency, XT mode | FOSC | 0.1 | | 4 | MHz | XT Oscillator mode | 341 |
| Oscillator frequency, HS mode | FOSC | 4 | | 25 | MHz | HS Oscillator mode | 341 |
| Oscillator frequency, HS + PLL mode (extended range) | FOSC | 4 | | 12 | MHz | HS + PLL Oscillator mode (Extended Range Devices) | 341 |
| Oscillator frequency, LP mode | FOSC | 5 | | 33 | kHz | LP Oscillator mode | 341 |
| External CLKIN period (EC, extended range devices) | TOSC | 20.8 | | | ns | EC, ECIO Oscillator mode (Extended Range Devices) | 341 |
| HFINTOSC calibrated frequency tolerance | HFOSC | -2 | | 2 | % | 0°C ≤ TA ≤ 60°C | 342 |
| HFINTOSC calibrated frequency tolerance | HFOSC | -3 | | 3 | % | 60°C ≤ TA ≤ +85°C | 342 |
| HFINTOSC calibrated frequency tolerance | HFOSC | -5 | | 5 | % | | 342 |
| PLL oscillator frequency range (F10) | FOSC | 4 | | 16 | MHz | VDD = 3.0-5.0V, -40°C to +85°C | 342 |
| PLL oscillator frequency range (F10) | FOSC | 4 | | 12 | MHz | VDD = 3.0-5.0V, 125°C | 342 |
| PLL on-chip VCO system frequency (F11) | FSYS | 16 | | 64 | MHz | VDD = 3.0-5.0V, -40°C to +85°C | 342 |
| PLL on-chip VCO system frequency (F11) | FSYS | 16 | | 48 | MHz | VDD = 3.0-5.0V, 125°C | 342 |
| PLL start-up time (lock time) | trc | | | 2 | ms | | 342 |
| CLKOUT stability (jitter) | CLK | -0.25 | | 0.25 | % | | 342 |
| Integral error | EIL | -2 | | 2 | LSb | VREF = 3.0V | 347 |
| Differential error | EDL | -1.5 | | 1.5 | LSb | No missing codes, VREF = 3.0V | 347 |
| Offset error | EOFF | -3 | | 3 | LSb | VREF = 3.0V | 347 |
| Gain error | EGN | -3 | | 3 | LSb | VREF = 3.0V | 347 |
| Recommended impedance of analog voltage source | ZAIN | | | 10 | kΩ | Can go higher if external 0.01 µF capacitor is present on input pin. | 347 |
| Thermal resistance junction to ambient, 20-pin QFN 4x4mm | JA | | 43 | | C/W | 20-pin QFN 4x4mm package | 338 |
| Thermal resistance junction to case, 20-pin QFN 4x4mm | JC | | 5.3 | | C/W | 20-pin QFN 4x4mm package | 338 |
| Maximum junction temperature | TJMAX | | 150 | | C | | 338 |
## CAD (KiCad official)
- Symbol: `PIC18F14K22-E`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`
- 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `pic18f14k22-e-etched.step` / `pic18f14k22-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic18f14k22-e.step` / `pic18f14k22-e.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914084595585024) (387 pp, sha256 `21f69d409798287f`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pic18f14k22-e-datasheet.pdf)