# PIC16F883-I

**Microchip Tech** · Microcontrollers (MCU/MPU/SOC) · SSOP-28-208mil

PIC16F883-I from Microchip Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RE3/MCLR/VPP | input | General purpose input RE3, Master Clear (MCLR, Schmitt trigger, internal weak pull-up) or high-voltage programming input VPP. |
| 2 | RA0/AN0/ULPWU/C12IN0- | bidirectional | General purpose I/O RA0 (TTL) shared with A/D channel 0 input, Ultra Low-Power Wake-up input and comparator C1/C2 negative input C12IN0-. |
| 3 | RA1/AN1/C12IN1- | bidirectional | General purpose I/O RA1 (TTL) shared with A/D channel 1 input and comparator C1/C2 negative input C12IN1-. |
| 4 | RA2/AN2/VREF-/CVREF/C2IN+ | bidirectional | General purpose I/O RA2 (TTL) shared with A/D channel 2, A/D negative voltage reference input VREF-, comparator voltage reference output CVREF and comparator C2 positive input. |
| 5 | RA3/AN3/VREF+/C1IN+ | bidirectional | General purpose I/O RA3 (TTL) shared with A/D channel 3, A/D positive voltage reference input VREF+ and comparator C1 positive input. |
| 6 | RA4/T0CKI/C1OUT | bidirectional | General purpose I/O RA4 (TTL) shared with Timer0 clock input T0CKI (Schmitt trigger) and comparator C1 output (CMOS). |
| 7 | RA5/AN4/SS/C2OUT | bidirectional | General purpose I/O RA5 (TTL) shared with A/D channel 4, SPI Slave Select input SS (Schmitt trigger) and comparator C2 output. |
| 8 | VSS | power_in | Ground reference. |
| 9 | RA7/OSC1/CLKIN | bidirectional | General purpose I/O RA7 (TTL) shared with crystal/resonator connection OSC1 and external clock input/RC oscillator connection CLKIN. |
| 10 | RA6/OSC2/CLKOUT | bidirectional | General purpose I/O RA6 (TTL) shared with crystal/resonator connection OSC2 and FOSC/4 clock output CLKOUT. |
| 11 | RC0/T1OSO/T1CKI | bidirectional | General purpose I/O RC0 (Schmitt trigger) shared with Timer1 oscillator output T1OSO and Timer1 clock input T1CKI. |
| 12 | RC1/T1OSI/CCP2 | bidirectional | General purpose I/O RC1 (Schmitt trigger) shared with Timer1 oscillator input T1OSI and Capture/Compare/PWM2 CCP2. |
| 13 | RC2/P1A/CCP1 | bidirectional | General purpose I/O RC2 (Schmitt trigger) shared with enhanced PWM output P1A and Capture/Compare/PWM1 CCP1. |
| 14 | RC3/SCK/SCL | bidirectional | General purpose I/O RC3 (Schmitt trigger) shared with SPI clock SCK and I2C clock SCL (open-drain). |
| 15 | RC4/SDI/SDA | bidirectional | General purpose I/O RC4 (Schmitt trigger) shared with SPI data input SDI and I2C data input/output SDA (open-drain). |
| 16 | RC5/SDO | bidirectional | General purpose I/O RC5 (Schmitt trigger) shared with SPI data output SDO. |
| 17 | RC6/TX/CK | bidirectional | General purpose I/O RC6 (Schmitt trigger) shared with EUSART asynchronous transmit TX and EUSART synchronous clock CK. |
| 18 | RC7/RX/DT | bidirectional | General purpose I/O RC7 (Schmitt trigger) shared with EUSART asynchronous receive RX and EUSART synchronous data DT. |
| 19 | VSS | power_in | Ground reference. |
| 20 | VDD | power_in | Positive supply. |
| 21 | RB0/AN12/INT | bidirectional | General purpose I/O RB0 with individual interrupt-on-change and weak pull-up, shared with A/D channel 12 and external interrupt INT. |
| 22 | RB1/AN10/P1C/C12IN3- | bidirectional | General purpose I/O RB1 with individual interrupt-on-change and weak pull-up, shared with A/D channel 10, PWM output P1C and comparator C1/C2 negative input C12IN3-. |
| 23 | RB2/AN8/P1B | bidirectional | General purpose I/O RB2 with individual interrupt-on-change and weak pull-up, shared with A/D channel 8 and PWM output P1B. |
| 24 | RB3/AN9/PGM/C12IN2- | bidirectional | General purpose I/O RB3 with individual interrupt-on-change and weak pull-up, shared with A/D channel 9, low-voltage ICSP programming enable PGM and comparator C1/C2 negative input C12IN2-. |
| 25 | RB4/AN11/P1D | bidirectional | General purpose I/O RB4 with individual interrupt-on-change and weak pull-up, shared with A/D channel 11 and PWM output P1D. |
| 26 | RB5/AN13/T1G | bidirectional | General purpose I/O RB5 with individual interrupt-on-change and weak pull-up, shared with A/D channel 13 and Timer1 gate input T1G. |
| 27 | RB6/ICSPCLK | bidirectional | General purpose I/O RB6 with individual interrupt-on-change and weak pull-up, shared with the ICSP serial programming clock ICSPCLK. |
| 28 | RB7/ICSPDAT | bidirectional | General purpose I/O RB7 with individual interrupt-on-change and weak pull-up, shared with the ICSP data I/O ICSPDAT. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SSOP-28-208mil |
| Category | Embedded Processors & Controllers |
| Pins | 28 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias |  | -40 |  | 125 | °C |  | 239 |
| Storage temperature |  | -65 |  | 150 | °C |  | 239 |
| Voltage on VDD with respect to VSS |  | -0.3 |  | 6.5 | V |  | 239 |
| Voltage on MCLR with respect to Vss |  | -0.3 |  | 13.5 | V |  | 239 |
| Voltage on all other pins with respect to VSS |  | -0.3 |  |  | V | Printed maximum is VDD + 0.3V (not numeric) | 239 |
| Maximum current out of VSS pin |  |  |  | 95 | mA |  | 239 |
| Maximum current into VDD pin |  |  |  | 95 | mA |  | 239 |
| Input clamp current | IIK |  |  | 20 | mA | VI < 0 or VI > VDD | 239 |
| Output clamp current | IOK |  |  | 20 | mA | Vo < 0 or Vo > VDD | 239 |
| Maximum output current sunk by any I/O pin |  |  |  | 25 | mA |  | 239 |
| Maximum output current sourced by any I/O pin |  |  |  | 25 | mA |  | 239 |
| VDD Supply Voltage | VDD | 2 |  | 5.5 | V | FOSC <= 8 MHz: HFINTOSC, EC | 241 |
| VDD Supply Voltage | VDD | 3 |  | 5.5 | V | FOSC <= 10 MHz | 241 |
| VDD Supply Voltage | VDD | 4.5 |  | 5.5 | V | FOSC <= 20 MHz | 241 |
| RAM Data Retention Voltage | VDR | 1.5 |  |  | V | Device in Sleep mode | 241 |
| VDD Rise Rate to ensure internal Power-on Reset signal | SVDD | 0.05 |  |  | V/ms | See Section 14.2.1 Power-on Reset (POR) for details | 241 |
| Supply Current (IDD) | IDD |  | 13 | 19 | µA | FOSC = 32 kHz; LP Oscillator mode; VDD = 2.0V | 242 |
| Supply Current (IDD) | IDD |  | 22 | 30 | µA | FOSC = 32 kHz; LP Oscillator mode; VDD = 3.0V | 242 |
| Supply Current (IDD) | IDD |  | 33 | 60 | µA | FOSC = 32 kHz; LP Oscillator mode; VDD = 5.0V | 242 |
| Supply Current (IDD) | IDD |  | 280 | 380 | µA | FOSC = 4 MHz; XT Oscillator mode; VDD = 2.0V | 242 |
| Supply Current (IDD) | IDD |  | 480 | 670 | µA | FOSC = 4 MHz; XT Oscillator mode; VDD = 3.0V | 242 |
| Supply Current (IDD) | IDD |  | 0.9 | 1.4 | mA | FOSC = 4 MHz; XT Oscillator mode; VDD = 5.0V | 242 |
| Supply Current (IDD) | IDD |  | 8 | 20 | µA | FOSC = 31 kHz; LFINTOSC mode; VDD = 2.0V | 242 |
| Supply Current (IDD) | IDD |  | 16 | 40 | µA | FOSC = 31 kHz; LFINTOSC mode; VDD = 3.0V | 242 |
| Supply Current (IDD) | IDD |  | 31 | 65 | µA | FOSC = 31 kHz; LFINTOSC mode; VDD = 5.0V | 242 |
| Supply Current (IDD) | IDD |  | 0.65 | 0.9 | mA | FOSC = 8 MHz; HFINTOSC mode; VDD = 2.0V | 242 |
| Supply Current (IDD) | IDD |  | 1.01 | 1.3 | mA | FOSC = 8 MHz; HFINTOSC mode; VDD = 3.0V | 242 |
| Supply Current (IDD) | IDD |  | 1.86 | 2.3 | mA | FOSC = 8 MHz; HFINTOSC mode; VDD = 5.0V | 242 |
| Supply Current (IDD) | IDD |  | 3.8 | 4.7 | mA | FOSC = 20 MHz; HS Oscillator mode; VDD = 4.5V | 242 |
| Supply Current (IDD) | IDD |  | 4 | 4.8 | mA | FOSC = 20 MHz; HS Oscillator mode; VDD = 5.0V | 242 |
| Power-down Base Current (IPD) | IPD |  | 0.05 | 1.2 | µA | WDT, BOR, Comparators, VREF and T1OSC disabled; VDD = 2.0V | 243 |
| Power-down Base Current (IPD) | IPD |  | 0.15 | 1.5 | µA | WDT, BOR, Comparators, VREF and T1OSC disabled; VDD = 3.0V | 243 |
| Power-down Base Current (IPD) | IPD |  | 0.35 | 1.8 | µA | WDT, BOR, Comparators, VREF and T1OSC disabled; VDD = 5.0V | 243 |
| Power-down Base Current (IPD) | IPD |  | 150 | 500 | nA | -40°C <= TA <= +25°C; VDD = 3.0V | 243 |
| Input Low Voltage, I/O port with TTL buffer | VIL |  |  | 0.8 | V | 4.5V <= VDD <= 5.5V | 245 |
| Input Low Voltage, I/O port (TTL, low VDD) | VIL |  |  | 0.15 | x VDD | 2.0V <= VDD <= 4.5V | 245 |
| Input Low Voltage, I/O port with Schmitt Trigger buffer | VIL |  |  | 0.2 | x VDD | 2.0V <= VDD <= 5.5V | 245 |
| Input Low Voltage, MCLR, OSC1 (RC mode) | VIL |  |  | 0.2 | x VDD |  | 245 |
| Input Low Voltage, OSC1 (XT and LP modes) | VIL |  |  | 0.3 | V |  | 245 |
| Input Low Voltage, OSC1 (HS mode) | VIL |  |  | 0.3 | x VDD |  | 245 |
| Input High Voltage, I/O port with TTL buffer | VIH | 2 |  |  | V | 4.5V <= VDD <= 5.5V | 245 |
| Input High Voltage, I/O port with Schmitt Trigger buffer | VIH | 0.8 |  |  | x VDD | 2.0V <= VDD <= 5.5V | 245 |
| Input High Voltage, MCLR | VIH | 0.8 |  |  | x VDD |  | 245 |
| Input High Voltage, OSC1 (XT and LP modes) | VIH | 1.6 |  |  | V |  | 245 |
| Input High Voltage, OSC1 (HS mode) | VIH | 0.7 |  |  | x VDD |  | 245 |
| Input High Voltage, OSC1 (RC mode) | VIH | 0.9 |  |  | x VDD |  | 245 |
| Input Leakage Current, I/O ports | IIL |  | 0.1 | 1 | µA | VSS <= VPIN <= VDD, Pin at high-impedance | 245 |
| Input Leakage Current, MCLR | IIL |  | 0.1 | 5 | µA | VSS <= VPIN <= VDD | 245 |
| Input Leakage Current, OSC1 | IIL |  | 0.1 | 5 | µA | VSS <= VPIN <= VDD, XT, HS and LP oscillator configuration | 245 |
| PORTB Weak Pull-up Current | IPUR | 50 | 250 | 400 | µA | VDD = 5.0V, VPIN = VSS | 245 |
| Output Low Voltage, I/O ports | VOL |  |  | 0.6 | V | IOL = 8.5 mA, VDD = 4.5V (Ind.) | 245 |
| HFINTOSC Internal Calibrated Frequency, 1% tolerance | HFOSC | 7.92 | 8 | 8.08 | MHz | VDD = 3.5V, 25°C | 250 |
| HFINTOSC Internal Calibrated Frequency, 2% tolerance | HFOSC | 7.84 | 8 | 8.16 | MHz | 2.5V <= VDD <= 5.5V, 0°C <= TA <= +85°C | 250 |
| HFINTOSC Internal Calibrated Frequency, 5% tolerance | HFOSC | 7.6 | 8 | 8.4 | MHz | 2.0V <= VDD <= 5.5V, -40°C <= TA <= +85°C (Ind.), -40°C <= TA <= +125°C (Ext.) | 250 |
| Thermal Resistance Junction to Ambient | JA |  | 89.4 |  | C/W | 28-pin SSOP package | 247 |
| Thermal Resistance Junction to Case | JC |  | 23.9 |  | C/W | 28-pin SSOP package | 247 |
| Junction Temperature | TJ |  | 150 |  | C | For derated power calculations | 247 |

## CAD (KiCad official)

- Symbol: `PIC16F883-I`
- Footprint: `Package_SO:SSOP-28_5.3x10.2mm_P0.65mm`
- 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files: `pic16f883-i-etched.step` / `pic16f883-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pic16f883-i.step` / `pic16f883-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588882119301349376) (322 pp, sha256 `8cca4a12d17d06af`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pic16f883-i-datasheet.pdf)