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PIC16F876AT-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC16F876AT-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SOIC-28-300mil

PIC16F876AT-I from Microchip Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MCLR/VPP input Active-low Master Clear (Reset) input to the device through an ST buffer, which also serves as the programming voltage input (VPP).
2 RA0/AN0 bidirectional PORTA bidirectional digital I/O (TTL buffer) that also serves as analog input 0.
3 RA1/AN1 bidirectional PORTA bidirectional digital I/O (TTL buffer) that also serves as analog input 1.
4 RA2/AN2/VREF-/CVREF bidirectional PORTA bidirectional digital I/O (TTL buffer) that also serves as analog input 2, the A/D reference voltage (low) input, and the comparator VREF output.
5 RA3/AN3/VREF+ bidirectional PORTA bidirectional digital I/O (TTL buffer) that also serves as analog input 3 and the A/D reference voltage (high) input.
6 RA4/T0CKI/C1OUT bidirectional PORTA bidirectional digital I/O (ST buffer), open-drain when configured as an output, that also serves as the Timer0 external clock input and the Comparator 1 output.
7 RA5/AN4/SS/C2OUT bidirectional PORTA bidirectional digital I/O (TTL buffer) that also serves as analog input 4, the SPI slave select input, and the Comparator 2 output.
8 VSS power_in Ground reference for logic and I/O pins.
9 OSC1/CLKI input Oscillator crystal input or external clock source input (ST buffer in RC mode, otherwise CMOS).
10 OSC2/CLKO output Oscillator crystal output connecting to a crystal or resonator; in RC mode it outputs CLKO at 1/4 the OSC1 frequency, denoting the instruction cycle rate.
11 RC0/T1OSO/T1CKI bidirectional PORTC bidirectional digital I/O (ST buffer) that also serves as the Timer1 oscillator output and the Timer1 external clock input.
12 RC1/T1OSI/CCP2 bidirectional PORTC bidirectional digital I/O (ST buffer) that also serves as the Timer1 oscillator input and the CCP2 capture input / compare output / PWM output.
13 RC2/CCP1 bidirectional PORTC bidirectional digital I/O (ST buffer) that also serves as the CCP1 capture input / compare output / PWM output.
14 RC3/SCK/SCL bidirectional PORTC bidirectional digital I/O (ST buffer) that also serves as the synchronous serial clock input/output for SPI mode and for I2C mode.
15 RC4/SDI/SDA bidirectional PORTC bidirectional digital I/O (ST buffer) that also serves as the SPI data input and the I2C data I/O.
16 RC5/SDO bidirectional PORTC bidirectional digital I/O (ST buffer) that also serves as the SPI data output.
17 RC6/TX/CK bidirectional PORTC bidirectional digital I/O (ST buffer) that also serves as the USART asynchronous transmit output and the USART synchronous clock.
18 RC7/RX/DT bidirectional PORTC bidirectional digital I/O (ST buffer) that also serves as the USART asynchronous receive input and the USART synchronous data.
19 VSS power_in Ground reference for logic and I/O pins.
20 VDD power_in Positive supply for logic and I/O pins.
21 RB0/INT bidirectional PORTB bidirectional digital I/O (TTL/ST buffer, Schmitt trigger when used as external interrupt) with internal weak pull-up programmable, that also serves as the external interrupt input.
22 RB1 bidirectional PORTB bidirectional digital I/O (TTL buffer) with software-programmable internal weak pull-up.
23 RB2 bidirectional PORTB bidirectional digital I/O (TTL buffer) with software-programmable internal weak pull-up.
24 RB3/PGM bidirectional PORTB bidirectional digital I/O (TTL buffer) that also serves as the low-voltage (single-supply) ICSP programming enable pin.
25 RB4 bidirectional PORTB bidirectional digital I/O (TTL buffer) with software-programmable internal weak pull-up.
26 RB5 bidirectional PORTB bidirectional digital I/O (TTL buffer) with software-programmable internal weak pull-up.
27 RB6/PGC bidirectional PORTB bidirectional digital I/O (TTL/ST buffer) that also serves as the in-circuit debugger and ICSP programming clock.
28 RB7/PGD bidirectional PORTB bidirectional digital I/O (TTL/ST buffer) that also serves as the in-circuit debugger and ICSP programming data.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-28-300mil
Category Embedded Processors & Controllers
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 173
Storage temperature -65 150 °C 173
Voltage on VDD with respect to VSS VDD -0.3 7.5 V 173
Voltage on any pin with respect to VSS (except VDD, MCLR, RA4) -0.3 V max printed as VDD + 0.3V 173
Voltage on MCLR with respect to VSS MCLR 0 14 V Note 2 (latch-up; series resistor 50-100 ohm for low level) 173
Voltage on RA4 with respect to VSS RA4 0 8.5 V 173
Total power dissipation 1 W Note 1 173
Input clamp current IIK 20 mA VI < 0 or VI > VDD 173
Output clamp current IOK 20 mA VO < 0 or VO > VDD 173
VDD Supply Voltage VDD 4 5.5 V All configurations (PIC16F87XA, not LF) 175
VDD Rise Rate to ensure internal Power-on Reset signal SVDD 0.05 V/ms See Section 14.5 Power-on Reset 175
Brown-out Reset Voltage VBOR 3.65 4 4.35 V BODEN bit in configuration word enabled 175
Supply current, XT/RC oscillator configurations IDD 1.6 4 mA XT, RC osc configurations, FOSC = 4 MHz, VDD = 5.5V 176
Supply current, HS oscillator configuration IDD 7 15 mA HS osc configuration, FOSC = 20 MHz, VDD = 5.5V 176
Brown-out Reset current IBOR 85 200 µA BOR enabled, VDD = 5.0V 176
Power-down current, WDT enabled IPD 10.5 42 µA VDD = 4.0V, WDT enabled, -40°C to +85°C 177
Power-down current, WDT disabled IPD 1.5 16 µA VDD = 4.0V, WDT disabled, -40°C to +85°C 177
Power-down current, WDT disabled (D021A row) IPD 1.5 19 µA VDD = 4.0V, WDT disabled, -40°C to +85°C 177
Input low voltage, I/O ports with TTL buffer VIL 0.8 V 4.5V <= VDD <= 5.5V 178
Input low voltage, OSC1 (XT and LP modes) VIL 0.3 V OSC1 in XT and LP modes (Note 1) 178
Input low voltage, RC3/RC4 with SMBus VIL -0.5 0.6 V VDD = 4.5 to 5.5V 178
Input high voltage, I/O ports with TTL buffer VIH 2 V 4.5V <= VDD <= 5.5V; max printed as VDD 178
Input high voltage, OSC1 (XT and LP modes) VIH 1.6 V OSC1 in XT and LP modes (Note 1); max printed as VDD 178
Input high voltage, RC3/RC4 with SMBus VIH 1.4 5.5 V VDD = 4.5 to 5.5V 178
PORTB weak pull-up current IPURB 50 250 400 µA VDD = 5V, VPIN = VSS, -40°C TO +85°C 178
Input leakage current, I/O ports IIL 1 µA VSS <= VPIN <= VDD, pin at high-impedance 178
Input leakage current, MCLR and RA4/T0CKI IIL 5 µA VSS <= VPIN <= VDD 178
Input leakage current, OSC1 IIL 5 µA VSS <= VPIN <= VDD, XT, HS and LP osc configuration 178
Output low voltage, I/O ports VOL 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C 179
Output low voltage, OSC2/CLKO (RC osc config) VOL 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C 179
Open-drain high voltage, RA4 pin (characterized, not tested) VOD 8.5 V RA4 pin 179
Capacitive loading, OSC2 pin COSC2 15 pF XT, HS and LP modes when external clock drives OSC1 179
Capacitive loading, all I/O pins and OSC2 (RC mode) CIO 50 pF 179
Capacitive loading, SCL, SDA (I2C mode) CB 400 pF 179
Data EEPROM endurance ED 100 K E/W -40°C to +85°C 179
Data EEPROM erase/write cycle time TDEW 4 8 ms 179
Program Flash endurance EP 10 K E/W -40°C to +85°C 179
Program Flash erase/write cycle time TPEW 4 8 ms 179
VDD for read (Program Flash) VPR 5.5 V VMIN = min. operating voltage 179
Comparator input offset voltage VIOFF -10 5 10 mV 3.0V < VDD < 5.5V, -40°C < TA < +85°C 180
Comparator common mode rejection ratio (characterized, not tested) CMRR 55 dB 3.0V < VDD < 5.5V, -40°C < TA < +85°C 180
Comparator response time (F device) TRESP 150 400 ns One input at (VDD-1.5)/2, other transitions VSS to VDD (Note 1) 180
Comparator mode change to output valid TMC2OV 10 µs 180
Voltage reference settling time TSET 10 µs VRR = 1 and VR<3:0> transitions from 0000 to 1111 180
A/D resolution NR 10 bits VREF = VDD = 5.12V, VSS <= VAIN <= VREF 194
A/D reference voltage (VREF+ - VREF-) VREF 2 V 194
Recommended impedance of analog voltage source ZAIN 2.5 kΩ Note 4 194
A/D clock period (TAD), TOSC based TAD 1.6 µs TOSC based, VREF >= 3.0V 195
A/D clock period (TAD), A/D RC mode TAD 2 4 6 µs A/D RC mode 195
A/D acquisition time (amplifier settling minimum) TACQ 10 µs Minimum time is amplifier settling time; input changed by no more than 1 LSb from last sample (characterized, not tested) 195
Instruction cycle time TCY 200 ns TCY = 4/FOSC 182
External clock period (HS osc mode) 1 TOSC 50 ns HS osc mode 182

CAD (KiCad official)

  • Symbol: PIC16F876AT-I
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: pic16f876at-i-etched.step / pic16f876at-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic16f876at-i.step / pic16f876at-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (234 pp, sha256 94f1cb4c43edd96e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF