component
PIC16F876A-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownPIC16F876A-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SOIC-28-300mil
PIC16F876A-I from Microchip Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MCLR/VPP | input | Active-low Master Clear (Reset) input to the device; also the programming voltage input (VPP). |
| 2 | RA0/AN0 | bidirectional | Bidirectional digital I/O (TTL input buffer) with analog input 0. |
| 3 | RA1/AN1 | bidirectional | Bidirectional digital I/O (TTL input buffer) with analog input 1. |
| 4 | RA2/AN2/VREF-/CVREF | bidirectional | Bidirectional digital I/O (TTL input buffer) with analog input 2, A/D reference voltage (low) input, and comparator VREF output. |
| 5 | RA3/AN3/VREF+ | bidirectional | Bidirectional digital I/O (TTL input buffer) with analog input 3 and A/D reference voltage (high) input. |
| 6 | RA4/T0CKI/C1OUT | bidirectional | Bidirectional digital I/O (Schmitt Trigger input, open-drain when configured as output) with Timer0 external clock input and Comparator 1 output. |
| 7 | RA5/AN4/SS/C2OUT | bidirectional | Bidirectional digital I/O (TTL input buffer) with analog input 4, SPI slave select input, and Comparator 2 output. |
| 8 | VSS | power_in | Ground reference for logic and I/O pins. |
| 9 | OSC1/CLKI | input | Oscillator crystal input or external clock source input (ST buffer when configured in RC mode, otherwise CMOS). |
| 10 | OSC2/CLKO | output | Oscillator crystal output connecting to a crystal or resonator; in RC mode outputs CLKO at 1/4 the frequency of OSC1. |
| 11 | RC0/T1OSO/T1CKI | bidirectional | Bidirectional digital I/O (Schmitt Trigger input) with Timer1 oscillator output and Timer1 external clock input. |
| 12 | RC1/T1OSI/CCP2 | bidirectional | Bidirectional digital I/O (Schmitt Trigger input) with Timer1 oscillator input and Capture2 input / Compare2 output / PWM2 output. |
| 13 | RC2/CCP1 | bidirectional | Bidirectional digital I/O (Schmitt Trigger input) with Capture1 input, Compare1 output, or PWM1 output. |
| 14 | RC3/SCK/SCL | bidirectional | Bidirectional digital I/O (Schmitt Trigger input) with synchronous serial clock input/output for SPI mode or I2C mode. |
| 15 | RC4/SDI/SDA | bidirectional | Bidirectional digital I/O (Schmitt Trigger input) with SPI data in or I2C data I/O. |
| 16 | RC5/SDO | bidirectional | Bidirectional digital I/O (Schmitt Trigger input) with SPI data out. |
| 17 | RC6/TX/CK | bidirectional | Bidirectional digital I/O (Schmitt Trigger input) with USART asynchronous transmit or USART synchronous clock. |
| 18 | RC7/RX/DT | bidirectional | Bidirectional digital I/O (Schmitt Trigger input) with USART asynchronous receive or USART synchronous data. |
| 19 | VSS | power_in | Ground reference for logic and I/O pins. |
| 20 | VDD | power_in | Positive supply for logic and I/O pins. |
| 21 | RB0/INT | bidirectional | Bidirectional digital I/O (TTL/Schmitt Trigger input when configured as external interrupt) with external interrupt input; PORTB can be software-programmed for weak pull-ups. |
| 22 | RB1 | bidirectional | Bidirectional digital I/O (TTL input buffer) with software-programmable internal weak pull-up. |
| 23 | RB2 | bidirectional | Bidirectional digital I/O (TTL input buffer) with software-programmable internal weak pull-up. |
| 24 | RB3/PGM | bidirectional | Bidirectional digital I/O (TTL input buffer) that also serves as the low-voltage (single-supply) ICSP programming enable pin. |
| 25 | RB4 | bidirectional | Bidirectional digital I/O (TTL input buffer) with software-programmable internal weak pull-up. |
| 26 | RB5 | bidirectional | Bidirectional digital I/O (TTL input buffer) with software-programmable internal weak pull-up. |
| 27 | RB6/PGC | bidirectional | Bidirectional digital I/O (TTL/Schmitt Trigger input in serial programming mode) serving as in-circuit debugger and ICSP programming clock. |
| 28 | RB7/PGD | bidirectional | Bidirectional digital I/O (TTL/Schmitt Trigger input in serial programming mode) serving as in-circuit debugger and ICSP programming data. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-28-300mil |
| Category | Embedded Processors & Controllers |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias | -55 | 125 | °C | 173 | |||
| Storage temperature | -65 | 150 | °C | 173 | |||
| Voltage on any pin with respect to VSS (except VDD, MCLR, RA4) | -0.3 | V | Max printed as (VDD + 0.3V) | 173 | |||
| Voltage on VDD with respect to VSS | VDD | -0.3 | 7.5 | V | 173 | ||
| Voltage on MCLR with respect to VSS | MCLR | 0 | 14 | V | Note 2 | 173 | |
| Voltage on RA4 with respect to VSS | RA4 | 0 | 8.5 | V | 173 | ||
| Total power dissipation | Pdis | 1 | W | Note 1 | 173 | ||
| Input clamp current | IIK | 20 | mA | VI < 0 or VI > VDD | 173 | ||
| Output clamp current | IOK | 20 | mA | VO < 0 or VO > VDD | 173 | ||
| Supply voltage VDD (PIC16F876A, 5V device) | VDD | 4 | 5.5 | V | All configurations | 175 | |
| Operating temperature, industrial | TA | -40 | 85 | °C | Industrial range (-I) per Standard Operating Conditions | 175 | |
| Brown-out Reset voltage | VBOR | 3.65 | 4 | 4.35 | V | BODEN bit in configuration word enabled | 175 |
| VDD rise rate to ensure internal Power-on Reset signal | SVDD | 0.05 | V/ms | See Section 14.5 Power-on Reset (POR) | 175 | ||
| Supply current IDD, XT/RC oscillator | IDD | 1.6 | 4 | mA | XT, RC osc configurations, FOSC = 4 MHz, VDD = 5.5V | 176 | |
| Supply current IDD, HS oscillator | IDD | 7 | 15 | mA | HS osc configuration, FOSC = 20 MHz, VDD = 5.5V | 176 | |
| Brown-out Reset current | IBOR | 85 | 200 | µA | BOR enabled, VDD = 5.0V | 176 | |
| Power-down current IPD, WDT enabled | IPD | 10.5 | 42 | µA | VDD = 4.0V, WDT enabled, -40°C to +85°C | 177 | |
| Power-down current IPD, WDT disabled | IPD | 1.5 | 16 | µA | VDD = 4.0V, WDT disabled, -40°C to +85°C | 177 | |
| Power-down current IPD, WDT disabled (row D021A) | IPD | 1.5 | 19 | µA | VDD = 4.0V, WDT disabled, -40°C to +85°C | 177 | |
| Input low voltage, I/O ports with TTL buffer (D030A) | VIL | 0.8 | V | 4.5V ≤ VDD ≤ 5.5V | 178 | ||
| Input low voltage, OSC1 in XT and LP modes | VIL | 0.3 | V | Note 1 | 178 | ||
| Input high voltage, I/O ports with TTL buffer (D040) | VIH | 2 | V | 4.5V ≤ VDD ≤ 5.5V | 178 | ||
| Input high voltage, OSC1 in XT and LP modes | VIH | 1.6 | V | Note 1 | 178 | ||
| Input high voltage, Ports RC3 and RC4 with SMBus | VIH | 1.4 | 5.5 | V | For VDD = 4.5 to 5.5V | 178 | |
| Input leakage current, I/O ports | IIL | 1 | µA | VSS ≤ VPIN ≤ VDD, pin at high-impedance | 178 | ||
| Input leakage current, MCLR and RA4/T0CKI | IIL | 5 | µA | VSS ≤ VPIN ≤ VDD | 178 | ||
| PORTB weak pull-up current | IPURB | 50 | 250 | 400 | µA | VDD = 5V, VPIN = VSS, -40°C to +85°C | 178 |
| Output low voltage, I/O ports | VOL | 0.6 | V | IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C | 179 | ||
| Output low voltage, OSC2/CLKO (RC osc config) | VOL | 0.6 | V | IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C | 179 | ||
| Open-drain high voltage, RA4 pin | VOD | 8.5 | V | RA4 pin | 179 | ||
| Capacitive loading, all I/O pins and OSC2 (RC mode) | CIO | 50 | pF | All I/O pins and OSC2 (RC mode) | 179 | ||
| Capacitive loading, SCL and SDA (I2C mode) | CB | 400 | pF | SCL, SDA (I2C mode) | 179 | ||
| Data EEPROM erase/write cycle time | TDEW | 4 | 8 | ms | 179 | ||
| Program Flash erase/write cycle time | TPEW | 4 | 8 | ms | 179 | ||
| VDD for read, program Flash (maximum) | VPR | 5.5 | V | VMIN = min. operating voltage | 179 | ||
| VDD for erase/write, program Flash (maximum) | VDD | 5.5 | V | Using EECON to read/write, VMIN = min. operating voltage | 179 | ||
| Input offset voltage | VIOFF | -10 | 5 | 10 | mV | 3.0V < VDD < 5.5V, -40°C < TA < +85°C | 180 |
| Input common mode voltage | VICM | 0 | V | 3.0V < VDD < 5.5V, -40°C < TA < +85°C | 180 | ||
| Common mode rejection ratio | CMRR | 55 | dB | 3.0V < VDD < 5.5V, -40°C < TA < +85°C | 180 | ||
| Comparator response time (PIC16F87XA) | TRESP | 150 | 400 | ns | Note 1: one input at (VDD, 1.5)/2, other input transitions VSS to VDD | 180 | |
| Comparator mode change to output valid | TMC2OV | 10 | µs | 180 | |||
| Voltage reference settling time | TSET | 10 | µs | VRR = 1 and VR<3:0> transitions from 0000 to 1111 | 180 | ||
| A/D TAD minimum (TOSC based) | TAD | 1.6 | µs | TOSC based, VREF ≥ 3.0V | 195 | ||
| A/D integral linearity error | EIL | -1 | 1 | LSb | VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF | 194 | |
| A/D differential linearity error | EDL | -1 | 1 | LSb | VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF | 194 | |
| A/D offset error | EOFF | -2 | 2 | LSb | VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF | 194 | |
| A/D gain error | EGN | -1 | 1 | LSb | VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF | 194 | |
| Recommended impedance of analog voltage source | ZAIN | 2.5 | kΩ | Note 4 | 194 | ||
| VREF input current during VAIN acquisition | IREF | 5 | µA | During VAIN acquisition | 194 | ||
| VREF input current during A/D conversion cycle | IREF | 150 | µA | During A/D conversion cycle | 194 | ||
| Supply voltage VDR, RAM data retention | VDR | 1.5 | V | 175 | |||
| A/D conversion current (VDD) PIC16F87XA | IAD | 220 | µA | Average current consumption when A/D is on (Note 1) | 194 |
CAD (KiCad official)
- Symbol:
PIC16F876A-I - Footprint:
Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm - 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
- 3D model files:
pic16f876a-i-etched.step/pic16f876a-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic16f876a-i.step/pic16f876a-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (234 pp, sha256
94f1cb4c43edd96e, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).