component
PIC16F722AT-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownPIC16F722AT-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SSOP-28-208mil
PIC16F722AT-I from Microchip Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RE3/MCLR/VPP | input | General purpose input RE3, active-low Master Clear with internal weak pull up (MCLR), or high-voltage programming voltage input (VPP). |
| 2 | RA0/AN0/SS/VCAP | bidirectional | General purpose I/O RA0 with A/D channel 0 input, SPI Slave Select input (selectable location) and regulator filter capacitor pin VCAP (PIC16F722A/723A only). |
| 3 | RA1/AN1 | bidirectional | General purpose I/O RA1 or A/D channel 1 input. |
| 4 | RA2/AN2 | bidirectional | General purpose I/O RA2 or A/D channel 2 input. |
| 5 | RA3/AN3/VREF | bidirectional | General purpose I/O RA3, A/D channel 3 input or A/D voltage reference input. |
| 6 | RA4/CPS6/T0CKI | bidirectional | General purpose I/O RA4, capacitive sensing input 6 or Timer0 clock input. |
| 7 | RA5/AN4/CPS7/SS/VCAP | bidirectional | General purpose I/O RA5 with A/D channel 4 input, capacitive sensing input 7, Slave Select input (selectable location) and VCAP regulator filter capacitor pin (PIC16F722A/723A only). |
| 8 | VSS | power_in | Ground reference. |
| 9 | RA7/OSC1/CLKIN | bidirectional | General purpose I/O RA7, crystal/resonator connection OSC1 (LP, XT, HS modes) or external clock input CLKIN (EC mode). |
| 10 | RA6/OSC2/CLKOUT/VCAP | bidirectional | General purpose I/O RA6, crystal/resonator connection OSC2, FOSC/4 clock output CLKOUT or VCAP regulator filter capacitor pin (PIC16F722A/723A only). |
| 11 | RC0/T1OSO/T1CKI | bidirectional | General purpose I/O RC0, Timer1 oscillator output connection or Timer1 clock input. |
| 12 | RC1/T1OSI/CCP2 | bidirectional | General purpose I/O RC1, Timer1 oscillator input connection or Capture/Compare/PWM2 (CCP2 location selectable as RC1 or RB3). |
| 13 | RC2/CCP1 | bidirectional | General purpose I/O RC2 or Capture/Compare/PWM1. |
| 14 | RC3/SCK/SCL | bidirectional | General purpose I/O RC3, SPI clock (SCK) or I2C clock (SCL). |
| 15 | RC4/SDI/SDA | bidirectional | General purpose I/O RC4, SPI data input (SDI) or I2C data input/output (SDA). |
| 16 | RC5/SDO | bidirectional | General purpose I/O RC5 or SPI data output (SDO). |
| 17 | RC6/TX/CK | bidirectional | General purpose I/O RC6, USART asynchronous transmit (TX) or USART synchronous clock (CK). |
| 18 | RC7/RX/DT | bidirectional | General purpose I/O RC7, USART asynchronous receive (RX) or USART synchronous data (DT). |
| 19 | VSS | power_in | Ground reference. |
| 20 | VDD | power_in | Positive supply (1.8V-5.5V for PIC16F722A/723A). |
| 21 | RB0/AN12/CPS0/INT | bidirectional | General purpose I/O RB0 with interrupt-on-change and weak pull up, A/D channel 12 input, capacitive sensing input 0 or external interrupt. |
| 22 | RB1/AN10/CPS1 | bidirectional | General purpose I/O RB1 with interrupt-on-change and weak pull up, A/D channel 10 input or capacitive sensing input 1. |
| 23 | RB2/AN8/CPS2 | bidirectional | General purpose I/O RB2 with interrupt-on-change and weak pull up, A/D channel 8 input or capacitive sensing input 2. |
| 24 | RB3/AN9/CPS3/CCP2 | bidirectional | General purpose I/O RB3 with interrupt-on-change and weak pull up, A/D channel 9 input, capacitive sensing input 3 or CCP2 (selectable location). |
| 25 | RB4/AN11/CPS4 | bidirectional | General purpose I/O RB4 with interrupt-on-change and weak pull up, A/D channel 11 input or capacitive sensing input 4. |
| 26 | RB5/AN13/CPS5/T1G | bidirectional | General purpose I/O RB5 with interrupt-on-change and weak pull up, A/D channel 13 input, capacitive sensing input 5 or Timer1 gate input. |
| 27 | RB6/ICSPCLK | bidirectional | General purpose I/O RB6 with interrupt-on-change and weak pull up, or In-Circuit Serial Programming/Debug clock. |
| 28 | RB7/ICSPDAT | bidirectional | General purpose I/O RB7 with interrupt-on-change and weak pull up, or In-Circuit Serial Programming/Debug data I/O. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SSOP-28-208mil |
| Category | Embedded Processors & Controllers |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias | -40 | 125 | °C | 186 | |||
| Storage temperature | -65 | 150 | °C | 186 | |||
| Voltage on VDD with respect to VSS, PIC16F722A/723A | VDD | -0.3 | 6.5 | V | PIC16F722A/723A | 186 | |
| Voltage on VCAP pin with respect to VSS, PIC16F722A/723A | VCAP | -0.3 | 4 | V | PIC16F722A/723A | 186 | |
| Voltage on MCLR with respect to VSS | VMCLR | -0.3 | 9 | V | 186 | ||
| Maximum current out of VSS pin | IVSS | 95 | mA | 186 | |||
| Maximum current into VDD pin | IVDD | 70 | mA | 186 | |||
| Maximum output current sunk by any I/O pin | IOL | 25 | mA | 186 | |||
| Maximum output current sourced by any I/O pin | IOH | 25 | mA | 186 | |||
| Maximum current sourced by all ports, industrial | 140 | mA | -40°C ≤ TA ≤ +85°C for industrial | 186 | |||
| Operating temperature (industrial) | TA | -40 | 85 | °C | Standard Operating Conditions, industrial (-I) | 187 | |
| VDD supply voltage, FOSC ≤ 16 MHz HFINTOSC or EC | VDD | 1.8 | 5.5 | V | PIC16F722A/723A; FOSC ≤ 16 MHz: HFINTOSC, EC | 187 | |
| VDD supply voltage, FOSC ≤ 4 MHz | VDD | 1.8 | 5.5 | V | PIC16F722A/723A; FOSC ≤ 4 MHz | 187 | |
| VDD supply voltage, FOSC ≤ 20 MHz EC | VDD | 2.3 | 5.5 | V | PIC16F722A/723A; FOSC ≤ 20 MHz, EC | 187 | |
| VDD supply voltage, FOSC ≤ 20 MHz HS | VDD | 2.5 | 5.5 | V | PIC16F722A/723A; FOSC ≤ 20 MHz, HS | 187 | |
| RAM data retention voltage | VDR | 1.7 | V | PIC16F722A/723A; device in Sleep mode | 187 | ||
| Fixed voltage reference initial accuracy, VFVR = 1.024V | VFVR | -5.5 | 5.5 | % | VFVR = 1.024V, VDD ≥ 2.5V | 187 | |
| Fixed voltage reference initial accuracy, VFVR = 2.048V | VFVR | -5.5 | 5.5 | % | VFVR = 2.048V, VDD ≥ 2.5V | 187 | |
| Fixed voltage reference initial accuracy, VFVR = 4.096V | VFVR | -5.5 | 5.5 | % | VFVR = 4.096V, VDD ≥ 4.75V; -40°C ≤ TA ≤ 85°C | 187 | |
| VDD rise rate to ensure internal Power-on Reset signal | SVDD | 0.05 | V/ms | See Section 3.2 Power-on Reset | 187 | ||
| Power-down base current (IPD), 1.8V, Max at +85°C | IPD | 4.3 | 10.2 | µA | VDD 1.8V; WDT, BOR, FVR, and T1OSC disabled, all peripherals inactive | 191 | |
| Power-down base current (IPD), 3.0V, Max at +85°C | IPD | 5 | 10.5 | µA | VDD 3.0V; WDT, BOR, FVR, and T1OSC disabled, all peripherals inactive | 191 | |
| Power-down base current (IPD), 5.0V, Max at +85°C | IPD | 5.5 | 11.8 | µA | VDD 5.0V; WDT, BOR, FVR, and T1OSC disabled, all peripherals inactive | 191 | |
| Supply current (IDD), HFINTOSC 8 MHz, 1.8V | IDD | 625 | 850 | µA | FOSC = 8 MHz, HFINTOSC mode; VDD 1.8V | 190 | |
| Supply current (IDD), HFINTOSC 8 MHz, 3.0V | IDD | 1000 | 1200 | µA | FOSC = 8 MHz, HFINTOSC mode; VDD 3.0V | 190 | |
| Supply current (IDD), HFINTOSC 8 MHz, 5.0V | IDD | 1100 | 1500 | µA | FOSC = 8 MHz, HFINTOSC mode; VDD 5.0V | 190 | |
| Supply current (IDD), HFINTOSC 16 MHz, 1.8V | IDD | 1 | 1.2 | mA | FOSC = 16 MHz, HFINTOSC mode; VDD 1.8V | 190 | |
| Supply current (IDD), HFINTOSC 16 MHz, 3.0V | IDD | 1.5 | 1.7 | mA | FOSC = 16 MHz, HFINTOSC mode; VDD 3.0V | 190 | |
| Supply current (IDD), HFINTOSC 16 MHz, 5.0V | IDD | 1.7 | 2.1 | mA | FOSC = 16 MHz, HFINTOSC mode; VDD 5.0V | 190 | |
| Input low voltage, I/O with TTL buffer | VIL | 0.8 | V | With TTL buffer; 4.5V ≤ VDD ≤ 5.5V | 193 | ||
| Input low voltage, I/O with Schmitt Trigger buffer | VIL | 0.2 | ×VDD | With Schmitt Trigger buffer; 2.0V ≤ VDD ≤ 5.5V | 193 | ||
| Input high voltage, I/O with TTL buffer | VIH | 2 | V | With TTL buffer; 4.5V ≤ VDD ≤ 5.5V | 193 | ||
| Input high voltage, I/O with Schmitt Trigger buffer | VIH | 0.8 | ×VDD | With Schmitt Trigger buffer; 2.0V ≤ VDD ≤ 5.5V | 193 | ||
| Input high voltage, MCLR | VIH | 0.8 | ×VDD | MCLR | 193 | ||
| Input leakage current, MCLR | IIL | -200 | 200 | nA | VSS ≤ VPIN ≤ VDD, 85°C | 193 | |
| PORTB weak pull-up current, VDD 3.3V | IPUR | 25 | 100 | 200 | µA | VDD = 3.3V, VPIN = VSS | 193 |
| PORTB weak pull-up current, VDD 5.0V | IPUR | 25 | 140 | 300 | µA | VDD = 5.0V, VPIN = VSS | 193 |
| Output low voltage, I/O ports | VOL | 0.6 | V | IOL = 8 mA, VDD = 5V; IOL = 6 mA, VDD = 3.3V; IOL = 1.8 mA, VDD = 1.8V | 193 | ||
| Capacitive loading, OSC2 pin | COSC2 | 15 | pF | In XT, HS and LP modes when external clock is used to drive OSC1 | 193 | ||
| Capacitive loading, all I/O pins | CIO | 50 | pF | 193 | |||
| EP cell endurance | 100 | E/W | Temperature during programming: 10°C ≤ TA ≤ 40°C | 194 | |||
| Voltage on MCLR/VPP during erase/program | VPP | 8 | 9 | V | Temperature during programming: 10°C ≤ TA ≤ 40°C | 194 | |
| VDD for write or row erase | VPEW | 2.7 | V | VMIN = minimum operating voltage | 194 | ||
| Internal calibrated HFINTOSC frequency tolerance, 0°C to +85°C | HFOSC | -2 | 2 | % | 0°C ≤ TA ≤ +85°C, VDD ≥ 2.5V; 16.0 MHz nominal | 200 | |
| Internal calibrated HFINTOSC frequency tolerance, -40°C to +125°C | HFOSC | -5 | 5 | % | -40°C ≤ TA ≤ +125°C; 16.0 MHz nominal | 200 | |
| Instruction cycle time | TCY | 200 | ns | TCY = 4/FOSC | 199 | ||
| HFINTOSC wake-up from Sleep start-up time | TIOSC_ST | 5 | 8 | µs | 200 | ||
| MCLR pulse width (low) | TMCL | 2 | µs | VDD = 3.3-5V, -40°C to +85°C | 203 | ||
| Low power watchdog timer time-out period (no prescaler) | TWDTLP | 10 | 18 | 27 | ms | VDD = 3.3V-5V | 203 |
| Power-up timer period, PWRTE = 0 | TPWRT | 40 | 65 | 140 | ms | PWRTE = 0 | 203 |
| Brown-out Reset voltage, BORV = 2.5V | VBOR | 2.38 | 2.5 | 2.73 | V | BORV = 2.5V | 203 |
| Brown-out Reset voltage, BORV = 1.9V | VBOR | 1.8 | 1.9 | 2.11 | V | BORV = 1.9V | 203 |
| Timer1 oscillator input frequency range | FT1 | 32.4 | 32.768 | 33.1 | kHz | Oscillator enabled by setting bit T1OSCEN | 204 |
| A/D offset error | EOFF | -2.2 | 2.2 | LSb | VREF = 3.0V | 205 | |
| A/D gain error | EGN | -1.5 | 1.5 | LSb | VREF = 3.0V | 205 | |
| A/D reference voltage | VREF | 1.8 | V | Upper limit is VDD | 205 | ||
| Clock high to data-out valid (SYNC XMIT, master and slave) | TCKH2DTV | 80 | ns | 3.0-5.5V | 207 | ||
| Junction to ambient thermal resistance, 28-pin SSOP | θJA | 71 | °C/W | 28-pin SSOP package | 195 |
CAD (KiCad official)
- Symbol:
PIC16F722AT-I - Footprint:
Package_SO:SSOP-28_5.3x10.2mm_P0.65mm - 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files:
pic16f722at-i-etched.step/pic16f722at-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic16f722at-i.step/pic16f722at-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (266 pp, sha256
d3e10d8105bc1424, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).