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PIC16F72-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC16F72-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SOIC-28-300mil

PIC16F72-I from Microchip Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MCLR/VPP input Master Clear (Reset) input or programming voltage input; an active low RESET to the device, with ST input buffer.
2 RA0/AN0 bidirectional PORTA bit 0 bi-directional I/O with TTL input buffer; can also be analog input 0.
3 RA1/AN1 bidirectional PORTA bit 1 bi-directional I/O with TTL input buffer; can also be analog input 1.
4 RA2/AN2 bidirectional PORTA bit 2 bi-directional I/O with TTL input buffer; can also be analog input 2.
5 RA3/AN3/VREF bidirectional PORTA bit 3 bi-directional I/O with TTL input buffer; can also be analog input 3 or analog reference voltage.
6 RA4/T0CKI bidirectional PORTA bit 4 bi-directional I/O with Schmitt Trigger input; can also be the clock input to Timer0, and its output is open drain type.
7 RA5/AN4/SS bidirectional PORTA bit 5 bi-directional I/O with TTL input buffer; can also be analog input 4 or the slave select for the synchronous serial port.
8 VSS power_in Ground reference for logic and I/O pins.
9 OSC1/CLKI input Oscillator crystal input or external clock source input; buffer is Schmitt Trigger in RC oscillator mode and CMOS otherwise.
10 OSC2/CLKO output Oscillator crystal output connecting to a crystal or resonator in crystal oscillator mode; in RC mode it outputs CLKO at 1/4 the frequency of OSC1 denoting the instruction cycle rate.
11 RC0/T1OSO/T1CKI bidirectional PORTC bit 0 bi-directional I/O with Schmitt Trigger input; can also be the Timer1 oscillator output or Timer1 clock input.
12 RC1/T1OSI bidirectional PORTC bit 1 bi-directional I/O with Schmitt Trigger input; can also be the Timer1 oscillator input.
13 RC2/CCP1 bidirectional PORTC bit 2 bi-directional I/O with Schmitt Trigger input; can also be the Capture1 input, Compare1 output or PWM1 output.
14 RC3/SCK/SCL bidirectional PORTC bit 3 bi-directional I/O with Schmitt Trigger input; serves as the synchronous serial clock input/output for both SPI and I2C modes.
15 RC4/SDI/SDA bidirectional PORTC bit 4 bi-directional I/O with Schmitt Trigger input; serves as SPI Data In (SPI mode) or Data I/O (I2C mode).
16 RC5/SDO bidirectional PORTC bit 5 bi-directional I/O with Schmitt Trigger input; can also be the SPI Data Out (SPI mode).
17 RC6 bidirectional PORTC bit 6 bi-directional I/O with Schmitt Trigger input.
18 RC7 bidirectional PORTC bit 7 bi-directional I/O with Schmitt Trigger input.
19 VSS power_in Ground reference for logic and I/O pins.
20 VDD power_in Positive supply for logic and I/O pins.
21 RB0/INT bidirectional PORTB bit 0 bi-directional I/O with TTL input buffer, which becomes Schmitt Trigger when configured as the external interrupt; can also be the external interrupt pin.
22 RB1 bidirectional PORTB bit 1 bi-directional I/O with TTL input buffer; PORTB can be software programmed for internal weak pull-up on all inputs.
23 RB2 bidirectional PORTB bit 2 bi-directional I/O with TTL input buffer; PORTB can be software programmed for internal weak pull-up on all inputs.
24 RB3 bidirectional PORTB bit 3 bi-directional I/O with TTL input buffer; PORTB can be software programmed for internal weak pull-up on all inputs.
25 RB4 bidirectional PORTB bit 4 bi-directional I/O with TTL input buffer; interrupt-on-change pin, and PORTB can be software programmed for internal weak pull-up.
26 RB5 bidirectional PORTB bit 5 bi-directional I/O with TTL input buffer; interrupt-on-change pin, and PORTB can be software programmed for internal weak pull-up.
27 RB6/PGC bidirectional PORTB bit 6 bi-directional I/O with TTL input buffer (Schmitt Trigger in serial programming mode); interrupt-on-change pin and serial programming clock.
28 RB7/PGD bidirectional PORTB bit 7 bi-directional I/O with TTL input buffer (Schmitt Trigger in serial programming mode); interrupt-on-change pin and serial programming data.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-28-300mil
Category Embedded Processors & Controllers
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -55 125 °C 89
Storage temperature -65 150 °C 89
Voltage on any pin with respect to VSS (except VDD, MCLR, RA4) -0.3 V Upper limit printed as (VDD + 0.3V) 89
Voltage on VDD with respect to VSS -0.3 6.5 V 89
Voltage on MCLR with respect to VSS 0 13.5 V (Note 2) 89
Voltage on RA4 with respect to VSS 0 12 V 89
Total power dissipation 1 W (Note 1) 89
Input clamp current IIK -20 20 mA VI < 0 or VI > VDD 89
Output clamp current IOK -20 20 mA VO < 0 or VO > VDD 89
Operating temperature (industrial) TA -40 85 °C Industrial grade, Standard Operating Conditions 91
Supply voltage PIC16F72 VDD 4 5.5 V All configurations 91
Supply voltage with BOR enabled VBOR 5.5 V BOR enabled (Note 7) 91
VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 V/ms See section on Power-on Reset for details 91
Brown-out Reset voltage VBOR 3.65 4 4.35 V BOREN bit in configuration word enabled 91
Supply current (XT, RC oscillator) IDD 0.9 4 mA XT, RC osc configuration, FOSC = 4 MHz, VDD = 5.5V (Note 4) 92
Supply current (HS oscillator) IDD 5.2 15 mA HS osc configuration, FOSC = 20 MHz, VDD = 5.5V 92
Brown-out Reset current ∆IBOR 25 200 µA BOR enabled, VDD = 5.0V 92
Power-down current (WDT enabled) IPD 5 42 µA VDD = 4.0V, WDT enabled, -40°C to +85°C 92
Power-down current (WDT disabled) IPD 0.1 19 µA VDD = 4.0V, WDT disabled, -40°C to +85°C 92
Brown-out Reset current (parameter D023) ∆IBOR 25 200 µA BOR enabled, VDD = 5.0V 92
Input low voltage, TTL buffer VIL 0.8 V 4.5V ≤ VDD ≤ 5.5V 93
Input low voltage, OSC1 in XT and LP mode VIL 0.3 V XT and LP mode (Note 1) 93
Input high voltage, TTL buffer VIH 2 V 4.5V ≤ VDD ≤ 5.5V 93
Input high voltage, OSC1 in XT and LP mode VIH 1.6 V XT and LP mode (Note 1) 93
PORTB weak pull-up current IPURB 50 250 400 µA VDD = 5V, VPIN = VSS 93
Input leakage current, I/O ports IIL -1 1 µA Vss ≤ VPIN ≤ VDD, pin at hi-impedance 93
Input leakage current, MCLR and RA4/T0CKI IIL -5 5 µA Vss ≤ VPIN ≤ VDD 93
Input leakage current, OSC1 IIL -5 5 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc configuration 93
Output low voltage, I/O ports VOL 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C 94
Output low voltage, OSC2/CLKO (RC osc) VOL 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C 94
Open drain high voltage, RA4 pin VOD 12 V RA4 pin 94
OSC2 pin capacitive loading COSC2 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 94
All I/O pins and OSC2 capacitive loading (RC mode) CIO 50 pF All I/O pins and OSC2 (in RC mode) 94
SCL, SDA capacitive loading in I2C mode CB 400 pF SCL, SDA in I2C mode 94
Program FLASH endurance EP 100 1000 E/W 25°C at 5V 94
VDD for FLASH read VPR 2 5.5 V 94
A/D resolution NR 8 bits VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF 106
A/D total absolute error EABS -1 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF 106
A/D integral linearity error EIL -1 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF 106
A/D differential linearity error EDL -1 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF 106
A/D full scale error EFS -1 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF 106
A/D offset error EOFF -1 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF 106
A/D reference voltage VREF 2.5 V -40°C to +85°C 106
Recommended impedance of analog voltage source ZAIN 10 kΩ 106
VREF input current during VAIN acquisition IREF -5 5 µA During VAIN acquisition 106
VREF input current during A/D conversion cycle IREF 500 µA During A/D conversion cycle 106
Oscillator frequency, HS mode FOSC 4 20 MHz HS Osc mode 96
Instruction cycle time TCY 200 ns TCY = 4/FOSC 96
External clock in (OSC1) high or low time, HS oscillator TosL, TosH 15 ns HS oscillator 96
External clock in (OSC1) rise or fall time, HS oscillator TosR, TosF 15 ns HS oscillator 96

CAD (KiCad official)

  • Symbol: PIC16F72-I
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: pic16f72-i-etched.step / pic16f72-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic16f72-i.step / pic16f72-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (136 pp, sha256 2ac6ba557743ff80, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF