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PIC16F1947-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPIC16F1947-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
PIC16F1947-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RE1/P2C/VLCD2 | bidirectional | PORTE general-purpose I/O (ST input, CMOS output) with alternate P2C PWM output (APFCON-selectable) and VLCD2 LCD bias input. |
| 2 | RE0/P2D/VLCD1 | bidirectional | PORTE general-purpose I/O (ST input, CMOS output) with alternate P2D PWM output (APFCON-selectable) and VLCD1 LCD bias input. |
| 3 | RG0/CCP3/P3A/SEG42 | bidirectional | PORTG general-purpose I/O with CCP3 capture/compare/PWM, P3A PWM output and SEG42 LCD segment drive. |
| 4 | RG1/AN15/CPS15/TX2/CK2/C3OUT/SEG43 | bidirectional | PORTG general-purpose I/O with AN15 ADC input, CPS15 capacitive sense, USART2 TX/CK, C3OUT comparator output and SEG43 LCD segment. |
| 5 | RG2/AN14/CPS14/RX2/DT2/C3IN+/SEG44 | bidirectional | PORTG general-purpose I/O with AN14 ADC input, CPS14 capacitive sense, USART2 RX/DT, C3IN+ comparator input and SEG44 LCD segment. |
| 6 | RG3/AN13/CPS13/C3IN0-/CCP4/P3D/SEG45 | bidirectional | PORTG general-purpose I/O with AN13 ADC input, CPS13 capacitive sense, C3IN0- comparator input, CCP4, P3D PWM output and SEG45 LCD segment. |
| 7 | RG5/MCLR/VPP | input | Input-only pin (RG5); when MCLR is enabled it is the Master Clear input with internal pull-up, and VPP is the high-voltage programming pin. |
| 8 | RG4/AN12/CPS12/C3IN1-/CCP5/P1D/SEG26 | bidirectional | PORTG general-purpose I/O with AN12 ADC input, CPS12 capacitive sense, C3IN1- comparator input, CCP5, P1D PWM output and SEG26 LCD segment. |
| 9 | VSS | power_in | Ground reference for the device. |
| 10 | VDD | power_in | Positive supply voltage for the device. |
| 11 | RF7/AN5/CPS5/C123IN3-/SS1/SEG25 | bidirectional | PORTF general-purpose I/O with AN5 ADC input, CPS5 capacitive sense, comparator C1/C2/C3 IN3- inputs, SS1 slave select input and SEG25 LCD segment. |
| 12 | RF6/AN11/CPS11/C1IN+/SEG24 | bidirectional | PORTF general-purpose I/O with AN11 ADC input, CPS11 capacitive sense, C1IN+ comparator input and SEG24 LCD segment. |
| 13 | RF5/AN10/CPS10/C12IN1-/DACOUT/SEG23 | bidirectional | PORTF general-purpose I/O with AN10 ADC input, CPS10 capacitive sense, C1IN1-/C2IN1- comparator inputs, DACOUT voltage reference output and SEG23 LCD segment. |
| 14 | RF4/AN9/CPS9/C2IN+/SEG22 | bidirectional | PORTF general-purpose I/O with AN9 ADC input, CPS9 capacitive sense, C2IN+ comparator input and SEG22 LCD segment. |
| 15 | RF3/AN8/CPS8/C123IN2-/SEG21 | bidirectional | PORTF general-purpose I/O with AN8 ADC input, CPS8 capacitive sense, C1/C2/C3 IN2- comparator inputs and SEG21 LCD segment. |
| 16 | RF2/AN7/CPS7/C1OUT/SRQ/SEG20 | bidirectional | PORTF general-purpose I/O with AN7 ADC input, CPS7 capacitive sense, C1OUT comparator output, SR Latch non-inverting output SRQ and SEG20 LCD segment. |
| 17 | RF1/AN6/CPS6/C2OUT/SRNQ/SEG19 | bidirectional | PORTF general-purpose I/O with AN6 ADC input, CPS6 capacitive sense, C2OUT comparator output, SR Latch inverting output SRNQ and SEG19 LCD segment. |
| 18 | RF0/AN16/CPS16/C1IN0-/C2IN0-/SEG41/VCAP | bidirectional | PORTF general-purpose I/O with AN16 ADC input, CPS16 capacitive sense, C1IN0-/C2IN0- comparator inputs and SEG41 LCD segment; the datasheet also lists this pin as the VCAP voltage regulator filter capacitor connection. |
| 19 | AVDD | power_in | Dedicated power pin for the on-board analog circuits, to be connected to VDD or filtered separately in noisy designs. |
| 20 | AVSS | power_in | Dedicated ground pin for the on-board analog circuits, to be connected to VSS or filtered separately in noisy designs. |
| 21 | RA3/AN3/VREF+/CPS3/SEG35 | bidirectional | PORTA general-purpose I/O with AN3 ADC input, VREF+ A/D positive voltage reference input, CPS3 capacitive sense and SEG35 LCD segment. |
| 22 | RA2/AN2/VREF-/CPS2/SEG34 | bidirectional | PORTA general-purpose I/O with AN2 ADC input, VREF- A/D negative voltage reference input, CPS2 capacitive sense and SEG34 LCD segment. |
| 23 | RA1/AN1/CPS1/SEG18 | bidirectional | PORTA general-purpose I/O with AN1 ADC input, CPS1 capacitive sense and SEG18 LCD segment. |
| 24 | RA0/AN0/CPS0/SEG33 | bidirectional | PORTA general-purpose I/O with AN0 ADC input, CPS0 capacitive sense and SEG33 LCD segment. |
| 25 | VSS | power_in | Ground reference for the device. |
| 26 | VDD | power_in | Positive supply voltage for the device. |
| 27 | RA5/AN4/CPS4/SEG15 | bidirectional | PORTA general-purpose I/O with AN4 ADC input, CPS4 capacitive sense and SEG15 LCD segment. |
| 28 | RA4/T0CKI/SEG14 | bidirectional | PORTA general-purpose I/O with Timer0 clock input T0CKI (Schmitt trigger) and SEG14 LCD segment. |
| 29 | RC1/T1OSI/P2A/CCP2/SEG32 | bidirectional | PORTC general-purpose I/O with Timer1 oscillator input T1OSI, CCP2/P2A capture-compare-PWM (default location) and SEG32 LCD segment. |
| 30 | RC0/T1OSO/T1CKI/SEG40 | bidirectional | PORTC general-purpose I/O with Timer1 oscillator output T1OSO, Timer1 clock input T1CKI and SEG40 LCD segment. |
| 31 | RC6/TX1/CK1/SEG27 | bidirectional | PORTC general-purpose I/O with EUSART1 asynchronous transmit TX1, synchronous clock CK1 and SEG27 LCD segment. |
| 32 | RC7/RX1/DT1/SEG28 | bidirectional | PORTC general-purpose I/O with EUSART1 asynchronous receive RX1, synchronous data DT1 and SEG28 LCD segment. |
| 33 | RC2/CCP1/P1A/SEG13 | bidirectional | PORTC general-purpose I/O with CCP1 capture/compare/PWM, P1A PWM output and SEG13 LCD segment. |
| 34 | RC3/SCK1/SCL1/SEG17 | bidirectional | PORTC general-purpose I/O with MSSP1 SPI clock SCK1, I2C clock SCL1 (open-drain) and SEG17 LCD segment. |
| 35 | RC4/SDI1/SDA1/SEG16 | bidirectional | PORTC general-purpose I/O with MSSP1 SPI data input SDI1, I2C data SDA1 (open-drain) and SEG16 LCD segment. |
| 36 | RC5/SDO1/SEG12 | bidirectional | PORTC general-purpose I/O with MSSP1 SPI data output SDO1 and SEG12 LCD segment. |
| 37 | RB7/ICSPDAT/ICDDAT/SEG39 | bidirectional | PORTB general-purpose I/O with interrupt-on-change and weak pull-up, ICSP data ICSPDAT/ICDDAT for programming and debug, and SEG39 LCD segment. |
| 38 | VDD | power_in | Positive supply voltage for the device. |
| 39 | RA7/OSC1/CLKIN/SEG37 | bidirectional | PORTA general-purpose I/O; functions as OSC1 crystal/resonator input (LP, XT, HS) or CLKIN external clock input (EC) per oscillator configuration, and SEG37 LCD segment. |
| 40 | RA6/OSC2/CLKOUT/SEG36 | bidirectional | PORTA general-purpose I/O; functions as OSC2 crystal/resonator output (LP, XT, HS), CLKOUT FOSC/4 output, and SEG36 LCD segment. |
| 41 | VSS | power_in | Ground reference for the device. |
| 42 | RB6/ICSPCLK/ICDCLK/SEG38 | bidirectional | PORTB general-purpose I/O with interrupt-on-change and weak pull-up, ICSP clock ICSPCLK/ICDCLK for programming and debug, and SEG38 LCD segment. |
| 43 | RB5/T1G/SEG29 | bidirectional | PORTB general-purpose I/O with interrupt-on-change and weak pull-up, Timer1 gate input T1G and SEG29 LCD segment. |
| 44 | RB4/SEG11 | bidirectional | PORTB general-purpose I/O with interrupt-on-change and weak pull-up, and SEG11 LCD segment. |
| 45 | RB3/SEG10 | bidirectional | PORTB general-purpose I/O with interrupt-on-change and weak pull-up, and SEG10 LCD segment. |
| 46 | RB2/SEG9 | bidirectional | PORTB general-purpose I/O with interrupt-on-change and weak pull-up, and SEG9 LCD segment. |
| 47 | RB1/SEG8 | bidirectional | PORTB general-purpose I/O with interrupt-on-change and weak pull-up, and SEG8 LCD segment. |
| 48 | RB0/INT/SRI/FLT0/SEG30 | bidirectional | PORTB general-purpose I/O with interrupt-on-change and weak pull-up, external interrupt INT, SR Latch input SRI, ECCP auto-shutdown fault input FLT0 and SEG30 LCD segment. |
| 49 | RD7/SS2/SEG7 | bidirectional | PORTD general-purpose I/O with MSSP2 slave select input SS2 and SEG7 LCD segment. |
| 50 | RD6/SCK2/SCL2/P1B/SEG6 | bidirectional | PORTD general-purpose I/O with MSSP2 SPI clock SCK2 / I2C clock SCL2 (open-drain), P1B PWM output (alternate location) and SEG6 LCD segment. |
| 51 | RD5/SDI2/SDA2/P1C/SEG5 | bidirectional | PORTD general-purpose I/O with MSSP2 SPI data input SDI2, I2C data SDA2 (open-drain), P1C PWM output (alternate location) and SEG5 LCD segment. |
| 52 | RD4/SDO2/P3B/SEG4 | bidirectional | PORTD general-purpose I/O with MSSP2 SPI data output SDO2, P3B PWM output (alternate location) and SEG4 LCD segment. |
| 53 | RD3/P3C/SEG3 | bidirectional | PORTD general-purpose I/O with P3C PWM output (alternate location) and SEG3 LCD segment. |
| 54 | RD2/P2B/SEG2 | bidirectional | PORTD general-purpose I/O with P2B PWM output (alternate location) and SEG2 LCD segment. |
| 55 | RD1/P2C/SEG1 | bidirectional | PORTD general-purpose I/O with P2C PWM output (alternate location) and SEG1 LCD segment. |
| 56 | VSS | power_in | Ground reference for the device. |
| 57 | VDD | power_in | Positive supply voltage for the device. |
| 58 | RD0/P2D/SEG0 | bidirectional | PORTD general-purpose I/O with P2D PWM output (alternate location) and SEG0 LCD segment. |
| 59 | RE7/CCP2/P2A/SEG31 | bidirectional | PORTE general-purpose I/O with CCP2/P2A PWM output (alternate location via APFCON) and SEG31 LCD segment. |
| 60 | RE6/P1B/COM3 | bidirectional | PORTE general-purpose I/O (ST input, no CMOS output stage listed) with P1B PWM output (default location) and COM3 LCD common drive. |
| 61 | RE5/P1C/COM2 | bidirectional | PORTE general-purpose I/O with P1C PWM output (default location) and COM2 LCD common drive. |
| 62 | RE4/P3B/COM1 | bidirectional | PORTE general-purpose I/O with P3B PWM output (default location) and COM1 LCD common drive. |
| 63 | RE3/P3C/COM0 | bidirectional | PORTE general-purpose I/O with P3C PWM output (default location) and COM0 LCD common drive. |
| 64 | RE2/P2B/VLCD3 | bidirectional | PORTE general-purpose I/O with P2B PWM output (default location) and VLCD3 LCD bias input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage, FOSC <= 16 MHz (PIC16F) | VDD | 1.8 | 5.5 | V | FOSC <= 16 MHz | 380 | |
| VDD supply voltage, FOSC <= 32 MHz (PIC16F) | VDD | 2.5 | 5.5 | V | FOSC <= 32 MHz (Note 2, PLL required) | 380 | |
| VDD operating supply voltage, FOSC <= 16 MHz (Standard Operating Conditions) | VDDMIN | 2.3 | 5.5 | V | FOSC <= 16 MHz, PIC16F1946/47 | 377 | |
| Operating ambient temperature, industrial | TA | -40 | 85 | °C | Industrial temperature range | 377 | |
| Ambient temperature under bias | -40 | 125 | °C | 376 | |||
| Storage temperature | -65 | 150 | °C | 376 | |||
| Voltage on VDD with respect to VSS, PIC16F1946/47 | VDD | -0.3 | 6.5 | V | 376 | ||
| Voltage on VCAP pin with respect to VSS | VCAP | -0.3 | 4 | V | 376 | ||
| Voltage on MCLR with respect to VSS | MCLR | -0.3 | 9 | V | 376 | ||
| Voltage on all other pins with respect to VSS | -0.3 | V | Upper limit printed as VDD + 0.3V | 376 | |||
| Maximum current out of VSS pin, industrial | 350 | mA | -40°C <= TA <= +85°C | 376 | |||
| Maximum current into VDD pin, industrial | 350 | mA | -40°C <= TA <= +85°C | 376 | |||
| Clamp current | IK | 20 | mA | VPIN < 0 or VPIN > VDD | 376 | ||
| Data RAM retention voltage | VDR | 1.7 | V | Device in Sleep mode (PIC16F1946/47) | 380 | ||
| Fixed Voltage Reference voltage for ADC | VADFVR | -8 | 6 | % | 1.024V, VDD >= 2.5V; 2.048V, VDD >= 2.5V; 4.096V, VDD >= 4.75V | 380 | |
| Fixed Voltage Reference voltage for Comparator and DAC | VCDAFVR | -11 | 7 | % | 1.024V, VDD >= 2.5V; 2.048V, VDD >= 2.5V; 4.096V, VDD >= 4.75V | 380 | |
| Fixed Voltage Reference voltage for LCD bias, initial accuracy | VLCDFVR | -11 | 10 | % | 3.072V (VDD relation as printed unclear) | 380 | |
| VDD rise rate to ensure internal Power-on Reset signal | SVDD | 0.05 | V/ms | 380 | |||
| Input low voltage, I/O port with TTL buffer | VIL | 0.8 | V | 4.5V <= VDD <= 5.5V | 388 | ||
| Input low voltage, I/O port with SMBus levels | VIL | 0.8 | V | SMBus levels; 2.7V <= VDD <= 5.5V | 388 | ||
| Input high voltage, I/O port with TTL buffer | VIH | 2 | V | 4.5V <= VDD <= 5.5V | 388 | ||
| Input high voltage, I/O port with SMBus levels | VIH | 2.1 | V | SMBus levels; 2.7V <= VDD <= 5.5V | 388 | ||
| Input leakage current, I/O ports | IIL | -125 | 125 | nA | VSS <= VPIN <= VDD, pin at high-impedance @ 85°C | 388 | |
| Input leakage current, I/O ports | IIL | -1000 | 1000 | nA | VSS <= VPIN <= VDD, pin at high-impedance @ 125°C | 388 | |
| Input leakage current, MCLR | IIL | -200 | 200 | nA | VSS <= VPIN <= VDD @ 85°C | 388 | |
| Weak pull-up current | IPUR | 25 | 100 | 200 | µA | VDD = 3.3V, VPIN = VSS | 388 |
| Weak pull-up current | IPUR | 25 | 140 | 300 | µA | VDD = 5.0V, VPIN = VSS | 388 |
| Output low voltage, I/O ports | VOL | 0.6 | V | IOL = 8mA, VDD = 5V; IOL = 6mA, VDD = 3.3V; IOL = 1.8mA, VDD = 1.8V | 388 | ||
| Capacitive loading, OSC2 pin | COSC2 | 15 | pF | XT, HS and LP modes when external clock is used to drive OSC1 | 388 | ||
| Capacitive loading, all I/O pins | CIO | 50 | pF | 388 | |||
| HFINTOSC frequency tolerance | HFOSC | -2 | 2 | % | 0°C <= TA <= +60°C, VDD >= 2.5V (16.0 MHz) | 393 | |
| HFINTOSC frequency tolerance | HFOSC | -3 | 3 | % | 60°C <= TA <= +85°C, VDD >= 2.5V (16.0 MHz) | 393 | |
| HFINTOSC frequency tolerance | HFOSC | -5 | 5 | % | -40°C <= TA <= +125°C (16.0 MHz) | 393 | |
| HFINTOSC wake-up from Sleep start-up time | TIOSC ST | 3.2 | 8 | µs | 393 | ||
| MFINTOSC wake-up from Sleep start-up time | TIOSC ST | 24 | 35 | µs | 393 | ||
| Brown-out Reset voltage, BORV = 0 | VBOR | 2.55 | 2.7 | 2.85 | V | BORV = 0 | 396 |
| Brown-out Reset voltage, BORV = 1 | VBOR | 1.8 | 1.9 | 2.11 | V | BORV = 1 | 396 |
| MCLR pulse width (low) | TMCL | 2 | µs | 396 | |||
| Watchdog Timer time-out period | TWDTLP | 10 | 16 | 27 | ms | VDD = 3.3V-5V, 1:512 prescaler used | 396 |
| Power-up Timer period, PWRTE = 0 | TPWRT | 40 | 65 | 140 | ms | PWRTE = 0 | 396 |
| Brown-out Reset hysteresis | VHYST | 0 | 25 | 50 | mV | -40°C to +85°C | 396 |
| Comparator input offset voltage | VIOFF | -60 | 7.5 | 60 | mV | High-Power mode; VICM = VDD/2 | 401 |
| Comparator response time, rising edge | TRESP | 400 | 800 | ns | High-Power mode | 401 | |
| Comparator response time, falling edge | TRESP | 200 | 400 | ns | High-Power mode | 401 | |
| Comparator mode change to output valid | TMC2OV | 10 | µs | 401 | |||
| DAC settling time | CST | 10 | µs | Settling time measured while DACR<4:0> transitions from 0000 to 1111 | 401 | ||
| ADC integral error | EIL | -1.7 | 1.7 | LSb | VREF = 3.0V | 398 | |
| ADC clock period (TOSC-based) | TAD | 1 | 9 | µs | TOSC-based | 399 | |
| Junction to ambient thermal resistance, 64-pin TQFP | JA | 48.3 | °C/W | 64-pin TQFP package | 390 | ||
| Junction to case thermal resistance, 64-pin TQFP | JC | 26.1 | °C/W | 64-pin TQFP package | 390 | ||
| Maximum junction temperature | TJMAX | 150 | °C | 390 | |||
| VCAP capacitor charging current | 200 | µA | 388 | ||||
| VCAP source/sink capability when charging complete | 0 | mA | 388 |
CAD (KiCad official)
- Symbol:
PIC16F1947-I - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
pic16f1947-i-etched.step/pic16f1947-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic16f1947-i.step/pic16f1947-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (459 pp, sha256
dea7e85cc0343ade, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).