Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

PIC16F1847T-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · SOIC-18-300mil

PIC16F1847T-I from Microchip Tech, in a SOIC-18-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RA2 bidirectional RA2 general purpose I/O (TTL in, CMOS out) shared with AN2, CPS2, C12IN2-, C12IN+, VREF- and DACOUT.
2 RA3 bidirectional RA3 general purpose I/O shared with AN3, CPS3, C12IN3-, C1IN+, VREF+, C1OUT, CCP3 and SRQ.
3 RA4 bidirectional RA4 general purpose I/O shared with AN4, CPS4, C2OUT, T0CKI, CCP4 and SRNQ.
4 RA5/MCLR/VPP input Input-only RA5 pin that serves as Master Clear (MCLR, with internal weak pull-up), VPP programming voltage input, or SS1 slave select input.
5 VSS power_in Ground reference.
6 RB0 bidirectional RB0 general purpose I/O with interrupt-on-change and weak pull-up, shared with T1G, CCP1/P1A, INT, SRI and FLT0.
7 RB1 bidirectional RB1 general purpose I/O with interrupt-on-change and weak pull-up, shared with AN11, CPS11, RX/DT, SDA1 and SDI1.
8 RB2 bidirectional RB2 general purpose I/O with interrupt-on-change and weak pull-up, shared with AN10, CPS10, MDMIN, TX/CK, RX/DT, SDA2, SDI2 and SDO1.
9 RB3 bidirectional RB3 general purpose I/O with interrupt-on-change and weak pull-up, shared with AN9, CPS9, MDOUT and CCP1/P1A.
10 RB4 bidirectional RB4 general purpose I/O with interrupt-on-change and weak pull-up, shared with AN8, CPS8, SCL1/SCK1 and MDCIN2.
11 RB5 bidirectional RB5 general purpose I/O with interrupt-on-change and weak pull-up, shared with AN7, CPS7, P1B, TX/CK, SCL2/SCK2 and SS1.
12 RB6/ICSPCLK bidirectional RB6 general purpose I/O with interrupt-on-change and weak pull-up, shared with AN5, CPS5, T1CKI, T1OSI, P1C, CCP2, P2A and the ICSP serial programming clock input.
13 RB7/ICSPDAT bidirectional RB7 general purpose I/O with interrupt-on-change and weak pull-up, shared with AN6, CPS6, T1OSO, P1D, P2B, MDCIN1 and the ICSP data I/O.
14 VDD power_in Positive supply (1.8V-5.5V for PIC16F1847).
15 RA6 bidirectional RA6 general purpose I/O shared with OSC2 (crystal), CLKOUT (FOSC/4), CLKR, P1D, P2B and SDO1.
16 RA7 bidirectional RA7 general purpose I/O shared with OSC1 (crystal), CLKIN (external clock), P1C, CCP2 and P2A.
17 RA0 bidirectional RA0 general purpose I/O shared with AN0, CPS0, C12IN0- and SDO2.
18 RA1 bidirectional RA1 general purpose I/O shared with AN1, CPS1, C12IN1- and SS2.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-18-300mil
Category Single Chip Microcomputer/Microcontroller
Pins 18

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (FOSC ≤ 16 MHz) VDD 1.8 5.5 V FOSC ≤ 16 MHz 329
Supply Voltage (FOSC ≤ 32 MHz) VDD 2.5 5.5 V FOSC ≤ 32 MHz (Note 2) 329
Operating Ambient Temperature, Industrial TA -40 85 °C Industrial Temperature 327
Ambient temperature under bias -40 125 °C 326
Storage temperature -65 150 °C 326
Voltage on VDD pin with respect to VSS VDD -0.3 6.5 V Printed as PIC16F1827 326
Voltage on MCLR pin with respect to VSS MCLR -0.3 9 V 326
Maximum current on VSS pin 170 mA -40°C ≤ TA ≤ +85°C 326
Maximum current on VDD pin 170 mA -40°C ≤ TA ≤ +85°C 326
Maximum current on any I/O pin 25 mA 326
Clamp current IK 20 mA VPIN < 0 or VPIN > VDD 326
RAM Data Retention Voltage VDR 1.7 V Device in Sleep mode 329
FVR Gain Voltage Accuracy for ADC VADFVR -8 6 % 1x VFVR, VDD ≥ 2.5V; 2x VFVR, VDD ≥ 2.5V; 4x VFVR, VDD ≥ 4.75V 329
FVR Gain Voltage Accuracy for Comparator and DAC VCDAFVR -11 7 % 1x VFVR, VDD ≥ 2.5V; 2x VFVR, VDD ≥ 2.5V; 4x VFVR, VDD ≥ 4.75V 329
VDD Rise Rate SVDD 0.05 V/ms Ensures that the Power-on Reset signal is released properly. 329
Fixed Voltage Reference Voltage VFVR 1.024 V -40°C ≤ TA ≤ +85°C 329
Power-on Reset Release Voltage VPOR 1.6 V 329
Power-on Reset Rearm Voltage VPORR 1.4 V 329
Supply Current, LP oscillator IDD 22 29 µA VDD = 1.8V, FOSC = 32 kHz LP Oscillator, -40°C ≤ TA ≤ +85°C 331
Supply Current, LP oscillator IDD 30 38 µA VDD = 5.0V, FOSC = 32 kHz LP Oscillator, -40°C ≤ TA ≤ +85°C 331
Supply Current, HFINTOSC 8 MHz IDD 1.55 1.8 mA VDD = 5.0V, FOSC = 8 MHz HFINTOSC 332
Supply Current, HFINTOSC 16 MHz IDD 2.3 2.6 mA VDD = 5.0V, FOSC = 16 MHz HFINTOSC 332
Supply Current, HFINTOSC 32 MHz IDD 4.2 4.3 mA VDD = 5.0V, FOSC = 32 MHz HFINTOSC (Note 3) 333
Power-Down Current, Sleep IPD 18 40 µA VDD = 3.0V, WDT, BOR and T1OSC disabled, all Peripherals Inactive; max at +85°C 334
Power-Down Current, Sleep IPD 19 45 µA VDD = 5.0V, WDT, BOR and T1OSC disabled, all Peripherals Inactive; max at +85°C 334
Input Low Voltage, TTL buffer VIL 0.8 V 4.5V ≤ VDD ≤ 5.5V 336
Input Low Voltage, SMBus levels VIL 0.8 V 2.7V ≤ VDD ≤ 5.5V 336
Input High Voltage, TTL buffer VIH 2 V 4.5V ≤ VDD ≤ 5.5V 336
Input High Voltage, SMBus levels VIH 2.1 V 2.7V ≤ VDD ≤ 5.5V 336
Input Leakage Current, I/O ports IIL -125 125 nA VSS ≤ VPIN ≤ VDD, Pin at high impedance at 85°C 336
Input Leakage Current, MCLR IIL -200 200 nA VSS ≤ VPIN ≤ VDD, Pin at high impedance at 85°C 336
Weak Pull-up Current IPUR 25 100 200 µA VDD = 3.3V, VPIN = VSS 336
Weak Pull-up Current IPUR 25 140 300 µA VDD = 5.0V, VPIN = VSS 336
Output Low Voltage, I/O ports VOL 0.6 V IOL = 8 mA, VDD = 5V; IOL = 6 mA, VDD = 3.3V; IOL = 1.8 mA, VDD = 1.8V 336
OSC2 pin capacitive loading COSC2 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 336
All I/O pins capacitive loading CIO 50 pF 336
Voltage on MCLR/VPP pin VIHH 8 9 V (Note 3) 337
Supply Current during Programming IDDP 10 mA 337
VDD for Bulk Erase VBE 2.7 V Max is VDDMAX 337
Data EEPROM Erase/Write Cycle Time TDEW 4 5 ms 337
Program Flash Self-timed Write Cycle Time TIW 2 2.5 ms 337
Thermal Resistance Junction to Ambient θJA 76 °C/W 18-pin SOIC package 338
Thermal Resistance Junction to Case θJC 23.5 °C/W 18-pin SOIC package 338
Maximum Junction Temperature TJMAX 150 °C 338
Brown-out Reset Voltage VBOR 2.55 2.7 2.85 V BORV = 0 345
Brown-out Reset Voltage VBOR 1.8 1.9 2.05 V BORV = 1 345
Power-up Timer Period TPWRT 58 74 92 ms PWRTE = 0 345
Integral Error EIL -1.7 1 1.7 LSb VREF = 3.0V 348
Offset Error EOFF -2.5 1 2.5 LSb VREF = 3.0V 348
Gain Error EGN -2 1 2 LSb VREF = 3.0V 348
ADC Reference Voltage VREF 1.8 V VREF = (VREF+ minus VREF-) 348
ADC Resolution NR 10 bit 348
Comparator Input Offset Voltage VIOFF -60 7.5 60 mV CxSP = 1, VICM = VDD/2 350
PLL Oscillator Frequency Range FOSC 4 8 MHz 2.7V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ +125°C 342
Internal Calibrated HFINTOSC Frequency HFOSC 16 MHz 0°C ≤ TA ≤ +60°C, VDD ≥ 2.5V, 2% tolerance 341

CAD (KiCad official)

  • Symbol: PIC16F1847T-I
  • Footprint: Package_SO:SOIC-18W_7.5x11.6mm_P1.27mm
  • 3D model: SOIC-18-300mil (KiCad packages3D, STEP)
  • 3D model files: pic16f1847t-i-etched.step / pic16f1847t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic16f1847t-i.step / pic16f1847t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (418 pp, sha256 30902786092b180c, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF