PIC16F1824-I/SL

{
  "slug": "pic16f1824-i-sl",
  "version": "0.2.1",
  "type": "component",
  "description": "Microchip Microcontrollers (MCU/MPU/SOC), SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "mcu",
    "pic16f1824-i"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "pic16f1824-i.kicad_sym",
    "pic16f1824-i.kicad_mod",
    "pic16f1824-i.glb",
    "pic16f1824-i.step",
    "pic16f1824-i-etched.step",
    "pic16f1824-i.lbr",
    "docs/hero.png",
    "docs/pic16f1824-i-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pads.json",
    "pic16f1824-i-etched.glb",
    "pic16f1824-i-sl-hero.glb",
    "pic16f1824-i-sl-hero.overlay.json"
  ],
  "component": {
    "mpn": "PIC16F1824-I/SL",
    "manufacturer": "Microchip",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "MCU",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/88d81547f5cf4afda59e76928edcf0c2.pdf",
    "parts": {
      "symbol": "pic16f1824-i.kicad_sym",
      "footprint": "pic16f1824-i.kicad_mod",
      "model_3d": "pic16f1824-i-sl-hero.glb",
      "model_3d_plain": "pic16f1824-i.glb",
      "model_3d_step": "pic16f1824-i-etched.step",
      "model_3d_step_plain": "pic16f1824-i.step",
      "lbr": "pic16f1824-i.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply voltage. 1.8V to 5.5V for PIC16F1824; 1.8V to 3.6V for PIC16LF1824. Decouple with 0.1 µF to VSS."
      },
      {
        "number": "2",
        "name": "RA5/T1CKI/T1OSI/CCP2/P2A/OSC1/CLKIN",
        "type": "bidirectional",
        "description": "PORTA bit 5. Digital I/O with weak pull-up and interrupt-on-change. Muxed functions: Timer1 clock input (T1CKI), Timer1 oscillator input (T1OSI), CCP2/P2A PWM, primary oscillator input (OSC1/CLKIN)."
      },
      {
        "number": "3",
        "name": "RA4/AN3/CPS3/T1G/T1OSO/P2B/SDO/OSC2/CLKOUT/CLKR",
        "type": "bidirectional",
        "description": "PORTA bit 4. Digital I/O with weak pull-up and IOC. Muxed: ADC channel AN3, CapSense CPS3, Timer1 gate/oscillator output, ECCP P2B PWM, MSSP SDO, oscillator output OSC2/CLKOUT, reference clock output."
      },
      {
        "number": "4",
        "name": "RA3/T1G/SS/MCLR/VPP",
        "type": "input",
        "description": "PORTA bit 3, input only (no digital output driver). Doubles as Master Clear (active-low reset) and High-Voltage Programming (VPP) input, MSSP slave-select (SS), Timer1 gate. Weak pull-up and IOC available. VPP up to ~9V during ICSP programming."
      },
      {
        "number": "5",
        "name": "RC5/CCP1/P1A/TX/CK/RX/DT/MDCIN2",
        "type": "bidirectional",
        "description": "PORTC bit 5. Digital I/O with weak pull-up. Muxed: CCP1/P1A PWM output, EUSART TX/CK (async TX or sync clock) or RX/DT (async RX or sync data), Data Signal Modulator carrier input MDCIN2."
      },
      {
        "number": "6",
        "name": "RC4/C2OUT/SRNQ/P1B/TX/CK/MDOUT",
        "type": "bidirectional",
        "description": "PORTC bit 4. Digital I/O with weak pull-up. Muxed: Comparator C2 output, SR latch inverted output (SRNQ), ECCP P1B, EUSART TX/CK, Data Signal Modulator output MDOUT."
      },
      {
        "number": "7",
        "name": "RC3/AN7/CPS7/C12IN3-/CCP2/P1C/P2A/SS/MDMIN",
        "type": "bidirectional",
        "description": "PORTC bit 3. Digital I/O with weak pull-up. Muxed: ADC AN7, CapSense CPS7, comparator C1/C2 inverting input C12IN3-, CCP2/P1C/P2A PWM, MSSP SS, Data Signal Modulator modulation input MDMIN."
      },
      {
        "number": "8",
        "name": "RC2/AN6/CPS6/C12IN2-/P1D/P2B/SDO/MDCIN1",
        "type": "bidirectional",
        "description": "PORTC bit 2. Digital I/O with weak pull-up. Muxed: ADC AN6, CapSense CPS6, comparator inverting input C12IN2-, ECCP P1D/P2B, MSSP SDO, Data Signal Modulator carrier input MDCIN1."
      },
      {
        "number": "9",
        "name": "RC1/AN5/CPS5/C12IN1-/CCP4/P1C/SDA/SDI",
        "type": "bidirectional",
        "description": "PORTC bit 1. Digital I/O with weak pull-up. Muxed: ADC AN5, CapSense CPS5, comparator inverting input C12IN1-, CCP4 output/P1C PWM, MSSP I2C data (SDA) or SPI serial data in (SDI)."
      },
      {
        "number": "10",
        "name": "RC0/AN4/CPS4/C2IN+/P1D/SCL/SCK",
        "type": "bidirectional",
        "description": "PORTC bit 0. Digital I/O with weak pull-up. Muxed: ADC AN4, CapSense CPS4, comparator C2 non-inverting input, ECCP P1D, MSSP I2C clock (SCL) or SPI clock (SCK)."
      },
      {
        "number": "11",
        "name": "RA2/AN2/CPS2/C1OUT/SRQ/T0CKI/CCP3/FLT0/INT/IOC",
        "type": "bidirectional",
        "description": "PORTA bit 2. Digital I/O with weak pull-up. Muxed: ADC AN2, CapSense CPS2, comparator C1 output, SR latch output (SRQ), Timer0 clock input (T0CKI), CCP3, ECCP fault input FLT0, external interrupt INT, IOC."
      },
      {
        "number": "12",
        "name": "RA1/AN1/VREF+/CPS1/C12IN0-/SRI/RX/DT/ICSPCLK/ICDCLK",
        "type": "bidirectional",
        "description": "PORTA bit 1. Digital I/O with weak pull-up and IOC. Muxed: ADC AN1, positive ADC reference VREF+, CapSense CPS1, comparator inverting input C12IN0-, SR latch input SRI, EUSART RX/DT, ICSP programming clock (ICSPCLK) and in-circuit debug clock (ICDCLK)."
      },
      {
        "number": "13",
        "name": "RA0/AN0/VREF-/DACOUT/CPS0/C1IN+/TX/CK/IOC/ICSPDAT",
        "type": "bidirectional",
        "description": "PORTA bit 0. Digital I/O with weak pull-up and IOC. Muxed: ADC AN0, negative ADC reference VREF-, 5-bit DAC output DACOUT, CapSense CPS0, comparator C1 non-inverting input, EUSART TX/CK, ICSP data (ICSPDAT)."
      },
      {
        "number": "14",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference for logic and I/O. Must be tied to system ground."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/88d81547f5cf4afda59e76928edcf0c2.pdf",
        "pages": 436,
        "sha256": "79590175dda79888",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -3.81
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9",
      "mark": "drawn"
    },
    "models_3d": [
      {
        "file": "pic16f1824-i.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "pic16f1824-i-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "e96ce607df35df739c4965bfb4c2c56704d1e03954fccc8544048e84b1ad2c03",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "family": {
      "base": "PIC16F1824-I",
      "siblings": [
        "PIC16F1824-I/ST"
      ],
      "old_slug": "pic16f1824-i",
      "note": "renamed from the cut-base slug to the part it was built from (slug collision split, 2026-11-11)"
    }
  },
  "title": "PIC16F1824-I/SL",
  "brief": "Microchip Microcontrollers (MCU/MPU/SOC), SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "metadata": {
    "specs": {
      "Manufacturer": "Microchip",
      "Package": "SOIC-14",
      "Category": "MCU",
      "Pins": "14"
    }
  },
  "discovery_triggers": [
    "pic16f1824-i"
  ],
  "discovery_pitch": "PIC16F1824-I (Microchip) component page with datasheet-verified CAD.",
  "visibility": "public"
}