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PIC12LF1822-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPIC12LF1822-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SOIC-8
PIC12LF1822-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply; the PIC12LF1822 operates from 1.8V to 3.6V. |
| 2 | RA5 | bidirectional | General-purpose I/O (TTL input, CMOS output) that can alternately serve as CLKIN/OSC1, T1OSI, T1CKI, SRNQ, P1A/CCP1, or RX/DT, with the 8-pin selection made through APFCON. |
| 3 | RA4 | bidirectional | General-purpose I/O (TTL input, CMOS output) that can alternately serve as OSC2/CLKOUT, T1OSO, AN3, CPS3, CLKR, SDO, TX/CK, P1B, T1G, or MDCIN2, with the 8-pin selection made through APFCON. |
| 4 | MCLR/VPP/RA3 | input | Input-only pin: MCLR is the Master Clear input with internal pull-up when MCLRE is enabled, and VPP is the high-voltage programming pin. |
| 5 | RA2 | bidirectional | General-purpose I/O (Schmitt-trigger input, CMOS output) that can alternately serve as AN2, CPS2, C1OUT, SRQ, T0CKI, CCP1/P1A, FLT0, SDA, SDI, INT, or MDCIN1. |
| 6 | RA1/ICSPCLK | bidirectional | General-purpose I/O (TTL input, CMOS output) that also carries the ICSP Serial Programming Clock (ICSPCLK) and can alternately serve as AN1, CPS1, VREF+, C1IN0-, SRI, RX/DT, SCL/SCK, or MDMIN. |
| 7 | RA0/ICSPDAT | bidirectional | General-purpose I/O (TTL input, CMOS output) that also carries the ICSP Data I/O (ICSPDAT) and can alternately serve as AN0, CPS0, C1IN+, DACOUT, TX/CK, SDO, SS, P1B, or MDOUT. |
| 8 | VSS | power_in | Ground reference. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage on VDD with respect to VSS, PIC12LF1822/16LF1823 | VDD | -0.3 | 4 | V | 322 | ||
| Voltage on MCLR with respect to VSS | -0.3 | 9 | V | 322 | |||
| Voltage on all other pins with respect to VSS | -0.3 | V | Max printed as (VDD + 0.3V) | 322 | |||
| Maximum current out of VSS pin | 210 | mA | -40°C ≤ TA ≤ +85°C for industrial | 322 | |||
| Maximum current out of VSS pin | 95 | mA | -40°C ≤ TA ≤ +125°C for extended | 322 | |||
| Maximum current into VDD pin | 150 | mA | -40°C ≤ TA ≤ +85°C for industrial | 322 | |||
| Maximum current into VDD pin | 70 | mA | -40°C ≤ TA ≤ +125°C for extended | 322 | |||
| Clamp current | IK | 20 | mA | VPIN < 0 or VPIN > VDD | 322 | ||
| Ambient temperature under bias | -40 | 125 | °C | 322 | |||
| Storage temperature | -65 | 150 | °C | 322 | |||
| VDD Supply Voltage PIC12LF1822/16LF1823 | VDD | 1.8 | 3.6 | V | FOSC ≤ 16 MHz | 325 | |
| VDD Supply Voltage PIC12LF1822/16LF1823 | VDD | 2.5 | 3.6 | V | FOSC ≤ 32 MHz (Note 2) | 325 | |
| RAM Data Retention Voltage | VDR | 1.5 | V | Device in Sleep mode | 325 | ||
| Fixed Voltage Reference Voltage for ADC | VADFVR | -8 | 6 | % | 1.024V, VDD ≥ 2.5V | 325 | |
| Fixed Voltage Reference Voltage for Comparator and DAC | VCDAFVR | -11 | 7 | % | 1.024V, VDD ≥ 2.5V | 325 | |
| VDD Rise Rate to ensure internal Power-on Reset signal | SVDD | 0.05 | V/ms | See Section 7.1 'Power-on Reset (POR)' | 325 | ||
| Input Low Voltage, I/O ports with SMBus levels | VIL | 0.8 | V | with SMBus levels, 2.7V ≤ VDD ≤ 5.5V | 333 | ||
| Input High Voltage, I/O ports with SMBus levels | VIH | 2.1 | V | with SMBus levels, 2.7V ≤ VDD ≤ 5.5V | 333 | ||
| Weak Pull-up Current | IPUR | 25 | 100 | 200 | µA | VDD = 3.3V, VPIN = VSS | 333 |
| Output Low Voltage, I/O ports | VOL | 0.6 | V | IOL = 6mA, VDD = 3.3V | 333 | ||
| Capacitive Loading, OSC2 pin | COSC2 | 15 | pF | In XT, HS and LP modes when external clock is used to drive OSC1 | 333 | ||
| Capacitive Loading, All I/O pins | CIO | 50 | pF | 333 | |||
| Supply Current, LP Oscillator mode | IDD | 5 | 15 | µA | VDD = 1.8V; FOSC = 32 kHz, -40°C to +85°C | 327 | |
| Supply Current, LP Oscillator mode | IDD | 8 | 19 | µA | VDD = 3.0V; LP Oscillator mode | 327 | |
| Supply Current, LP Oscillator mode (-40°C to +125°C) | IDD | 5 | 21 | µA | VDD = 1.8V; FOSC = 32 kHz, -40°C to +125°C | 327 | |
| Supply Current, LP Oscillator mode (-40°C to +125°C) | IDD | 7.5 | 25 | µA | VDD = 3.0V; LP Oscillator mode | 327 | |
| Supply Current, LFINTOSC mode | IDD | 2 | 20 | µA | VDD = 1.8V; FOSC = 31 kHz | 328 | |
| Supply Current, LFINTOSC mode | IDD | 4 | 22 | µA | VDD = 3.0V; LFINTOSC mode | 328 | |
| Supply Current, HFINTOSC mode | IDD | 0.55 | 0.8 | mA | VDD = 1.8V; FOSC = 8 MHz | 328 | |
| Supply Current, HFINTOSC mode | IDD | 0.8 | 1.25 | mA | VDD = 3.0V; HFINTOSC mode | 328 | |
| Supply Current, HFINTOSC mode | IDD | 0.8 | 1.2 | mA | VDD = 1.8V; FOSC = 16 MHz | 328 | |
| Supply Current, HFINTOSC mode | IDD | 1.3 | 1.9 | mA | VDD = 3.0V; HFINTOSC mode | 328 | |
| Supply Current, HFINTOSC mode | IDD | 2.2 | 3.3 | mA | VDD = 3.0V; FOSC = 32 MHz | 328 | |
| Supply Current, HFINTOSC mode | IDD | 2.3 | 3.6 | mA | VDD = 3.6V; HFINTOSC mode (Note 3) | 328 | |
| Supply Current, EXTRC mode | IDD | 210 | 425 | µA | VDD = 1.8V; FOSC = 4 MHz | 329 | |
| Supply Current, EXTRC mode | IDD | 470 | 800 | µA | VDD = 3.0V; EXTRC mode (Note 5) | 329 | |
| Power-down Base Current (IPD) | IPD | 0.02 | 1 | µA | VDD = 1.8V; WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive; Max. +85°C | 330 | |
| Power-down Base Current (IPD) | IPD | 0.02 | 4 | µA | VDD = 1.8V; WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive; Max. +125°C | 330 | |
| Power-down Base Current (IPD) | IPD | 0.03 | 1.8 | µA | VDD = 3.0V; Max. +85°C | 330 | |
| Power-down Base Current (IPD) | IPD | 0.03 | 4.8 | µA | VDD = 3.0V; Max. +125°C | 330 | |
| Internal LFINTOSC Frequency tolerance (nominal 31 kHz) | LFOSC | -25 | 25 | % | -40°C ≤ TA ≤ +125°C | 338 | |
| Internal Calibrated HFINTOSC Frequency tolerance (nominal 16.0 MHz) | HFOSC | -2 | 2 | % | 0°C ≤ TA ≤ +60°C, VDD ≥ 2.5V | 338 | |
| Internal Calibrated HFINTOSC Frequency tolerance (nominal 16.0 MHz) | HFOSC | -3 | 3 | % | 60°C ≤ TA ≤ +85°C, VDD ≥ 2.5V | 338 | |
| Internal Calibrated HFINTOSC Frequency tolerance (nominal 16.0 MHz) | HFOSC | -5 | 5 | % | -40°C ≤ TA ≤ +125°C | 338 | |
| Internal Calibrated MFINTOSC Frequency tolerance (nominal 500 kHz) | MFOSC | -2 | 2 | % | 0°C ≤ TA ≤ +60°C, VDD ≥ 2.5V | 338 | |
| Internal Calibrated MFINTOSC Frequency tolerance (nominal 500 kHz) | MFOSC | -3 | 3 | % | 60°C ≤ TA ≤ +85°C, VDD ≥ 2.5V | 338 | |
| Internal Calibrated MFINTOSC Frequency tolerance (nominal 500 kHz) | MFOSC | -5 | 5 | % | -40°C ≤ TA ≤ +125°C | 338 | |
| Power-up Timer Period | TPWRT | 40 | 65 | 140 | ms | PWRTE = 0 | 342 |
| MCLR Pulse Width (low) | TMCL | 2 | µs | 342 | |||
| Operating temperature | TA | -40 | 85 | °C | Industrial (-I): -40°C ≤ TA ≤ +85°C | 325 | |
| Thermal Resistance Junction to Ambient, 8-pin SOIC package | JA | 149.5 | °C/W | 8-pin SOIC package | 335 | ||
| Thermal Resistance Junction to Case, 8-pin SOIC package | JC | 39.9 | °C/W | 8-pin SOIC package | 335 | ||
| Maximum Junction Temperature | TJMAX | 150 | °C | 335 |
CAD (KiCad official)
- Symbol:
PIC12LF1822-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
pic12lf1822-i-etched.step/pic12lf1822-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic12lf1822-i.step/pic12lf1822-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (423 pp, sha256
4d928a589d6decfe, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).