PIC12LF1571T-I

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  "slug": "pic12lf1571t-i",
  "title": "PIC12LF1571T-I",
  "brief": "Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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  "license": "CC-BY-SA-4.0",
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    "embedded processors & controllers",
    "pic12lf1571t-i",
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  "component": {
    "mpn": "PIC12LF1571T-I",
    "manufacturer": "Microchip Tech",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915890662346752",
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      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
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      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply pin; the PIC12LF1571 operating voltage range is 1.8V to 3.6V per the Operating Characteristics."
      },
      {
        "number": "2",
        "name": "RA5",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry T1CKI, PWM1 (via APFCON), CWG1A (via APFCON), or CLKIN as the External Clock input in EC mode; RX/DT are on PIC12(L)F1572 only."
      },
      {
        "number": "3",
        "name": "RA4",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry AN3, C1IN1-, T1G, CWG1B, PWM2, or CLKOUT (FOSC/4 output), with the TX/CK alternates on PIC12(L)F1572 only."
      },
      {
        "number": "4",
        "name": "RA3/MCLR/VPP",
        "type": "input",
        "description": "Input-only general purpose pin with IOC and weak pull-up that serves as the active-low MCLR Master Clear reset with internal pull-up, or as the VPP programming voltage input."
      },
      {
        "number": "5",
        "name": "RA2",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry AN2, C1OUT, T0CKI, CWG1FLT, CWG1A, PWM3, or the INT external interrupt input."
      },
      {
        "number": "6",
        "name": "RA1/ICSPCLK",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry AN1, VREF+, C1IN0-, PWM1, or ICSPCLK, the ICSP programming clock input."
      },
      {
        "number": "7",
        "name": "RA0/ICSPDAT",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry AN0, C1IN+, DACOUT, CWG1B, PWM2, or ICSPDAT, the bidirectional ICSP programming data pin."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
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        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet covers PIC12(L)F1571 and PIC12(L)F1572 together. The pin table marks the EUSART (TX/CK; The SOIC package drawing is not in the extracted text. Pin numbering was taken from Table 1 and the ; Pin 4 (RA3/MCLR/VPP) is input-only and its TRISA bit always reads 1. Its type is set to input, but c",
          "3/8 pins cited to the wrong page (name found elsewhere): ['5:RA2@p10', '6:RA1/ICSPCLK@p10', '7:RA0/ICSPDAT@p10']"
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        "cost_usd": 0.2149,
        "at": "2026-10-18T05:25:10"
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        "sha256": "8c2780e95ad8fcbd",
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      "cad": "KiCad official (CC-BY-SA 4.0)",
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        "total": 8,
        "described": 8,
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  "metadata": {
    "specs": {
      "Manufacturer": "Microchip Tech",
      "Package": "SOIC-8",
      "Category": "Embedded Processors & Controllers",
      "Pins": "8"
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        {
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        {
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        {
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          "name": "Base power-down current in Sleep",
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          "conditions": "VDD 3.0V; WDT, BOR and FVR disabled, all peripherals inactive, VREGPM = 1; max at +85°C",
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          "conditions": "VDD 1.8V; max at +85°C",
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          "name": "WDT current",
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          "name": "Input low voltage, I/O ports",
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          "unit": "VDD",
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          "typ": null,
          "max": 0.15,
          "conditions": "D030A; 1.8V ≤ VDD ≤ 4.5V (printed as 0.15 VDD)",
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        {
          "name": "Input low voltage, Schmitt Trigger buffer",
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          "max": 0.2,
          "conditions": "D031; 2.0V ≤ VDD ≤ 5.5V (printed as 0.2 VDD)",
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          "source": "datasheet"
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          "name": "Input high voltage, Schmitt Trigger buffer",
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          "conditions": "D041; 2.0V ≤ VDD ≤ 5.5V (printed as 0.8 VDD)",
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          "name": "Input leakage current, I/O ports, +85°C",
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          "typ": null,
          "max": 125,
          "conditions": "D060; VSS to VDD pin voltage, pin at high-impedance, +85°C",
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          "name": "Input leakage current, MCLR",
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          "conditions": "D061; VSS to VDD, pin at high-impedance, +85°C",
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          "source": "datasheet"
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          "name": "Weak pull-up current",
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          "conditions": "D070; VDD = 3.3V, VPIN = VSS",
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          "source": "datasheet"
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          "name": "Output low voltage, I/O ports",
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          "max": 0.6,
          "conditions": "D080; IOL = 6 mA, VDD = 3.3V",
          "source_page": 268,
          "source": "datasheet"
        },
        {
          "name": "Capacitive loading on all I/O pins",
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          "kind": "electrical",
          "unit": "pF",
          "min": null,
          "typ": null,
          "max": 50,
          "conditions": "D101A; all I/O pins",
          "source_page": 268,
          "source": "datasheet"
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