PIC12LF1571T-I

{
  "slug": "pic12lf1571t-i",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "pic12lf1571t-i",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "pic12lf1571t-i.kicad_sym",
    "pic12lf1571t-i.kicad_mod",
    "pic12lf1571t-i.glb",
    "pic12lf1571t-i.step",
    "pic12lf1571t-i.lbr",
    "docs/hero.png",
    "docs/pic12lf1571t-i-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pic12lf1571t-i-hero.glb",
    "pic12lf1571t-i-hero.overlay.json",
    "pic12lf1571t-i-etched.glb"
  ],
  "component": {
    "mpn": "PIC12LF1571T-I",
    "manufacturer": "Microchip Tech",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915890662346752",
    "parts": {
      "symbol": "pic12lf1571t-i.kicad_sym",
      "footprint": "pic12lf1571t-i.kicad_mod",
      "model_3d": "pic12lf1571t-i-hero.glb",
      "model_3d_plain": "pic12lf1571t-i-etched.glb",
      "model_3d_step": "pic12lf1571t-i-etched.step",
      "model_3d_step_plain": "pic12lf1571t-i.step",
      "lbr": "pic12lf1571t-i.lbr"
    },
    "distributor_links": {
      "lcsc": "C624043"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T05:28:16Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply pin; the PIC12LF1571 operating voltage range is 1.8V to 3.6V per the Operating Characteristics."
      },
      {
        "number": "2",
        "name": "RA5",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry T1CKI, PWM1 (via APFCON), CWG1A (via APFCON), or CLKIN as the External Clock input in EC mode; RX/DT are on PIC12(L)F1572 only."
      },
      {
        "number": "3",
        "name": "RA4",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry AN3, C1IN1-, T1G, CWG1B, PWM2, or CLKOUT (FOSC/4 output), with the TX/CK alternates on PIC12(L)F1572 only."
      },
      {
        "number": "4",
        "name": "RA3/MCLR/VPP",
        "type": "input",
        "description": "Input-only general purpose pin with IOC and weak pull-up that serves as the active-low MCLR Master Clear reset with internal pull-up, or as the VPP programming voltage input."
      },
      {
        "number": "5",
        "name": "RA2",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry AN2, C1OUT, T0CKI, CWG1FLT, CWG1A, PWM3, or the INT external interrupt input."
      },
      {
        "number": "6",
        "name": "RA1/ICSPCLK",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry AN1, VREF+, C1IN0-, PWM1, or ICSPCLK, the ICSP programming clock input."
      },
      {
        "number": "7",
        "name": "RA0/ICSPDAT",
        "type": "bidirectional",
        "description": "General purpose I/O that can alternately carry AN0, C1IN+, DACOUT, CWG1B, PWM2, or ICSPDAT, the bidirectional ICSP programming data pin."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet covers PIC12(L)F1571 and PIC12(L)F1572 together. The pin table marks the EUSART (TX/CK; The SOIC package drawing is not in the extracted text. Pin numbering was taken from Table 1 and the ; Pin 4 (RA3/MCLR/VPP) is input-only and its TRISA bit always reads 1. Its type is set to input, but c",
          "3/8 pins cited to the wrong page (name found elsewhere): ['5:RA2@p10', '6:RA1/ICSPCLK@p10', '7:RA0/ICSPDAT@p10']"
        ],
        "pages_sent": 60,
        "cost_usd": 0.2149,
        "at": "2026-10-18T05:25:10"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915890662346752",
        "pages": 334,
        "sha256": "8c2780e95ad8fcbd",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "pic12lf1571t-i.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "pic12lf1571t-i-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "e0c3cdf36c298362df50e66d2b705a44068294efdf1f84036c30683b295e2ee8",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}