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PIC12C672-04I

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Microchip Tech Pre-ordered MCUs, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC12C672-04I

Microchip Tech · Pre-ordered MCUs · PDIP-8

PIC12C672-04I from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply for logic and I/O pins (device operates from 2.5V to 5.5V).
2 GP5/OSC1/CLKIN bidirectional Bi-directional I/O port, oscillator crystal input or external clock source input (GPIO in INTRC mode only, OSC1 in all other oscillator modes), Schmitt trigger input for EXTRC mode.
3 GP4/OSC2/AN3/CLKOUT bidirectional Bi-directional I/O port, oscillator crystal output or analog input 3; in EXTRC and INTRC modes it can output CLKOUT at 1/4 the frequency of OSC1 (instruction cycle rate).
4 GP3/MCLR/VPP input Input port, active-low master clear (reset) input or programming voltage input; voltage on MCLR/VPP must not exceed VDD during normal operation, with weak pull-up always on when configured as MCLR.
5 GP2/T0CKI/AN2/INT bidirectional Bi-directional I/O port or analog input 2, configurable as T0CKI or external interrupt (Schmitt trigger input).
6 GP1/AN1/VREF bidirectional Bi-directional I/O port, serial programming clock, analog input 1 or voltage reference, with software-programmable weak pull-up and interrupt-on-pin change.
7 GP0/AN0 bidirectional Bi-directional I/O port, serial programming data or analog input 0, with software-programmable weak pull-up and interrupt-on-pin change.
8 VSS power_in Ground reference for logic and I/O pins.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-8
Category Embedded Processors & Controllers
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 3 5.5 V 92
RAM Data Retention Voltage VDR 1.5 V Device in SLEEP mode 92
VDD Rise Rate to ensure Power-on Reset SVDD 0.05 V/ms See section on Power-on Reset for details 92
Supply Current, XT and EXTRC mode IDD 1.2 2.5 mA FOSC = 4MHz, VDD = 3.0V XT and EXTRC mode (Note 4) 92
Supply Current, INTRC mode IDD 1.2 2.5 mA FOSC = 4MHz, VDD = 3.0V INTRC mode (Note 6) 92
Supply Current, LP mode, Industrial IDD 19 37 µA FOSC = 32kHz, VDD = 3.0V, WDT disabled LP mode, Industrial Temperature 92
Power-down Current, 3.0V Industrial IPD 0.25 7 µA VDD = 3.0V, Industrial, WDT disabled 92
Power-down Current, 5.5V Industrial IPD 0.8 9 µA VDD = 5.5V, Industrial, WDT disabled 92
Watchdog Timer Current, Industrial IWDT 2.2 6 µA VDD = 3.0V, Industrial 92
Input Low Voltage, I/O ports TTL buffer VIL 0.8 V For 4.5V ≤ VDD ≤ 5.5V 95
Input High Voltage, I/O ports TTL buffer VIH 2 V 4.5V ≤ VDD ≤ 5.5V 95
Input Leakage Current, I/O ports IIL 1 µA VSS ≤ VPIN ≤ VDD, Pin at hi-impedance 95
Input Leakage Current, GP3/MCLR IIL 30 µA VSS ≤ VPIN ≤ VDD (Note 5) 95
Input Leakage Current, GP3 IIL 5 µA VSS ≤ VPIN ≤ VDD (Note 6) 95
Input Leakage Current, GP2/T0CKI IIL 5 µA VSS ≤ VPIN ≤ VDD 95
Input Leakage Current, OSC1 IIL 5 µA VSS ≤ VPIN ≤ VDD, XT, HS, and LP osc configuration 95
GPIO weak pull-up current IPUR 50 250 400 µA VDD = 5V, VPIN = VSS (Note 4) 95
MCLR pull-up current 30 µA VDD = 5V, VPIN = VSS 95
Output Low Voltage, I/O ports VOL 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C 95
Output Low Voltage, OSC2/CLKOUT VOL 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C 95
OSC2 pin capacitive loading COSC2 15 pF In XT and LP modes when external clock is used to drive OSC1 96
All I/O pins capacitive loading CIO 50 pF 96
LP Oscillator Operating Frequency FOSC 0 200 kHz All temperatures 93
XT Oscillator Operating Frequency FOSC 0 4 MHz All temperatures 93
Internal Calibrated RC Frequency, 5.0V 3.65 4 4.28 MHz VDD = 5.0V 101
Internal Calibrated RC Frequency, 2.5V 3.55 4 4.31 MHz VDD = 2.5V 101
Instruction Cycle Time TCY 400 ns TCY = 4/FOSC 100
A/D clock period, TOSC based TAD 1.6 µs TOSC based, VREF ≥ 3.0V 106
A/D clock period, RC mode TAD 2 4 6 µs A/D RC Mode 106
A/D Resolution NR 8 bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF 105
A/D Total absolute error EABS 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF (printed < 1) 105
A/D Integral linearity error EIL 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF (printed < 1) 105
A/D Differential linearity error EDL 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF (printed < 1) 105
A/D Full scale error EFS 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF (printed < 1) 105
A/D Offset error EOFF 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF (printed < 1) 105
Reference voltage VREF 2.5 V 105
Recommended impedance of analog voltage source ZAIN 10 kΩ 105
A/D conversion current (VDD) IAD 180 µA Average current consumption when A/D is on (Note 1) 105
Operating Temperature (industrial) TA -40 85 °C industrial 92
Ambient temperature under bias -40 125 °C 89
Storage temperature -65 150 °C 89
Voltage on VDD with respect to VSS VDD 0 7 V 89
Voltage on MCLR with respect to VSS 0 14 V Note 2 89
Maximum current into VDD pin 150 mA 89
Input clamp current IIK 20 mA VI < 0 or VI > VDD 89
Output clamp current IOK 20 mA VO < 0 or VO > VDD 89
Maximum output current sunk by any I/O pin 25 mA 89
Maximum output current sourced by any I/O pin 25 mA 89

CAD (KiCad official)

  • Symbol: PIC12C672-04I
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: pic12c672-04i-etched.step / pic12c672-04i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic12c672-04i.step / pic12c672-04i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (130 pp, sha256 976c784919a7946c, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF