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PIC12C508-04I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC12C508-04I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · PDIP-8

PIC12C508-04I from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply for logic and I/O pins.
2 GP5/OSC1/CLKIN bidirectional Bidirectional I/O port, oscillator crystal input or external clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes); TTL input when GPIO, ST input in external RC oscillator mode.
3 GP4/OSC2 bidirectional Bidirectional I/O port with TTL input or oscillator crystal output for crystal or resonator connection in XT and LP modes only (GPIO in other modes).
4 GP3/MCLR/VPP input Input port, active-low master clear (reset) input or programming voltage input; voltage on MCLR/VPP must not exceed VDD during normal operation or the device enters programming mode, with software-programmable weak pull-up and wake-up from SLEEP on pin change (weak pull-up always on if configured as MCLR).
5 GP2/T0CKI bidirectional Bidirectional I/O port with Schmitt Trigger input that can be configured as T0CKI.
6 GP1 bidirectional Bidirectional I/O port or serial programming clock with TTL/ST input, software-programmable weak pull-up and wake-up from SLEEP on pin change; Schmitt Trigger input in serial programming mode.
7 GP0 bidirectional Bidirectional I/O port or serial programming data with TTL/ST input, software-programmable weak pull-up and wake-up from SLEEP on pin change; Schmitt Trigger input in serial programming mode.
8 VSS power_in Ground reference for logic and I/O pins.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-8
Category Single Chip Microcomputer/Microcontroller
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 2.5 5.5 V FOSC = DC to 4 MHz (Commercial/Industrial) 66
RAM Data Retention Voltage VDR 1.5 V Device in SLEEP mode 66
VDD Rise Rate to ensure Power-on Reset SVDD 0.05 V/ms See section on Power-on Reset for details 66
Supply Current, XT and EXTRC IDD 0.78 2.4 mA FOSC = 4 MHz, VDD = 5.5V 66
Supply Current, INTRC IDD 1.1 2.4 mA FOSC = 4 MHz, VDD = 5.5V 66
Supply Current, LP Industrial IDD 14 35 µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled 66
Power-Down Current, Industrial IPD 0.25 5 µA VDD = 3.0V, Industrial WDT disabled 66
WDT Current, Industrial ∆IWDT 3.75 9 µA VDD = 3.0V, Industrial 66
GPIO weak pull-up current IPUR 50 250 400 µA VDD = 5V, VPIN = VSS 67
Input Leakage Current, I/O ports IIL -1 0.5 1 µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance 67
Input Leakage Current, MCLR, GP2/T0CKI IIL 20 130 250 µA VPIN = VSS + 0.25V 67
Input Leakage Current, MCLR, GP2/T0CKI IIL 0.5 5 µA VPIN = VDD 67
Input Leakage Current, OSC1 IIL -3 0.5 3 µA Vss ≤ VPIN ≤ VDD, XT and LP options 67
Output Low Voltage, I/O ports/CLKOUT VOL 0.6 V IOL = 8.7 mA, VDD = 4.5V 67
OSC2 pin capacitive loading COSC2 15 pF In XT and LP modes when external clock is used to drive OSC1. 67
All I/O pins capacitive loading CIO 50 pF 67
Ambient Temperature under bias -40 125 °C 65
Storage Temperature -65 150 °C 65
Voltage on VDD with respect to VSS VDD 0 7.5 V 65
Voltage on MCLR with respect to VSS MCLR 0 14 V 65
Max. Current into VDD pin 150 mA 65
Input Clamp Current IIK -20 20 mA VI < 0 or VI > VDD 65
Output Clamp Current IOK -20 20 mA VO < 0 or VO > VDD 65
Max. Output Current sunk by any I/O pin 25 mA 65
Max. Output Current sourced by any I/O pin 25 mA 65
Operating Temperature (industrial) TA -40 85 °C industrial 66
Internal Calibrated RC Frequency 3.58 4 4.32 MHz VDD = 5.0V 71
Internal Calibrated RC Frequency 3.5 4.26 MHz VDD = 2.5V 71
External CLKIN Frequency, XT FOSC 4 MHz XT osc mode 70
MCLR Pulse Width (low) TmcL 2000 ns VDD = 5 V 73
Watchdog Timer Time-out Period (No Prescaler) Twdt 9 18 30 ms VDD = 5 V (Commercial) 73
Device Reset Timer Period TDRT 9 18 30 ms VDD = 5 V (Commercial) 73
Port output rise time TioR 10 25 ns 72
Port output fall time TioF 10 25 ns 72

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Package Type: K04-057 8-Lead Plastic Small Outline (SN), Narrow, 150 mil Dimension Limits MIN 101

CAD (KiCad official)

  • Symbol: PIC12C508-04I
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: pic12c508-04i-etched.step / pic12c508-04i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic12c508-04i.step / pic12c508-04i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (113 pp, sha256 038ccfcc9e0e8996, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF