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PIC10LF320T-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC10LF320T-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · SOT-23-6

PIC10LF320T-I from Microchip Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RA0/ICSPDAT bidirectional General purpose I/O with interrupt-on-change and weak pull-up, multiplexed with ICSPDAT, PWM1, CWG1A, CLC1IN0 and AN0.
2 VSS power_in Ground reference for the device.
3 RA1/ICSPCLK bidirectional General purpose I/O with interrupt-on-change and weak pull-up, multiplexed with ICSPCLK, CLKIN (EC mode), PWM2, CWG1B, CLC1, AN1 and NCO1CLK.
4 RA2 bidirectional General purpose I/O with interrupt-on-change and weak pull-up, multiplexed with INT external interrupt, T0CKI, NCO1, CLKR, CLC1IN1, AN2 and CWG1FLT.
5 VDD power_in Positive supply; the PIC10LF320/322 operates over 1.8V to 3.6V.
6 RA3/MCLR/VPP input General purpose input only; when MCLR is enabled it is the Master Clear Reset input with internal weak pull-up, and VPP is the programming voltage.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOT-23-6
Category Single Chip Microcomputer/Microcontroller
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD (FOSC ≤ 16 MHz) VDD 1.8 3.6 V FOSC ≤ 16 MHz, PIC10LF320/322 159
Supply voltage VDD (FOSC ≤ 20 MHz) VDD 2.5 3.6 V FOSC ≤ 20 MHz (16 MHz < FOSC ≤ 20 MHz) 159
Operating ambient temperature TA (industrial) TA -40 85 °C Industrial temperature range 157
Operating ambient temperature TA (extended) TA -40 125 °C Extended temperature range 157
Voltage on VDD pin VDD -0.3 4 V PIC10LF320/322, with respect to VSS 156
Voltage on MCLR pin VMCLR -0.3 9 V with respect to VSS 156
Voltage on all other pins VPIN -0.3 V with respect to VSS; upper limit printed as (VDD + 0.3V) 156
Ambient temperature under bias TA -40 125 °C under bias 156
Storage temperature TSTG -65 150 °C 156
Maximum current on VSS pin IVSS 250 mA -40°C ≤ TA ≤ +85°C 156
Maximum current on VSS pin IVSS 85 mA +85°C ≤ TA ≤ +125°C 156
Maximum current on VDD pin IDD 250 mA -40°C ≤ TA ≤ +85°C 156
Maximum current on VDD pin IDD 85 mA +85°C ≤ TA ≤ +125°C 156
Current sunk by any I/O pin IOL 50 mA 156
Current sourced by any I/O pin IOH 50 mA 156
Clamp current IK 20 mA VPIN < 0 or VPIN > VDD 156
Thermal resistance junction to ambient θJA 60 °C/W 6-pin SOT-23 package 166
Thermal resistance junction to case θJC 31.4 °C/W 6-pin SOT-23 package 166
Maximum junction temperature TJMAX 150 °C 166
RAM data retention voltage VDR 1.5 V Device in Sleep mode 159
Power-on Reset release voltage VPOR 1.6 V 159
Power-on Reset rearm voltage VPORR 0.8 V Device in Sleep mode 159
VDD rise rate SVDD 0.05 V/ms See Section 5.1 Power-On Reset (POR) for details 159
Supply current IDD, FOSC = 500 kHz IDD 34 45 µA VDD 1.8V, FOSC = 500 kHz 161
Supply current IDD, EC mode IDD 60 105 µA EC mode, VDD 3.0V 161
Supply current IDD, FOSC = 8 MHz IDD 190 290 µA VDD 1.8V, FOSC = 8 MHz 161
Supply current IDD, EC mode 8 MHz IDD 350 500 µA EC mode, VDD 3.0V 161
Supply current IDD, FOSC = 20 MHz IDD 0.8 1.3 mA VDD 3.0V, FOSC = 20 MHz 161
Supply current IDD, EC mode 20 MHz IDD 1.1 1.8 mA EC mode, VDD 3.6V 161
Supply current IDD, LFINTOSC 32 kHz 85°C IDD 2.2 4.1 µA VDD 1.8V, FOSC = 32 kHz, LFINTOSC mode, 85°C 161
Supply current IDD, LFINTOSC 32 kHz 85°C IDD 3.9 6.5 µA VDD 3.0V, LFINTOSC mode, 85°C 161
Supply current IDD, LFINTOSC 32 kHz 125°C IDD 3.2 4.5 µA VDD 1.8V, FOSC = 32 kHz, LFINTOSC mode, 125°C 161
Supply current IDD, LFINTOSC 32 kHz 125°C IDD 4.8 7 µA VDD 3.0V, LFINTOSC mode, 125°C 161
Supply current IDD, HFINTOSC 500 kHz IDD 213 290 µA VDD 1.8V, FOSC = 500 kHz, HFINTOSC mode 162
Supply current IDD, HFINTOSC 8 MHz IDD 0.33 0.5 mA VDD 1.8V, FOSC = 8 MHz, HFINTOSC mode 162
Supply current IDD, HFINTOSC 16 MHz IDD 0.46 1.1 mA VDD 1.8V, FOSC = 16 MHz, HFINTOSC mode 162
Power-down current IPD (Sleep), +85°C IPD 0.06 1.1 µA VDD 1.8V, +85°C max, WDT, BOR and FVR disabled, all peripherals inactive 163
Power-down current IPD (Sleep), +125°C IPD 0.06 2 µA VDD 1.8V, +125°C max, WDT, BOR and FVR disabled, all peripherals inactive 163
Power-down current IPD (Sleep), +85°C IPD 0.08 1.3 µA VDD 3.0V, +85°C max, WDT, BOR and FVR disabled, all peripherals inactive 163
Power-down current IPD (Sleep), +125°C IPD 0.08 2 µA VDD 3.0V, +125°C max, WDT, BOR and FVR disabled, all peripherals inactive 163
WDT current, +85°C IWDT 0.5 9 µA VDD 1.8V, +85°C max, WDT current 163
WDT current, +125°C IWDT 0.5 11 µA VDD 1.8V, +125°C max, WDT current 163
FVR current, +85°C IFVR 30 96 µA VDD 1.8V, +85°C max, FVR current 163
FVR current, +125°C IFVR 30 120 µA VDD 1.8V, +125°C max, FVR current 163
A/D current, no conversion, +85°C IAD 0.1 4 µA VDD 1.8V, +85°C max, no conversion in progress 163
A/D current, no conversion, +125°C IAD 0.1 5 µA VDD 1.8V, +125°C max, no conversion in progress 163
Input low voltage, Schmitt trigger buffer VIL 0.2 x VDD D033, 2.0V ≤ VDD ≤ 5.5V 164
Input low voltage, MCLR VIL 0.2 x VDD D034 MCLR 164
Input low voltage, I/O (1.8V ≤ VDD ≤ 4.5V) VIL 0.15 x VDD D032A, 1.8V ≤ VDD ≤ 4.5V 164
Input high voltage, Schmitt trigger buffer VIH 0.8 x VDD D041, 2.0V ≤ VDD ≤ 5.5V 164
Input high voltage, MCLR VIH 0.8 x VDD D042 MCLR 164
Weak pull-up current IPUR 25 100 200 µA VDD = 3.3V, VPIN = VSS 164
Output low voltage I/O ports VOL 0.6 V IOL = 6mA, VDD = 3.3V 164
Flash data retention TRETD 40 Year Provided no other specifications are violated 165
Self-timed write cycle time TIW 2 2.5 ms 165
Voltage on MCLR/VPP during programming VIHH 8 9 V Required only if single-supply programming is disabled 165
Supply current during programming IDDP 10 mA 165
Internal oscillator LFINTOSC frequency tolerance LFOSC -25 25 % Internal LFINTOSC frequency, typical 31 kHz 168
Wake-up start-up time HFINTOSC TWARM 5 8 µs HFINTOSC wake-up from Sleep 168
Watchdog timer time-out period TWDTLP 10 16 27 ms VDD = 3.3V-5V, 1:16 prescaler used 172
Power-up timer period TPWRT 40 64 140 ms PWRTE = 0 172
Brown-out reset voltage (LF) VBOR 1.8 1.9 2.05 V BORV = 1 (PIC10LF320/322) 172
Brown-out reset hysteresis VHYST 0 25 50 mV -40°C to +85°C 172
Low-power brown-out reset voltage VLPBOR 1.8 2.1 2.5 V LPBOR = 1 172
CLKOUT fall delay from FOSC OS11 70 ns 3.3V ≤ VDD ≤ 5.0V 170
CLKOUT rise delay from FOSC OS12 72 ns 3.3V ≤ VDD ≤ 5.0V 170
Port output valid after CLKOUT OS13 20 ns 170
Port output valid after FOSC Q1 OS15 50 70 ns 3.3V ≤ VDD ≤ 5.0V 170
Port input invalid after FOSC Q2 OS16 50 ns 3.3V ≤ VDD ≤ 5.0V 170
Port input setup before FOSC Q2 OS17 20 ns 170
Port output rise time OS18 40 72 ns VDD = 1.8V 170
Port output fall time OS19 28 55 ns VDD = 1.8V 170
INT pin input high or low time OS20 25 ns 170
Interrupt-on-change input level time OS21 25 ns 170
A/D internal FRC oscillator period AD130 1 1.6 6 µs ADCS<1:0> = 11 (ADRC mode) 174
A/D conversion time TCNV 9.5 TAD Not including acquisition time 174
A/D acquisition time TACQ 5 µs 174
A/D integral error EIL -1.7 1.7 LSb VREF = 3.0V 174
A/D differential error EDL -1 1 LSb No missing codes, VREF = 3.0V 174
A/D offset error EOFF -2.5 2.5 LSb VREF = 3.0V 174
A/D gain error EGN -2 2 LSb VREF = 3.0V 174
A/D reference voltage VREF 1.8 V VREF = VREF+ minus VREF-, upper limit VDD 174
Recommended impedance of analog voltage source ZAIN 10 k Can go higher if external 0.01µF capacitor is present on input pin 174
CLC module input to output propagation time TCLC 24 ns VDD = 1.8V 173
CLC maximum switching frequency FCLCMAX 45 MHz 173

CAD (KiCad official)

  • Symbol: PIC10LF320T-I
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: pic10lf320t-i-etched.step / pic10lf320t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic10lf320t-i.step / pic10lf320t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (193 pp, sha256 e1be25947d2c45e3, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF