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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

PI6CG18201ZDIEX

Diodes Incorporated · Clock Generators / Frequency Synthesizers / PLL · TQFN-24-EP(4x4)

PI6CG18201ZDIEX from Diodes Incorporated, in a TQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	XTAL_IN/CLK	input	Crystal input or CMOS reference input, 25 MHz nominal (23 to 27 MHz input frequency).
2	XTAL_OUT	output	Crystal output.
3	VDD_OSC	power_in	Power supply for oscillator circuitry, nominal 1.8V.
4	SADR/REFOUT	bidirectional	CMOS latch input selecting the SMBus address, then 1.8V LVCMOS REFOUT output; has an internal pull-down.
5	GND_REFOUT	power_in	Ground for REFOUT.
6	GND_DIG	power_in	Ground for digital circuitry.
7	VDD_DIG	power_in	Power supply for digital circuitry, nominal 1.8V.
8	SCLK	input	CMOS SMBus clock input, 3.3V tolerant.
9	SDATA	bidirectional	CMOS SMBus data line, 3.3V tolerant.
10	GND	power_in	Ground.
11	VDDO	power_in	Power supply for differential outputs (1.7V to 1.9V operating range).
12	OE0#	input	Active-low CMOS input enabling the Q0 pair (1 = disable outputs, 0 = enable outputs); has an internal pull-down.
13	Q0+	output	HCSL differential true clock output (100 MHz) with on-chip termination.
14	Q0-	output	HCSL differential complementary clock output (100 MHz) with on-chip termination.
15	GNDA	power_in	Ground for analog circuitry.
16	VDDA	power_in	Power supply for analog circuitry, nominal 1.8V.
17	Q1+	output	HCSL differential true clock output (100 MHz) with on-chip termination.
18	Q1-	output	HCSL differential complementary clock output (100 MHz) with on-chip termination.
19	OE1#	input	Active-low CMOS input enabling the Q1 pair (1 = disable outputs, 0 = enable outputs); has an internal pull-down.
20	VDDO	power_in	Power supply for differential outputs (1.7V to 1.9V operating range).
21	GND	power_in	Ground.
22	PD#	input	CMOS input that makes the device sample latched inputs and start up on first high assertion; low enters Power Down mode, and it has an internal pull-up resistor.
23	SS_SEL_TRI	input	Tri-level latched input selecting spread amount at initial power up (1 = -0.5% spread, M = -0.25%, 0 = spread off).
24	GND_XTAL	power_in	Ground for oscillator circuit.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Diodes Incorporated
Package	TQFN-24-EP(4x4)
Category	RTC/Clock Chip
Pins	25

CAD (KiCad official)

Symbol: PI6CG18201ZDIEX
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: TQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: pi6cg18201zdiex-etched.step / pi6cg18201zdiex-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pi6cg18201zdiex.step / pi6cg18201zdiex.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Diodes Incorporated datasheet (19 pp, sha256 30d33ba0ec8363a4, retrieved 2026-10-27, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF