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PI6C4911506-06LIE

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Diodes Incorporated Clock Buffers, Drivers, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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PI6C4911506-06LIE

Diodes Incorporated · Clock Buffers, Drivers · TSSOP-24

PI6C4911506-06LIE from Diodes Incorporated, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 nQ2 output Inverting output of differential pair 2 with LVPECL interface levels.
2 Q2 output Non-inverting output of differential pair 2 with LVPECL interface levels.
3 VDD power_in Positive power supply pin, 3.135V to 3.465V or 2.375V to 2.625V.
4 nQ1 output Inverting output of differential pair 1 with LVPECL interface levels.
5 Q1 output Non-inverting output of differential pair 1 with LVPECL interface levels.
6 VEE power_in Negative supply pin, tied to 0V.
7 nQ0 output Inverting output of differential pair 0 with LVPECL interface levels.
8 Q0 output Non-inverting output of differential pair 0 with LVPECL interface levels.
9 CLK_SEL0 input Clock select input 0 with internal pulldown, LVCMOS/LVTTL levels, see Table 3B.
10 XTAL_IN input Parallel resonant crystal interface input, fundamental mode 12 to 40MHz crystal.
11 XTAL_OUT output Parallel resonant crystal interface output.
12 CLK_EN input Synchronizing clock enable with internal pullup, LVCMOS/LVTTL levels; outputs follow clock input when HIGH and are disabled when LOW.
13 CLK0 input LVCMOS/LVTTL clock input with internal pulldown (51kΩ typ), up to 300MHz.
14 CLK1 input Non-inverting differential clock input with internal pulldown (51kΩ typ), up to 1500MHz.
15 nCLK1 input Inverting differential clock input with internal pullup (51kΩ typ).
16 CLK_SEL1 input Clock select input 1 with internal pulldown, LVCMOS/LVTTL levels, see Table 3B.
17 nQ5 output Inverting output of differential pair 5 with LVPECL interface levels.
18 Q5 output Non-inverting output of differential pair 5 with LVPECL interface levels.
19 VDD power_in Positive power supply pin, 3.135V to 3.465V or 2.375V to 2.625V.
20 nQ4 output Inverting output of differential pair 4 with LVPECL interface levels.
21 Q4 output Non-inverting output of differential pair 4 with LVPECL interface levels.
22 VDD power_in Positive power supply pin, 3.135V to 3.465V or 2.375V to 2.625V.
23 nQ3 output Inverting output of differential pair 3 with LVPECL interface levels.
24 Q3 output Non-inverting output of differential pair 3 with LVPECL interface levels.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package TSSOP-24
Category Clock and Timing
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Core Supply Voltage (3.3V) VDD 3.135 3.465 V 3
Core Supply Voltage (2.5V) VDD 2.375 2.625 V 3
Core Power Supply Current IDD 150 mA Outputs unloaded 3
Ambient Operating Temperature TA -40 85 °C 3
Storage temperature -55 150 °C 3
Supply Voltage to Ground Potential VDD -0.5 4.6 V 3
Inputs (Referenced to GND) -0.5 V max is VDD+0.5V 3
Clock Output (Referenced to GND) -0.5 V max is VDD+0.5V 3
Input High Voltage VIH 2 V VDD = 3.3V; max VDD+0.3 3
Input High Voltage VIH 1.7 V VDD = 2.5V; max VDD+0.3 3
Input Low Voltage VIL -0.3 0.8 V VDD = 3.3V 3
Input Low Voltage VIL -0.3 0.7 V VDD = 2.5V 3
Input High Current CLK0, CLK_SEL0:1 IIH 150 μA VDD = VIN = 3.465V or 2.625V 3
Input High Current CLK_EN IIH 20 μA VDD = VIN = 3.465V or 2.625V 3
Input Low Current CLK0, CLK_SEL0:1 IIL -15 μA VDD = 3.465V or 2.625V, VIN = 0V 3
Input Low Current CLK_EN IIL -150 μA VDD = 3.465V or 2.625V, VIN = 0V 3
Common Mode Input Voltage VCMR 0.5 V min VEE+0.5, max VDD-0.85 4
Peak-to-Peak Input Voltage VPP 0.15 1.3 V 4
Input Low Current nCLK1 IIL -150 μA VDD = 3.465V or 2.625V, VIN = 0V 4
Input Low Current CLK1 IIL -5 μA VDD = 3.465V or 2.625V, VIN = 0V 4
Input High Current nCLK1 IIH 5 μA VDD = VIN = 3.465V or 2.625V 4
Input High Current CLK1 IIH 150 μA VDD = VIN = 3.465V 4
Crystal Frequency 12 40 MHz 4
Crystal ESR ESR 50 Ω 4
Crystal Shunt Capacitance 7 pF 4
Crystal Drive Level 1 mW 4
Output High voltage VOH 2.1 2.6 V VDD=3.3V 4
Output High voltage VOH 1.3 1.6 V VDD=2.5V 4
Output Low voltage VOL 1.3 1.8 V VDD=3.3V 4
Output Low voltage VOL 0.5 0.8 V VDD=2.5V 4
Output Frequency CLK1/nCLK1 fMAX 1500 MHz CLK1/nCLK1, VDD=3.3V±5% 5
Output Frequency CLK0 fMAX 300 MHz CLK0, VDD=3.3V±5% 5
Propagation Delay tPD 1.5 ns VDD=3.3V±5% 5
Buffer Additive Jitter, RMS tjit 0.03 ps CLK1/nCLK1, 156.25MHz, Integration Range: 12kHz - 20MHz, VDD=3.3V±5% 5
Output Skew tsk(o) 80 ps VDD=3.3V±5% 5
Part-to-Part Skew tsk(pp) 450 ps VDD=3.3V±5% 5
Output Rise/Fall Time tR / tF 120 350 ps 20% to 80%, VDD=3.3V±5% 5
Output Duty Cycle odc 48 52 % VDD=3.3V±5% 5
Input Capacitance CIN 4 pF 6
Input Pulldown Resistor RPULLDOWN 51 kΩ CLK0, CLK1 6
Input Pullup Resistor RPULLUP 51 kΩ nCLK1 6

CAD (KiCad official)

  • Symbol: PI6C4911506-06LIE
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: pi6c4911506-06lie-etched.step / pi6c4911506-06lie-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pi6c4911506-06lie.step / pi6c4911506-06lie.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (7 pp, sha256 6ee920fda7506d93, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF