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PI4IOE5V9555ZDEX

Diodes Incorporated · I/O Expanders · TQFN-24-EP(4x4)

PI4IOE5V9555ZDEX from Diodes Incorporated, in a TQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IO0_0	bidirectional	Port 0 general-purpose I/O bit 0, configured as input or output via Configuration Port 0 (C0.0); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
2	IO0_1	bidirectional	Port 0 general-purpose I/O bit 1, configured as input or output via Configuration Port 0 (C0.1); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
3	IO0_2	bidirectional	Port 0 general-purpose I/O bit 2, configured as input or output via Configuration Port 0 (C0.2); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
4	IO0_3	bidirectional	Port 0 general-purpose I/O bit 3, configured as input or output via Configuration Port 0 (C0.3); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
5	IO0_4	bidirectional	Port 0 general-purpose I/O bit 4, configured as input or output via Configuration Port 0 (C0.4); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
6	IO0_5	bidirectional	Port 0 general-purpose I/O bit 5, configured as input or output via Configuration Port 0 (C0.5); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
7	IO0_6	bidirectional	Port 0 general-purpose I/O bit 6, configured as input or output via Configuration Port 0 (C0.6); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
8	IO0_7	bidirectional	Port 0 general-purpose I/O bit 7, configured as input or output via Configuration Port 0 (C0.7); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
9	GND	power_in	Ground reference; all device voltages are specified with respect to GND = 0V.
10	IO1_0	bidirectional	Port 1 general-purpose I/O bit 0, configured as input or output via Configuration Port 1 (C1.0); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
11	IO1_1	bidirectional	Port 1 general-purpose I/O bit 1, configured as input or output via Configuration Port 1 (C1.1); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
12	IO1_2	bidirectional	Port 1 general-purpose I/O bit 2, configured as input or output via Configuration Port 1 (C1.2); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
13	IO1_3	bidirectional	Port 1 general-purpose I/O bit 3, configured as input or output via Configuration Port 1 (C1.3); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
14	IO1_4	bidirectional	Port 1 general-purpose I/O bit 4, configured as input or output via Configuration Port 1 (C1.4); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
15	IO1_5	bidirectional	Port 1 general-purpose I/O bit 5, configured as input or output via Configuration Port 1 (C1.5); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
16	IO1_6	bidirectional	Port 1 general-purpose I/O bit 6, configured as input or output via Configuration Port 1 (C1.6); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
17	IO1_7	bidirectional	Port 1 general-purpose I/O bit 7, configured as input or output via Configuration Port 1 (C1.7); inputs may be driven up to 5.5V and each I/O must be externally limited to 25mA.
18	A0	input	I2C device address select input bit 0 that selects one of eight preset addresses; VIL max 0.81V and VIH min 1.8V, tolerant up to 5.5V.
19	SCL	input	I2C serial clock input, 0 to 400 kHz in Fast Mode; VIH min 0.7VCC and VIL max 0.3VCC.
20	SDA	bidirectional	I2C serial data line, open-drain; VIH min 0.7VCC, VIL max 0.3VCC, and IOL min 3mA at VOL = 0.4V.
21	VCC	power_in	Supply voltage, 2.3V to 5.5V; the device resets when VCC is lowered to 0.2V for at least 20µs.
22	INT	output	Active-LOW open-drain interrupt output, asserted when an input-configured port pin changes state; IOL min 3mA at VOL = 0.4V.
23	A1	input	I2C device address select input bit 1 that selects one of eight preset addresses; VIL max 0.81V and VIH min 1.8V, tolerant up to 5.5V.
24	A2	input	I2C device address select input bit 2 that selects one of eight preset addresses; VIL max 0.81V and VIH min 1.8V, tolerant up to 5.5V.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Diodes Incorporated
Package	TQFN-24-EP(4x4)
Category	Communication Interface Chip/UART/485/232
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power Supply (absolute maximum)		-0.5		6	V		3
Voltage on an I/O pin (absolute maximum)				6	V	Printed as GND-0.5V to +6.0V; min not numeric	3
Input Current (absolute maximum)		-20		20	mA	Printed as ±20mA	3
Output Current on an I/O pin (absolute maximum)		-50		50	mA	Printed as ±50mA	3
Supply Current (absolute maximum)				160	mA		3
Ground Supply Current (absolute maximum)				200	mA		3
Total Power Dissipation (absolute maximum)				200	mW		3
Operation Temperature		-40		85	°C	Printed as -40°C ~ 85°C	3
Storage Temperature		-65		150	°C	Printed as -65°C ~ 150°C	3
Maximum Junction Temperature	Tj(max)			125	°C		3
Supply Voltage	VCC	2.3		5.5	V		3
Supply Current	ICC		135	200	μA	Operating mode; VCC = 5.5V; no load; fSCL = 100kHz	3
Standby Current (VI = GND)	Istb		1.1	1.5	mA	Standby mode; VCC = 5.5V; no load; VI = GND; fSCL = 0kHz; I/O = inputs	3
Standby Current (VI = VCC)	Istb		0.25	1	μA	Standby mode; VCC = 5.5V; no load; VI = VCC; fSCL = 0kHz; I/O = inputs	3
Power-On Reset Voltage	VPOR		1.16	1.41	V		3
Low Level Input Voltage (SCL, SDA)	VIL	-0.5			V	Printed max is +0.3VCC (not numeric)	3
High Level Input Voltage (SCL, SDA)	VIH			5.5	V	Printed min is 0.7VCC (not numeric)	3
Low Level Output Current (SDA)	IOL	3			mA	VOL = 0.4V	3
Leakage Current (SCL, SDA)	IL	-1		1	μA	VI = VCC = GND	3
Input Capacitance (SCL, SDA)	Ci		6	10	pF	VI = GND	3
Low Level Input Voltage (I/O)	VIL	-0.5		0.81	V		4
High Level Input Voltage (I/O)	VIH	1.8		5.5	V		4
Low Level Output Current (I/O)	IOL	8	20		mA	VCC = 2.3V to 5.5V; VOL = 0.5V	4
Low Level Output Current (I/O)	IOL	10	24		mA	VCC = 2.3V to 5.5V; VOL = 0.7V	4
High Level Output Voltage (I/O)	VOH	1.8			V	IOH = -8mA; VCC = 2.3V	4
High Level Output Voltage (I/O)	VOH	1.7			V	IOH = -10mA; VCC = 2.3V	4
High Level Output Voltage (I/O)	VOH	2.6			V	IOH = -8mA; VCC = 3.0V	4
High Level Output Voltage (I/O)	VOH	2.5			V	IOH = -10mA; VCC = 3.0V	4
High Level Output Voltage (I/O)	VOH	4.1			V	IOH = -8mA; VCC = 4.75V	4
High Level Output Voltage (I/O)	VOH	4			V	IOH = -10mA; VCC = 4.75V	4
High Level Input Leakage Current (I/O)	ILIH			1	μA	VCC = 5.5V; VI = VCC	4
Low Level Input Leakage Current (I/O)	ILIL			-100	μA	VCC = 5.5V; VI = GND	4
Input Capacitance (I/O)	Ci		3.7	10	pF		4
Output Capacitance (I/O)	Co		3.7	10	pF		4
Low Level Output Current (INT)	IOL	3			mA	VOL = 0.4V	4
Low Level Input Voltage (A0, A1, A2)	VIL	-0.5		0.81	V		4
High Level Input Voltage (A0, A1, A2)	VIH	1.8		5.5	V		4
Input Leakage Current (A0, A1, A2)	IL	-1		1	μA		4
SCL Clock Frequency	fSCL	0		100	kHz	Standard Mode (I2C)	5
SCL Clock Frequency	fSCL	0		400	kHz	Fast Mode (I2C)	5
Bus Free Time between STOP and START	tBUF	4.7			μs	Standard Mode (I2C)	5
Bus Free Time between STOP and START	tBUF	1.3			μs	Fast Mode (I2C)	5
Hold Time (Repeated) START Condition	tHD;STA	4			μs	Standard Mode (I2C)	5
Hold Time (Repeated) START Condition	tHD;STA	0.6			μs	Fast Mode (I2C)	5
Set-Up Time for a Repeated START Condition	tSU;STA	4.7			μs	Standard Mode (I2C)	5
Set-Up Time for a Repeated START Condition	tSU;STA	0.6			μs	Fast Mode (I2C)	5
Set-Up Time for STOP Condition	tSU;STO	4			μs	Standard Mode (I2C)	5
Set-Up Time for STOP Condition	tSU;STO	0.6			μs	Fast Mode (I2C)	5
Data Valid Acknowledge Time	tVD;ACK			3.45	μs	Standard Mode (I2C)	5
Data Valid Acknowledge Time	tVD;ACK			0.9	μs	Fast Mode (I2C)	5
Data Valid Time	tVD;DAT			3.45	μs	Standard Mode (I2C)	5
Data Valid Time	tVD;DAT			0.9	μs	Fast Mode (I2C)	5
Data Set-Up Time	tSU;DAT	250			ns	Standard Mode (I2C)	5
Data Set-Up Time	tSU;DAT	100			ns	Fast Mode (I2C)	5
LOW Period of the SCL Clock	tLOW	4.7			μs	Standard Mode (I2C)	5
LOW Period of the SCL Clock	tLOW	1.3			μs	Fast Mode (I2C)	5
HIGH Period of the SCL Clock	tHIGH	4			μs	Standard Mode (I2C)	5
HIGH Period of the SCL Clock	tHIGH	0.6			μs	Fast Mode (I2C)	5
Fall Time of both SDA and SCL Signals	tf			300	ns	Standard Mode (I2C)	5

CAD (KiCad official)

Symbol: PI4IOE5V9555ZDEX
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: TQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: pi4ioe5v9555zdex-etched.step / pi4ioe5v9555zdex-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pi4ioe5v9555zdex.step / pi4ioe5v9555zdex.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Diodes Incorporated datasheet (15 pp, sha256 02db35904a0052ce, retrieved 2026-10-29, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF