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PI3HDMI301FFEX

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Diodes Incorporated Interface - Specialized, LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PI3HDMI301FFEX

Diodes Incorporated · Interface - Specialized · LQFP-80(12x12)

PI3HDMI301FFEX from Diodes Incorporated, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OC_S3 input Output buffer control bit 3 selecting output swing and pre-emphasis/de-emphasis, with internal pull-up.
2 SDA1 bidirectional Port 1 DDC data, 5V tolerant side band signal.
3 SCL1 bidirectional Port 1 DDC clock, 5V tolerant side band signal.
4 GND power_in Ground.
5 CLK-1 input Port 1 TMDS clock negative input with integrated 50-ohm termination.
6 CLK+1 input Port 1 TMDS clock positive input with integrated 50-ohm termination.
7 VDD power_in 3.3V power supply.
8 D0-1 input Port 1 TMDS data 0 negative input.
9 D0+1 input Port 1 TMDS data 0 positive input.
10 GND power_in Ground.
11 D1-1 input Port 1 TMDS data 1 negative input.
12 D1+1 input Port 1 TMDS data 1 positive input.
13 VDD power_in 3.3V power supply.
14 D2-1 input Port 1 TMDS data 2 negative input.
15 D2+1 input Port 1 TMDS data 2 positive input.
16 GND power_in Ground.
17 VDD power_in 3.3V power supply.
18 OC_S1 input Output buffer control bit 1 selecting output swing and pre-emphasis/de-emphasis, with internal pull-up.
19 OC_S0 input Output buffer control bit 0 selecting output swing and pre-emphasis/de-emphasis, with internal pull-up.
20 OC_S2 input Output buffer control bit 2 selecting output swing and pre-emphasis/de-emphasis, with internal pull-up.
21 S1 input Source input control selecting Port 1 when high.
22 S2 input Source input control selecting Port 2.
23 S3 input Source input control selecting Port 3.
24 GND power_in Ground.
25 D2+ output TMDS data 2 positive output, high impedance when disabled.
26 D2- output TMDS data 2 negative output, high impedance when disabled.
27 VDD power_in 3.3V power supply.
28 D1+ output TMDS data 1 positive output, high impedance when disabled.
29 D1- output TMDS data 1 negative output, high impedance when disabled.
30 GND power_in Ground.
31 D0+ output TMDS data 0 positive output, high impedance when disabled.
32 D0- output TMDS data 0 negative output, high impedance when disabled.
33 VDD power_in 3.3V power supply.
34 CLK+ output TMDS clock positive output, high impedance when disabled.
35 CLK- output TMDS clock negative output, high impedance when disabled.
36 GND power_in Ground.
37 GND power_in Ground.
38 SCL_Sink bidirectional Sink side DDC clock, 5V tolerant side band signal.
39 SDA_Sink bidirectional Sink side DDC data, 5V tolerant side band signal.
40 HPD_Sink input Sink side hot plug detector input; high means 5V power signal asserted from source to sink and EDID ready, low means not asserted or EDID not ready.
41 EQ_S0 input Equalizer control bit 0 with internal pull-up.
42 OE input Output enable, active LOW.
43 VDD power_in 3.3V power supply.
44 HPD3 output Port 3 HPD output.
45 SDA3 bidirectional Port 3 DDC data, 5V tolerant side band signal.
46 SCL3 bidirectional Port 3 DDC clock, 5V tolerant side band signal.
47 GND power_in Ground.
48 CLK-3 input Port 3 TMDS clock negative input.
49 CLK+3 input Port 3 TMDS clock positive input.
50 VDD power_in 3.3V power supply.
51 D0-3 input Port 3 TMDS data 0 negative input.
52 D0+3 input Port 3 TMDS data 0 positive input.
53 GND power_in Ground.
54 D1-3 input Port 3 TMDS data 1 negative input.
55 D1+3 input Port 3 TMDS data 1 positive input.
56 VDD power_in 3.3V power supply.
57 D2-3 input Port 3 TMDS data 2 negative input.
58 D2+3 input Port 3 TMDS data 2 positive input.
59 GND power_in Ground.
60 EQ_S1 input Equalizer control bit 1 with internal pull-up.
61 VDD power_in 3.3V power supply.
62 HPD2 output Port 2 HPD output.
63 SDA2 bidirectional Port 2 DDC data, 5V tolerant side band signal.
64 SCL2 bidirectional Port 2 DDC clock, 5V tolerant side band signal.
65 GND power_in Ground.
66 GND power_in Ground.
67 CLK-2 input Port 2 TMDS clock negative input.
68 CLK+2 input Port 2 TMDS clock positive input.
69 VDD power_in 3.3V power supply.
70 D0-2 input Port 2 TMDS data 0 negative input.
71 D0+2 input Port 2 TMDS data 0 positive input.
72 GND power_in Ground.
73 D1-2 input Port 2 TMDS data 1 negative input.
74 D1+2 input Port 2 TMDS data 1 positive input.
75 VDD power_in 3.3V power supply.
76 D2-2 input Port 2 TMDS data 2 negative input.
77 D2+2 input Port 2 TMDS data 2 positive input.
78 GND power_in Ground.
79 VDD power_in 3.3V power supply.
80 HPD1 output Port 1 HPD output.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package LQFP-80(12x12)
Category Interface ICs
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD 3.135 3.3 3.465 V 7
Operating free-air temperature TA 0 70 °C 7
Receiver peak-to-peak differential input voltage VID 150 1560 mVp-p TMDS differential pins 7
TMDS output termination voltage VDD 3.135 3.3 3.465 V TMDS differential pins 7
Termination resistance RT 45 50 55 ohm 7
Signaling rate 0.25 2.5 Gbps 7
LVTTL High-level input voltage (control pins) VIH 2 3.3 V Control pins; max printed as VDD 7
LVTTL Low-level input voltage (control pins) VIL 0 0.8 V Control pins; min printed as GND 7
DDC input voltage VI(DDC) 0 5.5 V min printed as GND 7
HPD_SINK High-level input voltage VIH 2 5.3 V Status pins HPD_SINK 7
HPD_SINK Low-level input voltage VIL 0 0.8 V Status pins HPD_SINK; min printed as GND 7
Storage Temperature -65 150 °C 7
Supply Voltage to Ground Potential -0.5 4 V 7
DC Input Voltage -0.5 3.3 V max printed as VDD 7
DC Output Current 120 mA 7
Power Dissipation 1 W 7
Supply Current ICC 200 mA VIH = VDD, VIL = VDD - 0.4V, RT = 50-ohm, VDD = 3.3V, Data Input = 1.65 Gbps HDMI data pattern, CLK Input = 165 MHz clock 9
Power Dissipation PD 660 mW 9
Standby Current ICCQ 8 mA OE = HIGH, S1 = S2 = S3 = LOW 9
Single-ended high-level output voltage VOH -10 10 mV VDD = 3.3V, RT = 50-ohm, Pre-emphasis/De-emphasis = 0dB; printed VDD-10 to VDD+10 9
Single-ended low-level output voltage VOL -600 -400 mV VDD = 3.3V, RT = 50-ohm, Pre-emphasis/De-emphasis = 0dB; printed VDD-600 to VDD-400 9
Single-ended output swing voltage Vswing 400 600 mV VDD = 3.3V, RT = 50-ohm, Pre-emphasis/De-emphasis = 0dB 9
Overshoot of output differential voltage VOD(O) 6 15 % VDD = 3.3V, RT = 50-ohm, Pre-emphasis/De-emphasis = 0dB; printed 6% and 15% of 2x Vswing 9
Undershoot of output differential voltage VOD(U) 12 25 % VDD = 3.3V, RT = 50-ohm, Pre-emphasis/De-emphasis = 0dB; printed 12% and 25% of 2x Vswing 9
Change in steady-state common-mode output voltage between logic states ΔVOC(SS) 0.5 5 mV VDD = 3.3V, RT = 50-ohm, Pre-emphasis/De-emphasis = 0dB 9
Short circuit output current /I(OS)/ 12 mA 9
Steady state output differential voltage VODE(SS) 560 840 mVp-p OC_Sx = GND, Data Input = 250 Mbps HDMI data pattern, CLK Input = 25 MHz clock 9
Peak-to-peak output differential voltage VODE(PP) 800 1200 mVp-p OC_Sx = GND, Data Input = 250 Mbps HDMI data pattern, CLK Input = 25 MHz clock 9
Single-ended input voltage under high impedance input or open input VI(open) -10 10 mV II = 10μA; printed VDD-10 to VDD+10 9
Input termination resistance RINT 45 50 55 ohm VIN = 2.9V 9
DDC input leakage current /Ilkg/ -50 50 μA VI = 5.5V 9
DDC input leakage current /Ilkg/ -10 10 μA VI = VDD 9
DDC Input/output capacitance CIO 7.5 pF VI = 0V 9
DDC Switch resistance RON 25 50 ohm IO = 3mA, VO = 0.4V 9
DDC Switch output voltage VPASS 1.5 2 2.5 V VI = 3.3V, II = 100μA 9
HPD TTL High-level output voltage VOH(TTL) 2.4 V IOH = -4mA 9
HPD TTL Low-level output voltage VOL(TTL) 0.4 V IOL = 4mA 9
Control pins High-level digital input current IIH -10 10 μA VIH = 2.0V or VDD 10
Control pins Low-level digital input current IIL -10 10 μA VIL = GND or 0.8V 10
HPD_SINK High-level digital input current IIH -50 50 μA VIH = 5.3V 10
HPD_SINK High-level digital input current IIH -10 10 μA VIH = 2.0V or VDD 10
HPD_SINK Low-level digital input current IIL -10 10 μA VIL = GND or 0.8V 10
Propagation delay tpd 2000 ps VDD = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 11
Differential output signal rise time (20% - 80%) tr 75 140 ps VDD = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 11
Differential output signal fall time (20% - 80%) tf 75 140 ps VDD = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 11
Pulse skew tsk(p) 10 50 ps VDD = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 11
Intra-pair differential skew tsk(D) 23 50 ps VDD = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 11
Inter-pair differential skew tsk(o) 100 ps VDD = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 11
Peak-to-peak output jitter from TMDS CLK channel residual jitter TCLKjit(pp) 15 30 ps pre-emphasis/de-emphasis = 0dB, Data Input = 1.65 Gbps HDMI data pattern, CLK Input = 165 MHz clock 11
Peak-to-peak output jitter from TMDS data residual jitter TDATAjit(pp) 18 50 ps pre-emphasis/de-emphasis = 0dB, Data Input = 1.65 Gbps HDMI data pattern, CLK Input = 165 MHz clock 11
Enable time ten 200 ns 11
Propagation delay DDC tpd(DDC) 0.4 2.5 ns CL = 10pF 11
Propagation delay HPD_SINK to active HPDx tpd(HPD) 2 6 ns CL = 10pF 11
Switch time port select to latest valid HPDx tsx(HPD) 3 6.5 ns CL = 10pF 11

CAD (KiCad official)

  • Symbol: PI3HDMI301FFEX
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: pi3hdmi301ffex-etched.step / pi3hdmi301ffex-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pi3hdmi301ffex.step / pi3hdmi301ffex.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (16 pp, sha256 2ffd0025e4a2dea9, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF