component

PGA5807ARGCT

Public Made by Adom

by adom

Texas Instruments Analog Front End (AFE), VQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionpga5807argctfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

PGA5807ARGCT

Texas Instruments · Analog Front End (AFE) · VQFN-64(9x9)

PGA5807ARGCT from Texas Instruments, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INP1 input Analog input for channel 1; the dc input common-mode can be 2.1 V ± 200 mV.
2 INM1 input Complementary analog input for channel 1; the dc input common-mode can be 2.1 V ± 200 mV.
3 INP2 input Analog input for channel 2; the dc input common-mode can be 2.1 V ± 200 mV.
4 INM2 input Complementary analog input for channel 2; the dc input common-mode can be 2.1 V ± 200 mV.
5 INP3 input Analog input for channel 3; the dc input common-mode can be 2.1 V ± 200 mV.
6 INM3 input Complementary analog input for channel 3; the dc input common-mode can be 2.1 V ± 200 mV.
7 INP4 input Analog input for channel 4; the dc input common-mode can be 2.1 V ± 200 mV.
8 INM4 input Complementary analog input for channel 4; the dc input common-mode can be 2.1 V ± 200 mV.
9 INP5 input Analog input for channel 5; the dc input common-mode can be 2.1 V ± 200 mV.
10 INM5 input Complementary analog input for channel 5; the dc input common-mode can be 2.1 V ± 200 mV.
11 INP6 input Analog input for channel 6; the dc input common-mode can be 2.1 V ± 200 mV.
12 INM6 input Complementary analog input for channel 6; the dc input common-mode can be 2.1 V ± 200 mV.
13 INP7 input Analog input for channel 7; the dc input common-mode can be 2.1 V ± 200 mV.
14 INM7 input Complementary analog input for channel 7; the dc input common-mode can be 2.1 V ± 200 mV.
15 INP8 input Analog input for channel 8; the dc input common-mode can be 2.1 V ± 200 mV.
16 INM8 input Complementary analog input for channel 8; the dc input common-mode can be 2.1 V ± 200 mV.
17 AVDD power_in Analog supply pin at 3.3 V; recommended AVDD range is 3.15 V to 3.6 V.
18 VBIAS passive Bias voltage decoupling pin; bypass to ground with a 1-µF capacitor or greater.
19 AVSS power_in Analog ground pin.
20 AVSS power_in Analog ground pin.
21 NC unconnected Unused pin; do not connect.
22 NC unconnected Unused pin; do not connect.
23 NC unconnected Unused pin; do not connect.
24 AVSS power_in Analog ground pin.
25 NC unconnected Unused pin; do not connect.
26 NC unconnected Unused pin; do not connect.
27 AVSS power_in Analog ground pin.
28 AVDD power_in Analog supply pin at 3.3 V; recommended AVDD range is 3.15 V to 3.6 V.
29 AVSS power_in Analog ground pin.
30 NC unconnected Unused pin; do not connect.
31 AVDD power_in Analog supply pin at 3.3 V; recommended AVDD range is 3.15 V to 3.6 V.
32 NC unconnected Unused pin; do not connect.
33 OUTM8 output Complementary output pin for channel 8; the common-mode voltage is 0.95 V.
34 OUTP8 output Output pin for channel 8; the common-mode voltage is 0.95 V.
35 OUTM7 output Complementary output pin for channel 7; the common-mode voltage is 0.95 V.
36 OUTP7 output Output pin for channel 7; the common-mode voltage is 0.95 V.
37 OUTM6 output Complementary output pin for channel 6; the common-mode voltage is 0.95 V.
38 OUTP6 output Output pin for channel 6; the common-mode voltage is 0.95 V.
39 OUTM5 output Complementary output pin for channel 5; the common-mode voltage is 0.95 V.
40 OUTP5 output Output pin for channel 5; the common-mode voltage is 0.95 V.
41 OUTM4 output Complementary output pin for channel 4; the common-mode voltage is 0.95 V.
42 OUTP4 output Output pin for channel 4; the common-mode voltage is 0.95 V.
43 OUTM3 output Complementary output pin for channel 3; the common-mode voltage is 0.95 V.
44 OUTP3 output Output pin for channel 3; the common-mode voltage is 0.95 V.
45 OUTM2 output Complementary output pin for channel 2; the common-mode voltage is 0.95 V.
46 OUTP2 output Output pin for channel 2; the common-mode voltage is 0.95 V.
47 OUTM1 output Complementary output pin for channel 1; the common-mode voltage is 0.95 V.
48 OUTP1 output Output pin for channel 1; the common-mode voltage is 0.95 V.
49 AVDD power_in Analog supply pin at 3.3 V; recommended AVDD range is 3.15 V to 3.6 V.
50 AVSS power_in Analog ground pin.
51 GAIN0 input When RESET is high, programs the PGA gain per GAIN[2:0] in Table 2; use 3.3-V logic.
52 GAIN1 input When RESET is high, programs the PGA gain per GAIN[2:0] in Table 2; use 3.3-V logic.
53 PDN input Partial power-down control for the entire device with an internal 20-kΩ pull-down; active high; use 3.3-V logic.
54 AVSS power_in Analog ground pin.
55 SDOUT output Serial interface readout pin; logic high output is AVDD and logic low output is 0 V.
56 GAIN2 input When RESET is high, programs the PGA gain per GAIN[2:0] in Table 2; use 3.3-V logic.
57 SEN input Serial interface enable for channels 1 to 8, active low, with an internal 20-kΩ pull-up; use 3.3-V logic.
58 SDATA input Serial interface data input with an internal 20-kΩ pull-down; when RESET is high, setting it high selects the 60-MHz antialias filter corner; use 3.3-V logic.
59 SCLK input Serial interface clock input with an internal 20-kΩ pull-down; use 3.3-V logic.
60 RESET input Logic hardware reset pin, activated by a positive pulse; use 3.3-V logic.
61 AVSS power_in Analog ground pin.
62 AVDD power_in Analog supply pin at 3.3 V; recommended AVDD range is 3.15 V to 3.6 V.
63 AVDD power_in Analog supply pin at 3.3 V; recommended AVDD range is 3.15 V to 3.6 V.
64 AVDD power_in Analog supply pin at 3.3 V; recommended AVDD range is 3.15 V to 3.6 V.
65 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64(9x9)
Category Data Acquisition
Pins 65

CAD (KiCad official)

  • Symbol: PGA5807ARGCT
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: pga5807argct-etched.step / pga5807argct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pga5807argct.step / pga5807argct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 448ac1bcb2c4b386, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF