component

PGA460TPWR

Public Made by Adom

by adom

Texas Instruments ADC/DAC - Specialized, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionpga460tpwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

PGA460TPWR

Texas Instruments · ADC/DAC - Specialized · TSSOP-16

PGA460TPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground; absolute maximum ground voltage is -0.3 to 0.3 V and recommended -0.1 to 0.1 V.
2 INP input Positive transducer receive input; recommended operating range -0.1 to 0.9 V (abs max -0.3 to 2 V).
3 INN input Negative transducer receive input; recommended operating range -0.1 to 0.9 V (abs max -0.3 to 2 V).
4 GND power_in Ground; absolute maximum ground voltage is -0.3 to 0.3 V and recommended -0.1 to 0.1 V.
5 OUTA output Transducer driver output A (low-side driver), rated -0.3 to 30 V with 500 mA maximum sink current.
6 GNDP power_in Power ground for the output drivers; recommended -0.1 to 0.1 V.
7 OUTB output Transducer driver output B (low-side driver), rated -0.3 to 30 V with 500 mA maximum sink current.
8 IO bidirectional Time-command interface data input and output (open-drain with internal 10-kΩ pullup, also UART), rated -0.3 to 30 V.
9 TEST bidirectional Test output pin; its level at power-up selects 3.3 V (low) or 5 V (high) digital outputs, and it can output internal test-mux signals; -0.3 to 5.5 V.
10 TXD output USART interface transmit output, 3.3 V or 5 V CMOS level depending on the TEST pin level at power-up.
11 RXD input USART interface receive input; recommended -0.1 V to VIOREG (abs max -0.3 to 5.5 V).
12 SCLK input USART synchronous-mode clock input; recommended -0.1 V to VIOREG (abs max -0.3 to 5.5 V).
13 DECPL output Decoupling transistor gate drive output, rated -0.3 to 5.5 V.
14 IOREG power_out I/O buffer voltage regulator capacitor pin, rated -0.3 to 5.5 V.
15 VPWR power_in Power-supply voltage input; recommended 6 to 15 V for transformer topology and 6 to 28 V for direct drive (abs max 30 V).
16 AVDD power_out Analog voltage-regulator capacitor pin, rated -0.3 to 2 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VPWR input voltage VPWR -0.3 30 V 5
IO input voltage IO -0.3 30 V 5
INP, INN input voltage INP, INN -0.3 2 V 5
TEST, SCLK, RXD input voltage -0.3 5.5 V 5
AVDD output voltage AVDD -0.3 2 V 5
IOREG, DECPL, TEST, TXD output voltage -0.3 5.5 V 5
OUTA, OUTB output voltage -0.3 30 V 5
Ground voltage GNDP, GND -0.3 0.3 V 5
Sink current OUTA, OUTB 500 mA 5
Operating junction temperature TJ -40 125 °C 5
Storage temperature Tstg -40 125 °C 5
Supply input, transformer topology VVPWR_XF 6 15 V 5
Supply input, direct drive topology VVPWR_DD 6 28 V 5
IO pin voltage VIO -0.1 V max is VPWR 5
Transducer receive input INP, INN VINx -0.1 0.9 V 5
Digital I/O pins RXD, TEST, SCLK VDIG_IO -0.1 V max is VIOREG 5
Ground pins GNDP, GND VGND -0.1 0.1 V 5
VPWR input current, low power mode ILPM 500 µA Low Power Mode Enabled 5
VPWR input current during burst IBURST 500 mA During Ultrasonic Burst 5
Operating free-air temperature TA -40 105 °C 5
Operating junction temperature TJ -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 96.1 °C/W PW (TSSOP) 16 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 24.6 °C/W 6
Junction-to-board thermal resistance RθJB 42 °C/W 6
Internal analog supply voltage VAVDD 1.74 1.8 1.9 V IAVDD = 5 mA 6
Digital IO supply voltage 3.3 V VIOREG_33 2.95 3.3 3.65 V VTEST = 0 V during power-up ; IIOREG = 2 mA 6
Digital IO supply voltage 5 V VIOREG_50 4.45 5 5.65 V VTEST ≥ 2 V during power-up ; IIOREG = 2 mA; VVPWR > 7.5 V 6
AVDD current limit ILIM_AVDD 40 150 mA AVDD short to GND 6
IOREG current limit ILIM_IOREG 10 50 mA IOREG short to GND 6
AVDD undervoltage threshold VUV_AVDD 1.29 1.53 V 6
VPWR undervoltage threshold VUV_VPWR 5.25 6 V 6
VPWR overvoltage threshold VOV_VPWR 11 12.3 15 V VPWR_OV_TH = 0x0 6
VPWR overvoltage threshold VOV_VPWR 16 17.7 21 V VPWR_OV_TH = 0x1 6
VPWR overvoltage threshold VOV_VPWR 21.5 22.8 27 V VPWR_OV_TH = 0x2 6
VPWR overvoltage threshold VOV_VPWR 27 28.3 31 V VPWR_OV_TH = 0x3 6
Driver MOSFET on resistance RDSONDRV 4.8 8 Ω IDRAIN = 500 mA: TA = 105°C; DIS_CL=1 6
Driver leakage current ILEAK_DRV -1 1 µA VOUTA,VOUTB=14 V 6
Current clamp, minimum code ICLAMP_DRV_0 15 50 75 mA VVPWR>7 V;CURR_LIM1 = CURR_LIM2= 0 6
Current clamp, maximum code ICLAMP_DRV_63 450 500 570 mA VVPWR>7 V;CURR_LIM1 = CURR_LIM2= 63 6
Current clamp step size ISTEP_SIZE_CLAMP_DRV 5.2 7.2 9.2 mA 6
Switching frequency low fSW_LOW 30 80 kHz FREQ_SHIFT = 0 7
Switching frequency high fSW_HIGH 180 480 kHz FREQ_SHIFT = 1 7
Gain adjustment step size GAINSTEP_SIZE_RCV 0.2 0.5 0.8 dB 7
Gain thermal drift GAINTHRM_DRFT_RCV -3.5 3.5 % FSW = 30 kHz; TA = -40°C to +105°C; Gain = 58.5 7
Band-pass filter band width BWBPF 2 8 kHz 7
Low-pass filter cutoff frequency FREQCUTOFF_LPF 1 4 kHz 7
Temperature sensor range TRANGE_SENSE -40 125 °C 7
IO pullup resistance RPU_IO 4 10 16 kΩ IO pin 8
IO current limit ILIM_IO 40 250 mA Short to VPWR 8
RX pullup resistance RPU_DIGIO_RX 90 100 160 kΩ RX pin 8
SCLK pulldown resistance RPU_DIGIO_SCLK 80 100 130 kΩ SCLK pin 8
Core frequency fCORE_CLK 15.5 16 16.5 MHz At Room Temperature (25°C) 9
Core frequency accuracy ACCCORE_CLK -4 4 % Across Operating Temperature Range (-40°C to 105°C) 9
TCI bit period tBIT_TCI 225 300 375 µs 8
UART baud rate BaudUART 2.4 19.2 131.5 kbps 9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper • The analog drive pins can be high-current, high-voltage, or both and therefore the design limitation of the OUTA and OUTB pins is based on the copper trace profile. The driver pins are recommended t 111

CAD (KiCad official)

  • Symbol: PGA460TPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: pga460tpwr-etched.step / pga460tpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pga460tpwr.step / pga460tpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (121 pp, sha256 0c398c00955b72e2, retrieved 2026-10-23, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF