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PGA2500IDBR

Public Made by Adom

by adom

Texas Instruments Operational Amplifier, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PGA2500IDBR

Texas Instruments · Operational Amplifier · SSOP-28-208mil

PGA2500IDBR from Texas Instruments, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPO1 output General-purpose CMOS logic output, controlled via the serial port (data bit for GPO1).
2 GPO2 output General-purpose CMOS logic output, controlled via the serial port (data bit for GPO2).
3 GPO3 output General-purpose CMOS logic output, controlled via the serial port (data bit for GPO3).
4 GPO4 output General-purpose CMOS logic output, controlled via the serial port (data bit for GPO4).
5 OVR output Active-high CMOS over-range output, forced high when output exceeds the threshold set by the OL bit (5.1VRMS or 4.0VRMS differential).
6 DGND power_in Digital ground.
7 DCEN input DC servo enable input, active low.
8 0dB input Unity gain enable input, active high; overrides serial port gain settings while high.
9 ZCEN input Zero crossing detector enable input, active high; low disables detection so gain changes occur immediately.
10 SDI input Serial data input, sampled on the rising edge of SCLK, used to write the serial port register.
11 CS input Chip select and word latch clock input, active low; control word latched on low-to-high transition.
12 SCLK input Serial data clock input, up to 6.25MHz, clocking data into SDI and out of SDO.
13 SDO tri_state Serial data output clocked on the falling edge of SCLK, for read-back or daisy-chaining; high impedance when CS is high.
14 VD− power_in −5V digital supply (−4.75V to −5.25V operating).
15 VA− power_in −5V analog supply (−4.75V to −5.25V operating).
16 VOUT− output Inverting analog output, designed to drive a 600Ω differential load.
17 VOUT+ output Non-inverting analog output, designed to drive a 600Ω differential load.
18 VA+ power_in +5V analog supply (+4.75V to +5.25V operating).
19 VA+ power_in +5V analog supply (+4.75V to +5.25V operating).
20 VA− power_in −5V analog supply (−4.75V to −5.25V operating).
21 CS22 passive DC servo capacitor #2, terminal 2; capacitor connects between pins 22 and 21, 1µF recommended, up to 4.7µF.
22 CS21 passive DC servo capacitor #2, terminal 1; capacitor connects between pins 22 and 21, 1µF recommended, up to 4.7µF.
23 CS12 passive DC servo capacitor #1, terminal 2; capacitor connects between pins 24 and 23, 1µF recommended, up to 4.7µF.
24 CS11 passive DC servo capacitor #1, terminal 1; capacitor connects between pins 24 and 23, 1µF recommended, up to 4.7µF.
25 VCOMIN input Common mode voltage input, 0V to +2.5V, DC-biasing the PGA output and input.
26 VIN− power_in Inverting analog input; AC coupling recommended and at least 50pF to analog ground recommended.
27 VIN+ power_in Non-inverting analog input; AC coupling recommended and at least 50pF to analog ground recommended.
28 AGND power_in Analog ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-28-208mil
Category Operational Amplifier/Comparator
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VA+ VA+ 5.5 V 2
Supply Voltage VA− VA− -5.5 V 2
Supply Voltage VD− VD− -5.5 V 2
Operating Temperature Range -40 85 °C 2
Storage Temperature Range -60 150 °C 2
Operating Voltage VA+ VA+ 4.75 5 5.25 V 3
Operating Voltage VA− VA− -4.75 -5 -5.25 V 3
Operating Voltage VD− VD− -4.75 -5 -5.25 V 3
Gain Error 0.5 dB All Gain Settings 3
Output Offset Voltage 0.04 1 mV DC Servo On, Any Gain 3
Input Referred Offset 1 mV DC Servo Off, Gain = 30dB 3
High-Level Input Voltage VIH 2 V 3
Low-Level Input Voltage VIL -0.3 0.8 V 3
Low-Level Output Voltage VOL 0.4 V IO = −3.2mA 3
Input Leakage Current IIN 2 10 µA 3
Serial Clock Frequency fSCLK 0 6.25 MHz 3
SCLK Pulse Width Low tPH 80 ns 3
SCLK Pulse Width High tPL 80 ns 3
SDI Setup Time tSDS 20 ns 3
SDI Hold Time tSDH 20 ns 3
CS Falling to SCLK Rising tCSCR 90 ns 3
SCLK Falling to CS Rising tCFCS 35 ns 3
CS Low to SDO Active tCSO 35 ns 3
SCLK Falling to SDO Data Valid tCFDO 60 ns 3
CS High to SDO High Impedance tCSZ 100 ns 3
Quiescent Current IA+ IA+ 30 40 mA VA+ = +5V 3
Quiescent Current IA− IA− 30 40 mA VA− = −5V 3
Quiescent Current ID− ID− 1 2 mA VD− = −5V 3
Step Size 1 dB Gain = 10dB through 65dB 3
Input Resistance Per Input Pin 4600 Ω 3
Input Resistance Differential 9200 Ω 3

CAD (KiCad official)

  • Symbol: PGA2500IDBR
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: pga2500idbr-etched.step / pga2500idbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pga2500idbr.step / pga2500idbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 e6f66a2607f1e19b, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF