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PGA205AU
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Texas Instruments Programmable / Variable Gain Amplifiers (PGA/VGA), SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# PGA205AU++**Texas Instruments** · Programmable / Variable Gain Amplifiers (PGA/VGA) · SOIC-16-300mil++PGA205AU from Texas Instruments, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VO1 | output | Pin labeled VO1 in the pin configuration and block diagram; the datasheet gives no electrical limits or functional description for this pin. |+| 2 | NC | unconnected | No internal connection. |+| 3 | NC | unconnected | No internal connection. |+| 4 | V-IN | power_in | Inverting analog input; each input is individually protected for up to ±40V, and an input bias current return path must be provided. |+| 5 | V+IN | power_in | Non-inverting analog input; each input is individually protected for up to ±40V, and an input bias current return path must be provided. |+| 6 | VOS Adjust | passive | Input-stage offset trim terminal, used with the optional trim circuit of Figure 3 to adjust only the input-stage offset (about ±250µV trim range), not system or sensor offset. |+| 7 | VOS Adjust | passive | Input-stage offset trim terminal, used with the optional trim circuit of Figure 3 to adjust only the input-stage offset (about ±250µV trim range), not system or sensor offset. |+| 8 | V- | power_in | Negative power supply; the device operates from ±4.5V to ±18V, with a absolute maximum supply of ±18V. |+| 9 | VO2 | output | Pin labeled VO2 in the pin configuration and block diagram; the datasheet gives no electrical limits or functional description for this pin. |+| 10 | Ref | input | Output reference terminal, normally grounded, that must be a low-impedance connection because a 5Ω series resistance degrades CMR to about 80dB at G=1. |+| 11 | VO | output | Amplifier output, which must be connected to Feedback (pin 12) for proper operation; the output is short-circuit protected to ground (continuous rating). |+| 12 | Feedback | input | Output feedback connection that must be tied to output pin 11 for proper operation, and can be used to sense the output voltage directly at the load. |+| 13 | V+ | power_in | Positive power supply; the device operates from ±4.5V to ±18V, with an absolute maximum supply of ±18V. |+| 14 | Dig. Ground | power_in | Digital ground reference for the A0/A1 logic inputs, which may be connected to any potential from V- up to 4V below V+ and is normally connected to ground. |+| 15 | A0 | input | Gain-select logic input (TTL/CMOS compatible) where a logic 1 is defined as more than 2V above digital ground (pin 14), and inputs are not latched. |+| 16 | A1 | input | Gain-select logic input (TTL/CMOS compatible) where a logic 1 is defined as more than 2V above digital ground (pin 14), and inputs are not latched. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16-300mil |+| Category | Amplifiers/Comparators |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `PGA205AU`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)+- 3D model files: `pga205au-etched.step` / `pga205au-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pga205au.step` / `pga205au.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/pga204) (20 pp, sha256 `a49dcc8c5d3928e5`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/pga205au-datasheet.pdf)
page.jsonadded+249@@ -0,0 +1,249 @@+{+ "slug": "pga205au",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Programmable / Variable Gain Amplifiers (PGA/VGA), SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "amplifiers-comparators",+ "pga205au",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "pga205au.kicad_sym",+ "pga205au.kicad_mod",+ "pga205au.glb",+ "pga205au.step",+ "pga205au.lbr",+ "docs/hero.png",+ "docs/pga205au-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "pga205au-hero.glb",+ "pga205au-hero.overlay.json"+ ],+ "component": {+ "mpn": "PGA205AU",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16-300mil",+ "pin_count": 16,+ "category": "Amplifiers/Comparators",+ "subcategory": "Programmable / Variable Gain Amplifiers (PGA/VGA)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/pga204",+ "parts": {+ "symbol": "pga205au.kicad_sym",+ "footprint": "pga205au.kicad_mod",+ "model_3d": "pga205au-hero.glb",+ "model_3d_plain": "pga205au.glb",+ "model_3d_step": "pga205au-etched.step",+ "model_3d_step_plain": "pga205au.step",+ "lbr": "pga205au.lbr"+ },+ "distributor_links": {+ "lcsc": "C1849435",+ "digikey": "296-45014-5-ND",+ "mouser": "595-PGA205AU"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T03:33:00Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-45014-5-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-PGA205AU",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VO1",+ "type": "output",+ "description": "Pin labeled VO1 in the pin configuration and block diagram; the datasheet gives no electrical limits or functional description for this pin."+ },+ {+ "number": "2",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "4",+ "name": "V-IN",+ "type": "power_in",+ "description": "Inverting analog input; each input is individually protected for up to ±40V, and an input bias current return path must be provided."+ },+ {+ "number": "5",+ "name": "V+IN",+ "type": "power_in",+ "description": "Non-inverting analog input; each input is individually protected for up to ±40V, and an input bias current return path must be provided."+ },+ {+ "number": "6",+ "name": "VOS Adjust",+ "type": "passive",+ "description": "Input-stage offset trim terminal, used with the optional trim circuit of Figure 3 to adjust only the input-stage offset (about ±250µV trim range), not system or sensor offset."+ },+ {+ "number": "7",+ "name": "VOS Adjust",+ "type": "passive",+ "description": "Input-stage offset trim terminal, used with the optional trim circuit of Figure 3 to adjust only the input-stage offset (about ±250µV trim range), not system or sensor offset."+ },+ {+ "number": "8",+ "name": "V–",+ "type": "power_in",+ "description": "Negative power supply; the device operates from ±4.5V to ±18V, with a absolute maximum supply of ±18V."+ },+ {+ "number": "9",+ "name": "VO2",+ "type": "output",+ "description": "Pin labeled VO2 in the pin configuration and block diagram; the datasheet gives no electrical limits or functional description for this pin."+ },+ {+ "number": "10",+ "name": "Ref",+ "type": "input",+ "description": "Output reference terminal, normally grounded, that must be a low-impedance connection because a 5Ω series resistance degrades CMR to about 80dB at G=1."+ },+ {+ "number": "11",+ "name": "VO",+ "type": "output",+ "description": "Amplifier output, which must be connected to Feedback (pin 12) for proper operation; the output is short-circuit protected to ground (continuous rating)."+ },+ {+ "number": "12",+ "name": "Feedback",+ "type": "input",+ "description": "Output feedback connection that must be tied to output pin 11 for proper operation, and can be used to sense the output voltage directly at the load."+ },+ {+ "number": "13",+ "name": "V+",+ "type": "power_in",+ "description": "Positive power supply; the device operates from ±4.5V to ±18V, with an absolute maximum supply of ±18V."+ },+ {+ "number": "14",+ "name": "Dig. Ground",+ "type": "power_in",+ "description": "Digital ground reference for the A0/A1 logic inputs, which may be connected to any potential from V- up to 4V below V+ and is normally connected to ground."+ },+ {+ "number": "15",+ "name": "A0",+ "type": "input",+ "description": "Gain-select logic input (TTL/CMOS compatible) where a logic 1 is defined as more than 2V above digital ground (pin 14), and inputs are not latched."+ },+ {+ "number": "16",+ "name": "A1",+ "type": "input",+ "description": "Gain-select logic input (TTL/CMOS compatible) where a logic 1 is defined as more than 2V above digital ground (pin 14), and inputs are not latched."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet does not describe the function or electrical limits of pins VO1 (pin 1) and VO2 (pin 9; The datasheet's pin configuration (page 5) lists pins 2 and 3 as NC (no internal connection). They a; The pin-to-number mapping was reconstructed from the top-view pin configuration on page 5 and cross-",+ "1/16 pins cited to the wrong page (name found elsewhere): ['5:V+IN@p2']"+ ],+ "pages_sent": 20,+ "cost_usd": 0.1107,+ "at": "2026-10-08T03:32:43"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/pga204",+ "pages": 20,+ "sha256": "a49dcc8c5d3928e5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "pga205au.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "pga205au-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0d197ab0e68b151050d715307d87bbeff5d0bb37b2a3574cd9cd42f4550a80dc",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}