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PGA116AIPWR

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Texas Instruments Programmable / Variable Gain Amplifiers (PGA/VGA), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentamplifiers-comparatorspga116aipwrfactory-2.0.0extractor-text

Verified PGA116AIPWR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: PGA116AIPWR · TSSOP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 61-page datasheet
  • ✓distributor: lcsc C2863769, digikey 296-23772-2-ND, mouser 595-PGA116AIPWR
  • ✓family: TSSOP-20_4.4x6.5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-txji1d8y/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ pga116aipwr.kicad_sym✓ pga116aipwr.kicad_mod✓ pga116aipwr.step
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Ray Publish 0.1.0 396d1cf 4h ago

PGA116AIPWR

Texas Instruments · Programmable / Variable Gain Amplifiers (PGA/VGA) · TSSOP-20

PGA116AIPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog supply voltage (2.2 V to 5.5 V).
2 CH5 input Input MUX channel 5.
3 CH4 input Input MUX channel 4.
4 CH3 input Input MUX channel 3.
5 CH2 input Input MUX channel 2.
6 CH1 input Input MUX channel 1.
7 VCAL/CH0 input Input MUX channel 0 and VCAL input; connect to a low-impedance external reference to use the internal calibration channels, loaded with 100 kΩ (typical) when CAL2 or CAL3 is selected, otherwise high impedance.
8 VREF power_in Reference input for VOUT offset shift or midsupply referencing; must be a low-impedance reference capable of sourcing and sinking at least 2 mA or connected to GND.
9 VOUT output Analog voltage output; when AVDD < DVDD, VOUT is clamped to AVDD + 300 mV.
10 CH7 input Input MUX channel 7.
11 CH8 input Input MUX channel 8.
12 CH9 input Input MUX channel 9.
13 ENABLE input Hardware enable pin; logic low puts the part into Shutdown mode (IQ < 1 μA).
14 GND power_in Ground pin.
15 SCLK input Clock input for SPI serial interface.
16 DIN input Data input for SPI serial interface; contains a weak 10-μA internal pulldown current source to allow daisy-chain configurations.
17 DOUT output Data output for SPI serial interface; goes to high-Z state when CS goes high for standard SPI interface.
18 CS input Chip select line for SPI serial interface.
19 DVDD power_in Digital and op amp output stage supply voltage (2.2 V to 5.5 V); should be bypassed with a 0.1-μF ceramic capacitor and must supply the digital and output stage load current.
20 CH6 input Input MUX channel 6.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Amplifiers/Comparators
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage 7 V 5
Signal input terminals current -10 10 mA 5
Operating temperature -40 125 °C 5
Junction temperature 150 °C 5
Storage temperature -65 150 °C 5
Analog supply voltage AVDD AVDD 2.2 5 5.5 V 5
Digital supply voltage DVDD DVDD 2.2 5 5.5 V 5
Operating free-air temperature -40 25 125 °C 5
Input offset voltage VOS -100 25 100 μV AVDD = DVDD = 5 V, VREF = VIN = AVDD/2, VCM = 2.5 V 6
Input offset voltage VOS -325 75 325 μV AVDD = DVDD = 5 V, VREF = VIN = AVDD/2, VCM = 4.5 V 6
Offset voltage drift vs temperature dVOS/dT 0.35 1.2 μV/°C AVDD = DVDD = 5 V, VCM = 2.5 V, TA = -40°C to 125°C 6
Offset voltage drift vs temperature dVOS/dT 0.15 0.9 μV/°C AVDD = DVDD = 5 V, VCM = 2.5 V, TA = -40°C to 85°C 6
Offset voltage drift vs temperature dVOS/dT 0.6 1.8 μV/°C AVDD = DVDD = 5 V, VCM = 4.5 V, TA = -40°C to 125°C 6
Offset voltage drift vs temperature dVOS/dT 0.3 1.3 μV/°C AVDD = DVDD = 5 V, VCM = 4.5 V, TA = -40°C to 85°C 6
Offset voltage vs power supply (PSRR) PSRR 5 20 μV/V AVDD = DVDD = 2.2 V to 5.5 V, VCM = 0.5 V, VREF = VIN = AVDD/2 6
Offset voltage vs power supply (PSRR) PSRR 5 40 μV/V AVDD = DVDD = 2.2 V to 5.5 V, VCM = 0.5 V, VREF = VIN = AVDD/2, TA = -40°C to 125°C 6
Input on-channel current (Ch0, Ch1) IIN -5 1.5 5 nA VREF = VIN = AVDD/2 6
Nominal gain, binary gains 1 128 Binary gains: 1, 2, 4, 8, 16, 32, 64, 128 6
Nominal gain, scope gains 1 200 Scope gains: 1, 2, 5, 10, 20, 50, 100, 200 6
DC gain error 0.006 0.1 % G = 1, VOUT = GND + 85 mV to DVDD, 85 mV 6
DC gain error 0.1 % 1 < G ≤ 32, VOUT = GND + 85 mV to DVDD, 85 mV 6
DC gain error 0.3 % G ≥ 50, VOUT = GND + 85 mV to DVDD, 85 mV 6
Input off-channel current (Ch0, Ch1) ILKG -1 0.05 1 nA VREF = GND, VOFF-CHANNEL = AVDD/2, VON-CHANNEL = AVDD/2, 0.1 V 7
Short circuit current ISC -30 60 mA 7
Operating voltage range AVDD AVDD 2.2 5.5 V 7
Operating voltage range DVDD DVDD 2.2 5.5 V 7
Quiescent current analog IQA 0.33 0.45 mA IO = 0, G = 1, VOUT = VREF 7
Quiescent current analog over temperature IQA 0.45 mA TA = -40°C to 125°C 7
Quiescent current digital IQD 0.75 1.2 mA IO = 0, G = 1, VOUT = VREF, SCLK at 10 MHz, CS = Logic 0, DIO or DIN = Logic 0 7
Quiescent current digital over temperature IQD 1.2 mA IO = 0, G = 1, VOUT = VREF, SCLK at 10 MHz, TA = -40°C to 125°C, CS = Logic 0, DIO or DIN = Logic 0 7
Digital input leakage current -1 1 μA SCLK and CS only 8
Thermal resistance junction-to-ambient RθJA 100.3 °C/W PW (TSSOP-20) package 5
Thermal resistance junction-to-case (top) RθJC(top) 36.9 °C/W PW (TSSOP-20) package 5
Thermal resistance junction-to-board RθJB 50.6 °C/W PW (TSSOP-20) package 5
Junction-to-top characterization parameter ψJT 2.6 °C/W PW (TSSOP-20) package 5
Junction-to-board characterization parameter ψJB 50.2 °C/W PW (TSSOP-20) package 5

CAD (KiCad official)

  • Symbol: PGA116AIPWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: pga116aipwr-etched.step / pga116aipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pga116aipwr.step / pga116aipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (61 pp, sha256 e9dc65d9f2eda88a, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF