component
PESD5V0L6US
Public Made by Adomby adom
TECH PUBLIC ESD And Surge Protection (TVS/ESD), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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PESD5V0L6US
TECH PUBLIC · ESD And Surge Protection (TVS/ESD) · SOP-8
PESD5V0L6US from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | ESD-protected line 1, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 2 | I/O2 | passive | ESD-protected line 2, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 3 | I/O3 | passive | ESD-protected line 3, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 4 | I/O4 | passive | ESD-protected line 4, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 5 | I/O5 | passive | ESD-protected line 5, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 6 | GND | power_in | Common ground node of the diode array, tied internally to pin 7 in the schematic. |
| 7 | GND | power_in | Common ground node of the diode array, tied internally to pin 6 in the schematic. |
| 8 | I/O6 | passive | ESD-protected line 6, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | Circuit Protection |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
PESD5V0L6US - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
pesd5v0l6us-etched.step/pesd5v0l6us-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pesd5v0l6us.step/pesd5v0l6us.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (4 pp, sha256
2316c1d58d864cbd, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# PESD5V0L6US
**TECH PUBLIC** · ESD And Surge Protection (TVS/ESD) · SOP-8
PESD5V0L6US from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | ESD-protected line 1, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 2 | I/O2 | passive | ESD-protected line 2, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 3 | I/O3 | passive | ESD-protected line 3, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 4 | I/O4 | passive | ESD-protected line 4, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 5 | I/O5 | passive | ESD-protected line 5, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
| 6 | GND | power_in | Common ground node of the diode array, tied internally to pin 7 in the schematic. |
| 7 | GND | power_in | Common ground node of the diode array, tied internally to pin 6 in the schematic. |
| 8 | I/O6 | passive | ESD-protected line 6, diode-clamped to the common ground node (any I/O to GND, VRWM 5V max, CJ 3pF max). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | Circuit Protection |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `PESD5V0L6US`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `pesd5v0l6us-etched.step` / `pesd5v0l6us-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pesd5v0l6us.step` / `pesd5v0l6us.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590237898487734272) (4 pp, sha256 `2316c1d58d864cbd`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/pesd5v0l6us-datasheet.pdf)